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user?s manual v850/sc1 tm , v850/sc2 tm , v850/sc3 tm 32-bit single-chip microcontrollers hardware pd703068y pd703069y pd703088y pd703089y pd70f3089y printed in japan document no. u15109ej3v0ud00 (3rd edition) date published june 2002 n cp(k) ? 2001, 2002
2 user?s manual u15109ej3v0ud [memo]
user?s manual u15109ej3v0ud 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. v850 series, v850/sc1, v850/sc2, v850/sc3, iebus, and inter equipment bus are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries.
4 user ? s manual u15109ej3v0ud the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed: pd70f3089y the customer must judge the need for license: pd703068y, 703069y, 703088y, 703089y m8e 00. 4 the information in this document is current as of may, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual pr operty rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual pr operty rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": tr ansportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if cust omers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?
user ? s manual u15109ej3v0ud 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j02.4 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290
6 user?s manual u15109ej3v0ud major revisions in this edition (1/4) page description throughout ? deletion of indication ?under development? for the following products (developed) pd703068ygj- -uen, 703069ygj- -uen ? addition of watch timer high-speed clock select register (wtnhc), iic flag registers 0 and 1 (iicf0, iicf1) p.49 change of minimum instruction execution time in 1.4.1 features (v850/sc3) p.56 modification of description in table 2-1 pin i/o buffer power supplies p.66 modification of description in table 2-3 pin operation states in various operating modes pp.109, 113, 115, 116 modification of 3.4.8 peripheral i/o registers p.119 addition of remarks in 3.4.9 (2) system status register (sys) p.120 change of frequency of the v850/sc3 in 4.1 (1) main clock oscillator pp.122, 123 addition of note and caution in 4.3.1 (1) processor clock control register (pcc) p.123 modification of description for setting dclk1 and dclk0 bits = 01b and addition to notes in 4.3.1 (2) power save control register (psc) p.128 modification of description on operation status of a16 to a21 pins in table 4-1 operating statuses in halt mode p.129 modification of description on operation of uart0 to uart3 in table 4-2 operating statuses in idle mode p.131 addition of description in 4.4.4 (1) settings and operating states p.132 modification of description on operation status of uart0 to uart3 in table 4-3 operating statuses in software stop mode p.135 addition of 4.6 (1) when executing an instruction on internal rom p.136 addition of caution in 4.6 (2) when executing an instruction on external rom p.138 modification of description in table 5-1 pin i/o buffer power supplies p.166 addition of caution in 5.2.8 (1) function of p9 pins pp.192 to 194 addition and modification of description in table 5-16 setting when port pin is used for alternate function p.198 addition of 5.4 operation of port function p.201 addition of note and caution in 6.2.2 (1) system control register (syc) (v850/sc1, v850/sc2) p.223 modification of description in figure 7-2 acknowledging non-maskable interrupt requests p.250 addition of 7.8.1 interrupt request valid timing following ei instruction p.252 addition of 7.9 bit manipulation instruction of interrupt control register on dma transfer p.258 addition and modification of description in 8.1.3 (2) capture/compare register n0 (cr00, cr10, cr70 to cr120) p.259 addition and modification of description in 8.1.3 (3) capture/compare register n1 (cr01, cr11, cr71 to cr121) p.261 addition to cautions in 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) p.262 addition to cautions in 8.1.4 (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) p.275 addition of figure 8-6 configuration of ppg output and figure 8-7 ppg output operation timing
user?s manual u15109ej3v0ud 7 major revisions in this edition (2/4) page description p.288 change of description of caution in 8.2.6 (2) one-shot pulse output via external trigger p.319 addition of caution in 10.3 (2) watchdog timer clock select register (wdcs) p.324 addition of description in 11.2 (2) 3-wire serial i/o mode (fixed as msb first) p.327 addition to cautions in 11.2.2 (1) serial clock select register n (csisn) and serial operation mode register n (csimn) p.350 modification of description on manipulatable bits in 11.4.3 (6) clocked serial interface read-only receive buffer registers l5, l6 (sirbel5, sirbel6) p.351 modification of description on manipulatable bits in 11.4.3 (8) clocked serial interface transmit buffer registers l5, l6 (sotbl6, sotbl5) p.352 modification of description on manipulatable bits in 11.4.3 (10) clocked serial interface initial transmit buffer registers l5, l6 (sotbfl5, sotbfl6) p.353 modification of description on manipulatable bits in 11.4.3 (12) serial i/o shift registers l5, l6 (siol5, siol6) pp.378, 379 modification of description and addition to note in 11.5.2 (1) iic control register 0, 1 (iicc0, iicc1) p.385 addition of caution in 11.5.2 (4) iic clock expansion registers 0, 1 (iicce0, iicce1), iic function expansion registers 0, 1 (iicx0, iicx1), iic clock select registers 0, 1 (iiccl0, iiccl1) pp.421, 422 addition of 11.5.12 (2) when communication reservation function is disabled (iicrsvn of iicfn register = 1) p.423 change of description in 11.5.13 cautions p.424 change of description in 11.5.14 (1) master operations (1) p.425 addition of 11.5.14 (2) master operations (2) p.426 addition of description in figure 11-39 slave operation flowchart p.437 addition to cautions in 11.6.2 (1) asynchronous serial interface mode registers 0 to 3 (asim0 to asim3) p.440 addition to cautions in 11.6.2 (4) baud rate generator mode control registers n0, n1 (brgmcn0, brgmcn1) p.441 addition to cautions in figure 11-43 asimn setting (operation stopped mode) p.442 addition to cautions in figure 11-44 asimn setting (asynchronous serial interface mode) p.445 addition to cautions in figure 11-47 brgmcn0 and brgmcn1 settings (asynchronous serial interface mode) p.451 addition of description in 11.6.3 (3) (d) reception p.452 deletion of description in 11.6.3 (3) (e) receive error p.452 modification of note in figure 11-52 receive error timing p.456 modification of caution in 12.2 (2) a/d conversion result register (adcr), a/d conversion result register h (adcrh) p.460 addition of caution in 12.3 (2) analog input channel specification register (ads) p.467 modification of description in 12.6 (3) <3> conflict between writing of adcr and writing a/d converter mode register 1 (adm1) or analog input channel specification register (ads) p.470 modification of description in 12.6 (8) reading out a/d converter result register (adcr) p.472 addition of 13.3 configuration p.477 addition to cautions in 13.4 (6) start factor settings
8 user?s manual u15109ej3v0ud major revisions in this edition (3/4) page description pp.479, 480 addition of 13.5 operation pp.480 to 482 addition of 13.6 cautions p.483 modification of description in 14.1 (3) internal reset by power-on-clear (poc) p.487 modification of description in 14.3 (3) poc control register (pocc) p.495 addition of figure 17-1 example of wiring of adapter for flash programming (fa-144gj-uen) p.496 addition of table 17-1 table for wiring of adapter for pd70f3089y flash programming (fa- 144gj-uen) p.514 addition of description in table 18-5 control field acknowledge signal output conditions p.559 addition of 19.1 features p.559 modification of description in table 19-1 overview of functions pp.574, 575 change of manipulatable bits and reset values in 19.4.2 list of fcan registers p.576 modification of description in 19.5.1 can message data length registers 00 to 31 (m_dlc00 to m_dlc31) pp.577, 578 modification of description in 19.5.2 can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) p.585 addition of description in 19.5.6 can message configuration registers 00 to 31 (m_conf00 to m_conf31) p.587 modification of description in 19.5.7 can message status registers 00 to 31 (m_stat00 to m_stat31) p.593 modification of description on manipulatable bits and modification of register format and bit description in 19.5.10 can global interrupt pending register (cgintp) pp.594, 595 modification of description on manipulatable bits and modification of register format in 19.5.11 cann interrupt pending register (cnintp) p.596 addition to cautions in 19.5.12 can stop register (cstop) pp.597, 598 modification of description on manipulatable bits and modification of bit description in 19.5.13 can global status register (cgst) p.600 modification of description on manipulatable bits and modification of bit description in 19.5.14 can global interrupt enable register (cgie) p.601 addition of description in 19.5.15 can main clock select register (cgcs) p.602 deletion of caution in figure 19-2 fcan clocks pp.604, 605 addition of cautions and bit name, and modification of bit description in 19.5.17 can message search start/result register (cgmss/cgmsr) p.606 addition of description in 19.5.18 cann address mask a registers l and h (cnmaskla and cnmaskha) p.610 addition of description in 19.5.19 cann control register (cnctrl) pp.612 to 614 modification of description on manipulatable bits and modification of bit description in 19.5.20 cann definition register (cndef) pp.618, 619 modification of description on manipulatable bits and addition of bit description in 19.5.23 cann interrupt enable register (cnie) pp.626, 627 modification of description in cautions and addition of bit description in 19.5.27 cann synchronization control register (cnsync)
user?s manual u15109ej3v0ud 9 major revisions in this edition (4/4) page description p.630 addition of caution in 19.7 time stamp function p.633 modification of description in 19.8 message processing p.638 change of figure 19-10 composition of layers p.653 addition of caution in 19.11.7 (2) nominal bit time (8 to 25 time quanta) p.654 addition to note in figure 19-25 nominal bit time p.656 addition of description in figure 19-28 initialization processing p.659 addition of note in figure 19-33 setting of cann synchronization control register (cnsync) p.664 addition of description in figure 19-38 message buffer setting p.667 addition of figure 19-41 setting of can message status registers 00 to 31 (m_stat00 to m_stat31) p.670 addition of figure 19-44 setting receive operation using reception polling p.671 addition of figure 19-45 setting of can message search start/result register (cgmss/cgmsr) p.674 addition of description in figure 19-49 can stop mode setting p.674 addition of description in figure 19-50 clearing can stop mode p.675 modification of description in 19.13 rules for correct setting of baud rate p.680 addition to cautions in 19.14.2 burst read mode p.682 deletion of caution 2 in 19.16 how to shutdown fcan controller pp.682, 683 addition of <4> and <5> in 19.17 cautions on use p.684 addition of chapter 20 electrical specifications p.712 addition of chapter 21 package drawing p.713 addition of chapter 22 recommended soldering conditions p.732 addition of appendix c revision history the mark shows major revised points.
10 user?s manual u15109ej3v0ud introduction readers this manual is intended for users who wish to understand the functions of the v850/sc1, v850/sc2, and v850/sc3 to design application systems using the v850/sc1, v850/sc2, and v850/sc3. purpose this manual is intended to give users an understanding of the hardware functions described in the organization below. organization the v850/sc1, v850/sc2, and v850/sc3 user?s manual is divided into two parts: hardware (this manual) and architecture (v850 series tm architecture user?s manual). hardware architecture ? pin functions ? cpu functions ? on-chip peripheral functions ? flash memory programming ? iebus tm controller ? fcan controller ? electrical specifications ? data types ? register set ? instruction format and instruction set ? interrupts and exceptions ? pipeline operation how to read this manual it is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to find out the details of a register whose name is known: refer to appendix a register index . to understand the details of an instruction function: refer to v850 series architecture user?s manual, available separately. to know the electrical specifications of the v850/sc1, v850/sc2, and v850/sc3: refer to chapter 20 electrical specifications . how to read register formats: names of bits whose numbers are enclosed in < > are defined in the device file under reserved words. to understand the overall functions of the v850/sc1, v850/sc2, and v850/sc3: read this manual in accordance with the contents .
user?s manual u15109ej3v0ud 11 conventions data significance: higher digits on the left and lower digits on the right active low: xxx (overscore over pin or signal name) memory map address: higher addresses at the top and lower addresses at the bottom note : footnote for items marked with note in the text caution : information requiring particular attention remark : supplementary information number representation: binary ? xxxx or xxxxb decimal ? xxxx hexadecimal ? xxxxh prefixes indicating power of 2 (address space, memory capacity): k (kilo): 2 10 ? 1024 m (mega): 2 20 ? 1024 2 g (giga): 2 30 ? 1024 3
12 user?s manual u15109ej3v0ud related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850/sc1, v850/sc2, v850/sc3 document name document no. v850 series architecture user?s manual u10243e v850/sc1, v850/sc2, v850/sc3 hardware user?s manual this manual documents related to development tools (user?s manuals) document name document no. ie-703002-mc (in-circuit emulator) u11595e ie-703089-mc-em1 (in-circuit emulator option board) to be prepared operation u14568e c language u14566e project manager u14569e ca850 ver. 2.30 or later c compiler package assembly language u14567e operation u15024e c language u15025e project manager u15026e ca850 ver. 2.40 or later c compiler package assembly language u15027e id850 ver. 2.40 integrated debugger operation windows tm based u15181e sm850 ver. 2.40 system simulator operation windows based u15182e sm850 ver. 2.00 or later system simulator external part user open interface specifications u14873e basics u13430e installation u13410e rx850 ver. 3.13 or later real-time os technical u13431e fundamental u13773e installation u13774e rx850 pro ver. 3.13 real-time os technical u13772e rd850 ver. 3.01 task debugger u13737e rd850 pro ver. 3.01 task debugger u13916e az850 ver. 3.0 system performance analyzer u14410e pg-fp3 flash memory programmer u13502e pg-fp4 flash memory programmer u15260e
user?s manual u15109ej3v0ud 13 contents chapter 1 introduction..................................................................................................... ............34 1.1 general ..................................................................................................................... .................34 1.2 v850/sc1 .................................................................................................................... ...............35 1.2.1 features (v850/sc1) ....................................................................................................... ........ 35 1.2.2 application fields (v850/sc1) ............................................................................................. ..... 36 1.2.3 ordering information (v850/sc1)........................................................................................... .. 36 1.2.4 pin configuration (top view) (v850/sc1) .................................................................................. 3 7 1.2.5 function blocks (v850/sc1) ................................................................................................ .... 39 1.3 v850/sc2 .................................................................................................................... ...............42 1.3.1 features (v850/sc2) ....................................................................................................... ........ 42 1.3.2 application fields (v850/sc2) ............................................................................................. ..... 43 1.3.3 ordering information (v850/sc2)........................................................................................... .. 43 1.3.4 pin configuration (top view) (v850/sc2) .................................................................................. 4 4 1.3.5 function blocks (v850/sc2) ................................................................................................ .... 46 1.4 v850/sc3 .................................................................................................................... ...............49 1.4.1 features (v850/sc3) ....................................................................................................... ........ 49 1.4.2 application fields (v850/sc3) ............................................................................................. ..... 50 1.4.3 ordering information (v850/sc3)........................................................................................... .. 50 1.4.4 pin configuration (top view) (v850/sc3) .................................................................................. 5 1 1.4.5 function blocks (v850/sc3) ................................................................................................ .... 53 chapter 2 pin functions ................................................................................................... ............56 2.1 list of pin functions ....................................................................................................... .........56 2.2 pin states .................................................................................................................. ................66 2.3 description of pin functions................................................................................................ ...67 2.4 pin i/o circuit types, i/o buffer power supply and connection of unused pins .............82 2.5 pin i/o circuits............................................................................................................ ..............85 chapter 3 cpu functions................................................................................................... ...........86 3.1 features.................................................................................................................... .................86 3.2 cpu register set ............................................................................................................ ..........87 3.2.1 program register set...................................................................................................... ........... 88 3.2.2 system register set ....................................................................................................... ........... 89 3.3 operating modes ............................................................................................................. .........92 3.4 address space............................................................................................................... ...........93 3.4.1 cpu address space ......................................................................................................... ........ 93 3.4.2 imaging ................................................................................................................... ................. 94 3.4.3 wrap-around of cpu address space ....................................................................................... 95 3.4.4 memory map ................................................................................................................ ............ 96 3.4.5 area...................................................................................................................... .................... 97 3.4.6 external expansion mode................................................................................................... .... 103
14 user?s manual u15109ej3v0ud 3.4.7 recommended use of address space ....................................................................................106 3.4.8 peripheral i/o registers .................................................................................................. ........108 3.4.9 specific registers ........................................................................................................ ............118 chapter 4 clock generation function...............................................................................120 4.1 general..................................................................................................................... ................120 4.2 configuration ............................................................................................................... ...........121 4.3 clock output function ....................................................................................................... ....121 4.3.1 control registers ......................................................................................................... ............122 4.4 power save functions ........................................................................................................ ...125 4.4.1 general................................................................................................................... ................125 4.4.2 halt mode ................................................................................................................. ...........126 4.4.3 idle mode................................................................................................................. .............129 4.4.4 software stop mode........................................................................................................ .....131 4.5 oscillation stabilization time.............................................................................................. ..134 4.6 cautions on power save function........................................................................................135 chapter 5 port functions .................................................................................................. .......138 5.1 port configuration .......................................................................................................... ........138 5.2 port pin functions.......................................................................................................... ........140 5.2.1 port 0.................................................................................................................... ..................140 5.2.2 port 1.................................................................................................................... ..................144 5.2.3 port 2.................................................................................................................... ..................149 5.2.4 port 3.................................................................................................................... ..................153 5.2.5 ports 4 and 5 ............................................................................................................. .............157 5.2.6 port 6.................................................................................................................... ..................160 5.2.7 ports 7 and 8 ............................................................................................................. .............163 5.2.8 port 9.................................................................................................................... ..................165 5.2.9 port 10................................................................................................................... .................168 5.2.10 port 11.................................................................................................................. ..................171 5.2.11 port 12.................................................................................................................. ..................176 5.2.12 port 13.................................................................................................................. ..................180 5.2.13 port 14.................................................................................................................. ..................182 5.2.14 port 15.................................................................................................................. ..................185 5.2.15 port 17.................................................................................................................. ..................188 5.3 setting when port pin is used for alternate function .......................................................192 5.4 operation of port function .................................................................................................. ..198 5.4.1 writing data to i/o port .................................................................................................. .........198 5.4.2 reading data from i/o port ................................................................................................ .....198 chapter 6 bus control function ..........................................................................................1 99 6.1 features .................................................................................................................... ...............199 6.2 bus control pins and control register ................................................................................200 6.2.1 bus control pins.......................................................................................................... ............200
user?s manual u15109ej3v0ud 15 6.2.2 control register.......................................................................................................... ............. 201 6.3 bus access .................................................................................................................. ...........201 6.3.1 number of access clocks ................................................................................................... .... 201 6.3.2 bus width................................................................................................................. ............... 202 6.4 memory block function....................................................................................................... ..203 6.5 wait function............................................................................................................... ...........204 6.5.1 programmable wait function................................................................................................ ... 204 6.5.2 external wait function .................................................................................................... ......... 205 6.5.3 relationship between programmable wait and external wait ................................................. 205 6.6 idle state insertion function ............................................................................................... ..206 6.7 bus hold function........................................................................................................... .......207 6.7.1 outline of function ....................................................................................................... ........... 207 6.7.2 bus hold procedure ........................................................................................................ ........ 208 6.7.3 operation in power save mode .............................................................................................. 208 6.8 bus timing .................................................................................................................. ............209 6.9 bus priority ................................................................................................................ .............216 6.10 memory boundary operation condition ..............................................................................216 6.10.1 program space............................................................................................................ ........... 216 6.10.2 data space ............................................................................................................... .............. 216 chapter 7 interrupt/exception processing function .................................................217 7.1 outline ..................................................................................................................... ................217 7.1.1 features .................................................................................................................. ............... 217 7.2 non-maskable interrupts ..................................................................................................... ..221 7.2.1 operation ................................................................................................................. .............. 222 7.2.2 restore................................................................................................................... ................ 224 7.2.3 np flag ................................................................................................................... ................ 225 7.2.4 noise eliminator of nmi pin ............................................................................................... ..... 225 7.2.5 edge detection function of nmi pin ........................................................................................ 226 7.3 maskable interrupts......................................................................................................... .......227 7.3.1 operation ................................................................................................................. .............. 227 7.3.2 restore................................................................................................................... ................ 229 7.3.3 priorities of maskable interrupts......................................................................................... .... 230 7.3.4 interrupt control register (xxicn) ........................................................................................ .... 233 7.3.5 in-service priority register (ispr) ....................................................................................... .... 237 7.3.6 id flag................................................................................................................... .................. 237 7.3.7 watchdog timer mode register (wdtm)................................................................................. 238 7.3.8 noise elimination......................................................................................................... ........... 238 7.3.9 edge detection function................................................................................................... ....... 240 7.4 software exceptions ......................................................................................................... .....241 7.4.1 operation ................................................................................................................. .............. 241 7.4.2 restore................................................................................................................... ................ 242 7.4.3 ep flag................................................................................................................... ................. 243 7.5 exception trap.............................................................................................................. ..........244 7.5.1 illegal op code definition................................................................................................ ......... 244
16 user?s manual u15109ej3v0ud 7.5.2 operation................................................................................................................. ...............244 7.5.3 restore................................................................................................................... ................245 7.6 priority control............................................................................................................ ............246 7.6.1 priorities of interrupts and exceptions ................................................................................... .246 7.6.2 multiple interrupt servicing.............................................................................................. ........247 7.7 response time ............................................................................................................... ........249 7.8 periods in which interrupts are not acknowledged ..........................................................250 7.8.1 interrupt request valid timing following ei instruction .............................................................250 7.9 bit manipulation instruction of interrupt control register on dma transfer ..................252 7.10 key interrupt function ..................................................................................................... ......253 chapter 8 timer/counter function........................................................................................25 5 8.1 16-bit timer (tm0, tm1, tm7 to tm12) .................................................................................255 8.1.1 outline ................................................................................................................... .................255 8.1.2 function.................................................................................................................. ................255 8.1.3 configuration ............................................................................................................. .............257 8.1.4 timer 0, 1, 7 to 12 control registers..................................................................................... ...260 8.2 16-bit timer (tm0, tm1, tm7 to tm12) operation ...............................................................272 8.2.1 operation as interval timer ............................................................................................... ......272 8.2.2 ppg output operation ...................................................................................................... .......274 8.2.3 pulse width measurement ................................................................................................... ...276 8.2.4 operation as external event counter ......................................................................................2 83 8.2.5 operation as square-wave output ..........................................................................................2 85 8.2.6 operation as one-shot pulse output .......................................................................................2 86 8.2.7 cautions .................................................................................................................. ...............291 8.3 16-bit timer (tm5, tm6) ..................................................................................................... ....296 8.3.1 functions................................................................................................................. ...............296 8.3.2 configuration ............................................................................................................. .............297 8.3.3 timer n control registers................................................................................................. ........298 8.4 16-bit timer (tm5, tm6) operation .......................................................................................302 8.4.1 operation as an interval timer ............................................................................................ ....302 8.4.2 operation as external event counter ......................................................................................3 04 8.4.3 operation as square-wave output ..........................................................................................3 05 8.4.4 operation as 16-bit pwm output ............................................................................................ 306 8.4.5 cautions .................................................................................................................. ...............308 chapter 9 watch timer function ........................................................................................... 309 9.1 function.................................................................................................................... ...............309 9.2 configuration ............................................................................................................... ...........310 9.3 watch timer control register ...............................................................................................3 11 9.4 operation ................................................................................................................... ..............313 9.4.1 operation as watch timer.................................................................................................. ......313 9.4.2 operation as interval timer ............................................................................................... ......314 9.4.3 cautions .................................................................................................................. ...............315
user?s manual u15109ej3v0ud 17 chapter 10 watchdog timer function.................................................................................316 10.1 functions .................................................................................................................. ..............316 10.2 configuration .............................................................................................................. ............318 10.3 watchdog timer control registers ......................................................................................318 10.4 operation.................................................................................................................. ...............321 10.4.1 operation as watchdog timer .............................................................................................. ... 321 10.4.2 operation as interval timer .............................................................................................. ....... 322 10.5 standby function control register......................................................................................323 chapter 11 serial interface function................................................................................324 11.1 overview................................................................................................................... ...............324 11.2 3-wire serial i/o (csi0, csi2, csi3): 8 bits...........................................................................324 11.2.1 configuration............................................................................................................ .............. 325 11.2.2 csin control registers................................................................................................... .......... 326 11.2.3 operations............................................................................................................... ............... 328 11.3 3-wire serial i/o (csi4): 8 to 16 bits variable ......................................................................331 11.3.1 configuration............................................................................................................ .............. 331 11.3.2 csi4 control registers................................................................................................... .......... 334 11.3.3 operations............................................................................................................... ............... 338 11.4 3-wire serial i/o (csi5, csi6): 8 or 16 bits ...........................................................................343 11.4.1 features ................................................................................................................. ................ 343 11.4.2 configuration............................................................................................................ .............. 344 11.4.3 control registers........................................................................................................ ............. 346 11.4.4 operation ................................................................................................................ ............... 354 11.4.5 output pins............................................................................................................ ................. 369 11.5 i 2 c bus .......................................................................................................................... ...........370 11.5.1 configuration............................................................................................................ .............. 373 11.5.2 i 2 c control registers ............................................................................................................ .... 375 11.5.3 i 2 c bus mode functions .......................................................................................................... 3 88 11.5.4 i 2 c bus definitions and control methods ................................................................................. 389 11.5.5 i 2 c interrupt requests (intiicn) .............................................................................................. 396 11.5.6 interrupt request (intiicn) generation timing and wait control .............................................. 414 11.5.7 address match detection method........................................................................................... 415 11.5.8 error detection.......................................................................................................... .............. 415 11.5.9 extension code........................................................................................................... ............ 415 11.5.10 arbitration............................................................................................................. .................. 416 11.5.11 wakeup function ......................................................................................................... ........... 417 11.5.12 communication reservation ............................................................................................... .... 418 11.5.13 cautions ................................................................................................................ ................. 423 11.5.14 communication operations ................................................................................................ .... 424 11.5.15 timing of data communication ............................................................................................ ... 427 11.6 asynchronous serial interface (uart0 to uart3).............................................................434 11.6.1 configuration............................................................................................................ .............. 434 11.6.2 uartn control registers.................................................................................................. ....... 436 11.6.3 operations............................................................................................................... ............... 441
18 user?s manual u15109ej3v0ud 11.6.4 standby function......................................................................................................... ............453 chapter 12 a/d converter.................................................................................................. ........454 12.1 function................................................................................................................... ................454 12.2 configuration .............................................................................................................. ............456 12.3 control registers.......................................................................................................... ..........458 12.4 operation .................................................................................................................. ...............461 12.4.1 basic operation.......................................................................................................... .............461 12.4.2 input voltage and conversion result...................................................................................... ..463 12.4.3 a/d converter operation mode............................................................................................. ...464 12.5 low-power-consumption mode............................................................................................467 12.6 cautions................................................................................................................... ................467 chapter 13 dma functions .................................................................................................. .......471 13.1 functions.................................................................................................................. ...............471 13.2 transfer completion interrupt request................................................................................471 13.3 configuration .............................................................................................................. ............472 13.4 control registers.......................................................................................................... ..........473 13.5 operation .................................................................................................................. ...............479 13.6 cautions................................................................................................................... ................480 chapter 14 reset function................................................................................................. .......483 14.1 general.................................................................................................................... .................483 14.2 pin operations ............................................................................................................. ...........484 14.3 power-on-clear operation ................................................................................................... ..486 chapter 15 regulator....................................................................................................... ...........488 15.1 outline.................................................................................................................... ..................488 15.2 operation .................................................................................................................. ...............488 chapter 16 rom correction function .................................................................................489 16.1 general.................................................................................................................... .................489 16.2 rom correction peripheral i/o registers ............................................................................490 16.2.1 correction control register (corcn)...................................................................................... 490 16.2.2 correction request register (corrq) ....................................................................................49 0 16.2.3 correction address registers 0 to 3 (corad0 to corad3) ..................................................491 chapter 17 flash memory ( pd70f3089y) ..............................................................................493 17.1 features ................................................................................................................... ................493 17.1.1 erasing unit ............................................................................................................. ...............493 17.1.2 write/read time .......................................................................................................... .............494 17.2 writing with flash programmer ............................................................................................49 4
user?s manual u15109ej3v0ud 19 17.3 programming environment ...................................................................................................4 97 17.4 communication mode ......................................................................................................... ...497 17.5 pin connection ............................................................................................................. ..........500 17.5.1 v pp pin........................................................................................................................... ......... 500 17.5.2 serial interface pin ..................................................................................................... ............ 501 17.5.3 reset pin ................................................................................................................ ............. 503 17.5.4 port pins (including nmi)................................................................................................ ........ 503 17.5.5 other signal pins ........................................................................................................ ............ 503 17.5.6 power supply............................................................................................................. ............. 503 17.6 programming method ......................................................................................................... ...504 17.6.1 flash memory control..................................................................................................... ........ 504 17.6.2 flash memory programming mode ........................................................................................ 504 17.6.3 selection of communication mode ......................................................................................... 5 05 17.6.4 communication command.................................................................................................... .. 505 chapter 18 iebus controller (v850/sc2) ..............................................................................507 18.1 iebus controller function .................................................................................................. ...507 18.1.1 communication protocol of iebus .......................................................................................... 507 18.1.2 determination of bus mastership (arbitration) ........................................................................ 508 18.1.3 communication mode ....................................................................................................... ..... 508 18.1.4 communication address .................................................................................................... .... 508 18.1.5 broadcast communication.................................................................................................. .... 509 18.1.6 transfer format of iebus ................................................................................................. ....... 509 18.1.7 transfer data............................................................................................................ .............. 518 18.1.8 bit format............................................................................................................... ................. 521 18.2 iebus controller configuration............................................................................................. 522 18.3 internal registers of iebus controller .................................................................................524 18.3.1 internal register list................................................................................................... .............. 524 18.3.2 internal registers ....................................................................................................... ............. 525 18.4 interrupt operations of iebus controller.............................................................................544 18.4.1 interrupt control block.................................................................................................. ........... 544 18.4.2 interrupt source list.................................................................................................... ............. 545 18.4.3 communication error cause processing list ........................................................................... 546 18.5 interrupt generation timing and main cpu processing ....................................................548 18.5.1 master transmission ...................................................................................................... ......... 548 18.5.2 master reception ......................................................................................................... ........... 550 18.5.3 slave transmission ....................................................................................................... .......... 552 18.5.4 slave reception .......................................................................................................... ............ 554 18.5.5 interval of occurrence of interrupt for iebus control............................................................... 555 chapter 19 fcan controller (v850/sc3) ..............................................................................559 19.1 features................................................................................................................... ................559 19.2 overview of functions ...................................................................................................... .....559 19.3 configuration .............................................................................................................. ............560
20 user?s manual u15109ej3v0ud 19.4 internal registers of fcan controller..................................................................................562 19.4.1 configuration of messages and buffers..................................................................................56 2 19.4.2 list of fcan registers ................................................................................................... .........563 19.5 control registers.......................................................................................................... ..........576 19.5.1 can message data length registers 00 to 31 (m_dlc00 to m_dlc31) ................................576 19.5.2 can message control registers 00 to 31 (m_ctrl00 to m_ctrl31)...................................577 19.5.3 can message time stamp registers 00 to 31 (m_time00 to m_time31)..............................579 19.5.4 can message data registers n0 to n7 (m_datan0 to m_datan7) ......................................581 19.5.5 can message id registers l00 to l31 and h00 to h31 (m_idl00 to m_idl31 and m_idh00 to m_idh31)................................................................583 19.5.6 can message configuration registers 00 to 31 (m_conf00 to m_conf31) .......................585 19.5.7 can message status registers 00 to 31 (m_stat00 to m_stat31) ....................................587 19.5.8 can status set/clear registers 00 to 31 (sc_stat00 to sc_stat31) .................................589 19.5.9 can interrupt pending register (ccintp) ..............................................................................591 19.5.10 can global interrupt pending register (cgintp) ...................................................................593 19.5.11 cann interrupt pending register (cnintp).............................................................................594 19.5.12 can stop register (cstop) ............................................................................................... ....596 19.5.13 can global status register (cgst) ....................................................................................... .597 19.5.14 can global interrupt enable register (cgie) ..........................................................................600 19.5.15 can main clock select register (cgcs).................................................................................60 1 19.5.16 can time stamp count register (cgtsc)...............................................................................603 19.5.17 can message search start/result register (cgmss/cgmsr) ...............................................604 19.5.18 cann address mask a registers l and h (cnmaskla and cnmaskha)..............................606 19.5.19 cann control register (cnctrl).......................................................................................... ..608 19.5.20 cann definition register (cndef) ........................................................................................ ..612 19.5.21 cann information register (cnlast) .....................................................................................6 16 19.5.22 cann error count register (cnerc) ....................................................................................... 617 19.5.23 cann interrupt enable register (cnie)................................................................................... .618 19.5.24 cann bus active register (cnba) ......................................................................................... ..621 19.5.25 cann bit rate prescaler register (cnbrp)..............................................................................62 2 19.5.26 cann bus diagnostic information register (cndinf)..............................................................625 19.5.27 cann synchronization control register (cnsync) .................................................................626 19.6 cautions regarding bit set/clear function .........................................................................628 19.7 time stamp function ........................................................................................................ .....630 19.8 message processing ......................................................................................................... .....633 19.8.1 message transmission..................................................................................................... .......634 19.8.2 message reception ........................................................................................................ .........635 19.9 mask function.............................................................................................................. ...........636 19.10 protocol .................................................................................................................. .................638 19.10.1 frame format ............................................................................................................ ..............638 19.10.2 frame types ............................................................................................................. ..............639 19.10.3 data frame and remote frame ............................................................................................. ...639 19.10.4 error frame ............................................................................................................. ................647 19.10.5 overload frame.......................................................................................................... .............648 19.11 functions................................................................................................................. ................649
user?s manual u15109ej3v0ud 21 19.11.1 determination of bus priority ........................................................................................... ....... 649 19.11.2 bit stuffing ............................................................................................................ .................. 649 19.11.3 multimasters............................................................................................................ ............... 649 19.11.4 multi-cast.............................................................................................................. .................. 649 19.11.5 can sleep mode/can stop mode function ............................................................................ 650 19.11.6 error control function.................................................................................................. ............ 650 19.11.7 baud rate control function .............................................................................................. ........ 653 19.12 operations................................................................................................................ ...............656 19.12.1 initialization processing ............................................................................................... ........... 656 19.12.2 transmit setting........................................................................................................ .............. 668 19.12.3 receive setting......................................................................................................... .............. 669 19.12.4 can sleep mode .......................................................................................................... .......... 672 19.12.5 can stop mode ........................................................................................................... ........... 674 19.13 rules for correct setting of baud rate................................................................................675 19.14 ensuring data consistency................................................................................................. ..679 19.14.1 sequential data read .................................................................................................... .......... 679 19.14.2 burst read mode......................................................................................................... ............ 680 19.15 interrupt conditions ...................................................................................................... .........681 19.15.1 interrupts that occur for fcan controller ............................................................................... 681 19.15.2 interrupts that occur for global can interface ........................................................................ 68 1 19.16 how to shutdown fcan controller......................................................................................682 19.17 cautions on use ........................................................................................................... ..........682 chapter 20 electrical specifications .................................................................................684 chapter 21 package drawing................................................................................................ ...712 chapter 22 recommended soldering conditions ...........................................................713 appendix a register index ................................................................................................. ........714 appendix b list of instruction sets....................................................................................7 25 appendix c revision history ................................................................................................ ......732
22 user?s manual u15109ej3v0ud list of figures (1/8) figure no. title page 3-1 cpu register set ............................................................................................................ ................................87 3-2 cpu address space........................................................................................................... .............................93 3-3 address space imaging ....................................................................................................... ...........................94 3-4 program space............................................................................................................... .................................95 3-5 data space.................................................................................................................. ....................................95 3-6 memory map.................................................................................................................. ..................................96 3-7 internal rom/flash memory area .............................................................................................. .....................97 3-8 internal ram area ........................................................................................................... ................................99 3-9 on-chip peripheral i/o area ................................................................................................. ........................100 3-10 external memory area (when expanded to 64 kb, 256 kb, or 1 mb)..........................................................101 3-11 external memory area (when expanded to 4 mb)............................................................................... .........102 3-12 application of wrap-around................................................................................................. ..........................106 3-13 recommended memory map (flash memory version) .............................................................................. ...107 4-1 clock generator ............................................................................................................. ...............................121 4-2 oscillation stabilization time.............................................................................................. ...........................134 5-1 block diagram of p00 to p07 ................................................................................................. .......................143 5-2 block diagram of p10 and p12 ................................................................................................ .....................146 5-3 block diagram of p11, p13 to p15, and p17................................................................................... ..............147 5-4 block diagram of p16........................................................................................................ ............................148 5-5 block diagram of p20 and p22 ................................................................................................ .....................151 5-6 block diagram of p21 and p23 to p27 ......................................................................................... .................152 5-7 block diagram of p30 to p37 ................................................................................................. .......................156 5-8 block diagram of p40 to p47 and p50 to p57.................................................................................. .............159 5-9 block diagram of p60 to p65 ................................................................................................. .......................162 5-10 block diagram of p70 to p77 and p80 to p83................................................................................. ..............164 5-11 block diagram of p90 to p96 ................................................................................................ ........................167 5-12 block diagram of p100 to p107 .............................................................................................. ......................170 5-13 block diagram of p110 and p114 to p117 ..................................................................................... ...............174 5-14 block diagram of p111 to p113 .............................................................................................. ......................175 5-15 block diagram of p120 to p125 .............................................................................................. ......................178 5-16 block diagram of p126 and p127 ............................................................................................. ....................179 5-17 block diagram of p130 to p133 .............................................................................................. ......................181 5-18 block diagram of p140 to p147 .............................................................................................. ......................184 5-19 block diagram of p150 to p157 .............................................................................................. ......................187 5-20 block diagram of p170 to p175 .............................................................................................. ......................190 5-21 block diagram of p176...................................................................................................... ............................191
user?s manual u15109ej3v0ud 23 list of figures (2/8) figure no. title page 6-1 byte access (8 bits) ........................................................................................................ .............................. 202 6-2 halfword access (16 bits) ................................................................................................... .......................... 202 6-3 word access (32 bits)....................................................................................................... ............................ 202 6-4 memory block................................................................................................................ ................................ 203 6-5 wait control................................................................................................................ ................................... 205 6-6 example of inserting wait states ............................................................................................ ...................... 205 6-7 bus hold procedure .......................................................................................................... ............................ 208 6-8 memory read................................................................................................................. ............................... 209 6-9 memory write ................................................................................................................ ................................ 213 6-10 bus hold timing ............................................................................................................ ................................ 215 7-1 non-maskable interrupt servicing ............................................................................................ ..................... 222 7-2 acknowledging non-maskable interrupt requests ............................................................................... ........ 223 7-3 reti instruction processing................................................................................................. ......................... 224 7-4 np flag (np) ................................................................................................................ ................................. 225 7-5 maskable interrupt servicing................................................................................................ ......................... 228 7-6 reti instruction processing................................................................................................. ......................... 229 7-7 example of interrupt nesting process........................................................................................ ................... 231 7-8 example of servicing interrupt requests simultaneously generated........................................................... 2 33 7-9 id flag..................................................................................................................... ...................................... 237 7-10 software exception processing.............................................................................................. ....................... 241 7-11 reti instruction processing................................................................................................ .......................... 242 7-12 ep flag (ep) ............................................................................................................... .................................. 243 7-13 illegal op code............................................................................................................ .................................. 244 7-14 exception trap processing .................................................................................................. ......................... 244 7-15 reti instruction processing................................................................................................ .......................... 245 7-16 pipeline operation at interrupt request acknowledgement.................................................................... ...... 249 7-17 pipeline flow and interrupt request generation timing...................................................................... ......... 252 7-18 block diagram of key return ................................................................................................ ........................ 254 8-1 block diagram of tm0, tm1, and tm7 to tm12 .................................................................................. ......... 256 8-2 control register settings when tmn operates as interval timer ............................................................... . 272 8-3 configuration of interval timer ............................................................................................. ......................... 273 8-4 timing of interval timer operation.......................................................................................... ...................... 273 8-5 control register settings in ppg output operation ........................................................................... .......... 274 8-6 configuration of ppg output................................................................................................. ........................ 275 8-7 ppg output operation timing ................................................................................................. ..................... 275
24 user?s manual u15109ej3v0ud list of figures (3/8) figure no. title page 8-8 control register settings for pulse width measurement with free-running counter and one capture register ....................................................................................................................... ..................................276 8-9 configuration for pulse width measurement with free-running counter.....................................................277 8-10 timing of pulse width measurement with free-running counter and one capture register (with both edges specified) ............................................................................................................... ............................277 8-11 control register settings for measurement of two pulse widths with free-running counter.....................278 8-12 crn1 capture operation with rising edge specified .......................................................................... .........279 8-13 timing of pulse width measurement with free-running counter (with both edges specified) ...................279 8-14 control register settings for pulse width measurement with free-running counter and two capture registers ...................................................................................................................... .................................280 8-15 timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) ................................................................................................................ .............................281 8-16 control register settings for pulse width measurement by restarting ........................................................ 282 8-17 timing of pulse width measurement by restarting (with rising edge specified).........................................282 8-18 control register settings in external event counter mode................................................................... ........283 8-19 configuration of external event counter .................................................................................... ...................284 8-20 timing of external event counter operation (with rising edge specified) ...................................................2 84 8-21 control register settings in square-wave output mode ....................................................................... .......285 8-22 timing of square-wave output operation ..................................................................................... ...............286 8-23 control register settings for one-shot pulse output via software trigger ..................................................2 87 8-24 timing of one-shot pulse output operation via software trigger............................................................. ...288 8-25 control register settings for one-shot pulse output via external trigger ................................................... 289 8-26 timing of one-shot pulse output operation via external trigger (with rising edge specified)...................290 8-27 start timing of 16-bit timer register n .................................................................................... .....................291 8-28 timing after changing compare register during timer count operation....................................................291 8-29 data hold timing of capture register....................................................................................... ....................292 8-30 operation timing of ovfn flag.............................................................................................. .......................293 8-31 block diagram of tm5 and tm6 ............................................................................................... .....................296 8-32 timing of interval timer operation ......................................................................................... .......................302 8-33 timing of external event counter operation (with rising edge specified) ...................................................3 04 8-34 square-wave output operation timing ........................................................................................ ................305 8-35 timing of pwm output ....................................................................................................... ...........................307 8-36 start timing of timer n .................................................................................................... ..............................308 9-1 block diagram of watch timer................................................................................................ ......................309 9-2 operation timing of watch timer/interval timer.............................................................................. .............314 9-3 watch timer interrupt request (intwtn) generation (interrupt period = 0.5 s) .........................................315
user?s manual u15109ej3v0ud 25 list of figures (4/8) figure no. title page 10-1 block diagram of watchdog timer............................................................................................ .................... 316 11-1 block diagram of 3-wire serial i/o (csi0, csi2, csi3) ...................................................................... .......... 325 11-2 csimn setting (operation stopped mode)..................................................................................... ............... 328 11-3 csimn setting (3-wire serial i/o mode) ..................................................................................... .................. 329 11-4 timing of 3-wire serial i/o mode ........................................................................................... ....................... 330 11-5 block diagram of 3-wire serial i/o (csi4) .................................................................................. .................. 332 11-6 when transfer bit length other than 16 bits is set ......................................................................... ........... 333 11-7 csim4 setting (operation stopped mode)..................................................................................... ............... 338 11-8 csim4 setting (3-wire serial i/o mode) ..................................................................................... .................. 339 11-9 csib4 setting (3-wire serial i/o mode) ..................................................................................... ................... 340 11-10 timing of 3-wire serial i/o mode .......................................................................................... ........................ 341 11-11 timing of 3-wire serial i/o mode (when csib4 = 08h) ....................................................................... ........ 342 11-12 block diagram of 3-wire serial i/o (csi5, csi6) ........................................................................... ............... 344 11-13 timing chart in single transfer mode...................................................................................... ..................... 355 11-14 timing chart according to clock phase selection........................................................................... ............. 357 11-15 timing chart of interrupt request signal output in delay mode ............................................................. ..... 359 11-16 repeat transfer (receive-only) timing chart............................................................................... ............... 362 11-17 repeat transfer (transmission/reception) timing chart..................................................................... ........ 364 11-18 timing chart of next transfer reservation period .......................................................................... ............. 365 11-19 transfer request clear and register access contention..................................................................... ........ 367 11-20 interrupt request and register access contention .......................................................................... ............ 368 11-21 block diagram of i 2 cn ............................................................................................................................. ...... 371 11-22 serial bus configuration example using i 2 c bus.......................................................................................... 372 11-23 pin configuration diagram ................................................................................................. ........................... 388 11-24 i 2 c bus serial data transfer timing.............................................................................................. ................ 389 11-25 start conditions.......................................................................................................... ................................... 389 11-26 address ................................................................................................................... ...................................... 390 11-27 transfer direction specification .......................................................................................... .......................... 391 11-28 ack signal ................................................................................................................ .................................... 392 11-29 stop condition............................................................................................................ ................................... 393 11-30 wait signal ............................................................................................................... ..................................... 394 11-31 arbitration timing example ................................................................................................ ........................... 416 11-32 communication reservation timing .......................................................................................... ................... 419 11-33 timing for accepting communication reservations........................................................................... ........... 419 11-34 communication reservation flowchart (1) ................................................................................... ................ 420 11-35 sttn = 1 setting disabled timing .......................................................................................... ...................... 421 11-36 communication reservation flowchart (2) ................................................................................... ................ 422
26 user?s manual u15109ej3v0ud list of figures (5/8) figure no. title page 11-37 master operation flowchart (1)............................................................................................ .........................424 11-38 master operation flowchart (2)............................................................................................ .........................425 11-39 slave operation flowchart ................................................................................................. ...........................426 11-40 example of master to slave communication (when 9-clock wait is selected for both master and slave) ...................................................................... ..428 11-41 example of slave to master communication (when 9-clock wait is selected for both master and slave) ...................................................................... ..431 11-42 block diagram of uartn .................................................................................................... ..........................435 11-43 asimn setting (operation stopped mode) .................................................................................... ................441 11-44 asimn setting (asynchronous serial interface mode) ........................................................................ ..........442 11-45 asisn setting (asynchronous serial interface mode)........................................................................ ...........443 11-46 brgcn setting (asynchronous serial interface mode)........................................................................ .........444 11-47 brgmcn0 and brgmcn1 settings (asynchronous serial interface mode).................................................445 11-48 allowable baud rate error range (when k = 16), including sampling errors..............................................447 11-49 format of transmit/receive data in asynchronous serial interface.......................................................... ...448 11-50 timing of asynchronous serial interface transmission completion interrupt...............................................45 0 11-51 timing of asynchronous serial interface reception completion interrupt .................................................... 451 11-52 receive error timing...................................................................................................... ...............................452 12-1 block diagram of a/d converter ............................................................................................. ......................455 12-2 basic operation of a/d converter ........................................................................................... ......................462 12-3 relationship between analog input voltage and a/d conversion result .....................................................463 12-4 a/d conversion by hardware start (with falling edge specified) ............................................................. ....465 12-5 a/d conversion by software start........................................................................................... ......................466 12-6 handling of analog input pin ............................................................................................... ..........................468 12-7 a/d conversion end interrupt generation timing ............................................................................. ............469 12-8 handling of adcv dd pin........................................................................................................................... .....470 13-1 dma block diagram .......................................................................................................... ............................472 13-2 correspondence between dran setting value and internal ram ...............................................................47 4 13-3 dma transfer operation timing.............................................................................................. ......................479 13-4 processing when transfer requests dma0 to dma5 are generated simultaneously ................................480 13-5 when interrupt servicing occurs twice during dma operation ................................................................. ..481 14-1 system reset timing by reset signal input.................................................................................. .............484 14-2 system reset timing by watchdog timer overflow ............................................................................. ........484 14-3 system reset timing by power-on-clear...................................................................................... ................485
user?s manual u15109ej3v0ud 27 list of figures (6/8) figure no. title page 15-1 regulator ( pd70f3089y).................................................................................................................... ........ 488 16-1 block diagram of rom correction ............................................................................................ .................... 489 16-2 rom correction operation and program flow .................................................................................. ........... 492 17-1 example of wiring of adapter for flash programming (fa-144gj-uen)...................................................... 495 17-2 environment required for writing programs to flash memory .................................................................. ... 497 17-3 communication with dedicated flash programmer (uart0) ...................................................................... . 497 17-4 communication with dedicated flash programmer (csi0)....................................................................... .... 498 17-5 communication with dedicated flash programmer (csi0 + hs) .................................................................. 498 17-6 v pp pin connection example ........................................................................................................ ................ 500 17-7 conflict of signals (serial interface input pin)........................................................................... .................... 501 17-8 malfunction of other device ................................................................................................ .......................... 502 17-9 conflict of signals (reset pin) ............................................................................................ ........................ 503 17-10 procedure for manipulating flash memory ................................................................................... ................ 504 17-11 flash memory programming mode ............................................................................................. .................. 504 17-12 communication command ..................................................................................................... ....................... 505 18-1 iebus transfer signal format ............................................................................................... ........................ 509 18-2 master address field ....................................................................................................... ............................. 510 18-3 slave address field ........................................................................................................ .............................. 511 18-4 control field .............................................................................................................. .................................... 513 18-5 telegraph length field ..................................................................................................... ............................ 515 18-6 data field ................................................................................................................. ..................................... 516 18-7 bit configuration of slave status.......................................................................................... ......................... 519 18-8 configuration of lock address .............................................................................................. ........................ 520 18-9 bit format of iebus ........................................................................................................ ............................... 521 18-10 iebus controller block diagram............................................................................................ ........................ 522 18-11 interrupt generation timing (for (1), (3), and (4))....................................................................... ................... 530 18-12 interrupt generation timing (for (2) and (5)) ............................................................................. .................... 531 18-13 timing of intie2 interrupt generation in locked state (for (4) and (5)) ................................................... .... 531 18-14 timing of intie2 interrupt generation in locked state (for (3)) ........................................................... ........ 531 18-15 example of broadcast communication flag operation ......................................................................... ....... 535 18-16 configuration of interrupt control block .................................................................................. ...................... 544 18-17 master transmission ....................................................................................................... .............................. 548 18-18 master reception .......................................................................................................... ................................ 550 18-19 slave transmission ........................................................................................................ ............................... 552 18-20 slave reception ........................................................................................................... ................................. 554
28 user?s manual u15109ej3v0ud list of figures (7/8) figure no. title page 18-21 master transmission (interval of interrupt occurrence) .................................................................... ............555 18-22 master reception (interval of interrupt occurrence) ....................................................................... ..............556 18-23 slave transmission (interval of interrupt occurrence) ..................................................................... .............557 18-24 slave reception (interval of interrupt occurrence) ........................................................................ ...............558 19-1 block diagram of fcan ...................................................................................................... ..........................561 19-2 fcan clocks ................................................................................................................ .................................602 19-3 example of bit setting/clearing operations ................................................................................. .................628 19-4 16-bit data during write operation......................................................................................... ......................629 19-5 time stamp function setting for message reception (when cxctrl register?s tmr bit = 0)..................630 19-6 time stamp function setting for message reception (when cxctrl register?s tmr bit = 1)..................631 19-7 time stamp function setting for message transmission (when m_ctrl register?s ats bit = 1)............632 19-8 message processing example (when pbb bit = 0) .............................................................................. ........634 19-9 message processing example (when pbb bit = 1) .............................................................................. ........634 19-10 composition of layers..................................................................................................... ..............................638 19-11 data frame................................................................................................................ ....................................639 19-12 remote frame.............................................................................................................. .................................640 19-13 start of frame (sof) ...................................................................................................... ...............................640 19-14 arbitration field (during standard format mode)........................................................................... ...............641 19-15 arbitration field (in extended format mode)............................................................................... ..................641 19-16 control field ............................................................................................................. .....................................642 19-17 data field ................................................................................................................ ......................................643 19-18 crc field ................................................................................................................. .....................................643 19-19 ack field ................................................................................................................. .....................................644 19-20 end of frame (eof) ........................................................................................................ ..............................644 19-21 interframe space (error active node) ...................................................................................... .....................645 19-22 interframe space (error passive node) ..................................................................................... ...................645 19-23 error frame ............................................................................................................... ....................................647 19-24 overload frame............................................................................................................ .................................648 19-25 nominal bit time .......................................................................................................... .................................654 19-26 coordination of data bit synchronization.................................................................................. ....................655 19-27 resynchronization ......................................................................................................... ................................655 19-28 initialization processing................................................................................................. ................................656 19-29 setting of can main clock select register (cgcs) .......................................................................... ...........657 19-30 setting of can global interrupt enable register (cgie) .................................................................... ..........657 19-31 setting of can global status register (cgst).............................................................................. ...............658 19-32 setting of cann bit rate prescaler (cnbrp)................................................................................ ................658 19-33 setting of cann synchronization control register (cnsync) ................................................................. ....659
user?s manual u15109ej3v0ud 29 list of figures (8/8) figure no. title page 19-34 setting of cann interrupt enable register (cnie) .......................................................................... .............. 660 19-35 setting of cann definition register (cndef) ............................................................................... ................ 661 19-36 setting of cann control register (cnctrl) ................................................................................. ............... 662 19-37 setting of cann address mask a registers l and h (cnmaskla and cnmaskha)................................... 663 19-38 message buffer setting .................................................................................................... ............................. 664 19-39 setting of can message configuration registers 00 to 31 (m_conf00 to m_conf31) ............................ 665 19-40 setting of can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) ....................................... 666 19-41 setting of can message status registers 00 to 31 (m_stat00 to m_stat31) ......................................... 667 19-42 transmit setting .......................................................................................................... .................................. 668 19-43 setting of receive operation using reception completion interrupt ......................................................... .. 669 19-44 setting receive operation using reception polling ......................................................................... ............ 670 19-45 setting of can message search start/result register (cgmss/cgmsr).................................................. 671 19-46 can sleep mode setting .................................................................................................... .......................... 672 19-47 clearing can sleep mode by can bus active status.......................................................................... ........ 672 19-48 clearing can sleep mode by cpu ............................................................................................ ................... 673 19-49 can stop mode setting ..................................................................................................... ........................... 674 19-50 clearing can stop mode .................................................................................................... .......................... 674 19-51 cnsync register settings .................................................................................................. ......................... 678 19-52 sequential data read ...................................................................................................... ............................. 679
30 user?s manual u15109ej3v0ud list of tables (1/4) table no. title page 1-1 product lineup of v850/sc1, v850/sc2, and v850/sc3 .......................................................................... .....34 2-1 pin i/o buffer power supplies ............................................................................................... ..........................56 2-2 differences in pins of v850/sc1, v850/sc2, and v850/sc3..................................................................... .....57 2-3 pin operation states in various operating modes............................................................................. .............66 3-1 program registers........................................................................................................... ................................88 3-2 system register numbers..................................................................................................... ..........................89 3-3 interrupt/exception table ................................................................................................... .............................98 4-1 operating statuses in halt mode............................................................................................. ...................127 4-2 operating statuses in idle mode ............................................................................................. ....................129 4-3 operating statuses in software stop mode .................................................................................... ............132 5-1 pin i/o buffer power supplies ............................................................................................... ........................138 5-2 port 0 alternate function pins.............................................................................................. .........................140 5-3 port 1 alternate function pins.............................................................................................. .........................144 5-4 port 2 alternate function pins.............................................................................................. .........................149 5-5 port 3 alternate function pins.............................................................................................. .........................153 5-6 alternate function pins of ports 4 and 5 .................................................................................... ...................157 5-7 port 6 alternate function pins.............................................................................................. .........................160 5-8 alternate function pins of ports 7 and 8 .................................................................................... ...................163 5-9 port 9 alternate function pins.............................................................................................. .........................165 5-10 port 10 alternate function pins............................................................................................ .........................168 5-11 port 11 alternate function pins............................................................................................ .........................171 5-12 port 12 alternate function pins............................................................................................ .........................176 5-13 port 14 alternate function pins............................................................................................ .........................182 5-14 port 15 alternate function pins............................................................................................ .........................185 5-15 port 17 alternate function pins............................................................................................ .........................188 5-16 setting when port pin is used for alternate function....................................................................... ............192 6-1 bus control pins............................................................................................................ ................................200 6-2 number of access clocks ..................................................................................................... ........................201 6-3 bus priority ................................................................................................................ ....................................216 7-1 interrupt source list ....................................................................................................... ...............................218 7-2 interrupt control registers (xxicn)......................................................................................... .......................235 7-3 priorities of interrupts and exceptions..................................................................................... ......................246
user?s manual u15109ej3v0ud 31 list of tables (2/4) table no. title page 7-4 description of key return detection pin ..................................................................................... .................. 253 8-1 configuration of timers 0, 1, and 7 to 12 ................................................................................... ................... 257 8-2 valid edge of tin0 pin and capture trigger of crn0 .......................................................................... ......... 258 8-3 valid edge of tin1 pin and capture trigger of crn0 .......................................................................... ......... 258 8-4 valid edge of tin0 pin and capture trigger of crn1 .......................................................................... ......... 259 8-5 configuration of timers 5 and 6 ............................................................................................. ....................... 297 9-1 interval time of interval timer............................................................................................. .......................... 310 9-2 configuration of watch timer................................................................................................ ........................ 310 9-3 interval time of interval timer............................................................................................. .......................... 314 10-1 loop detection time of watchdog timer...................................................................................... ................ 317 10-2 interval time of interval timer............................................................................................ ........................... 317 10-3 watchdog timer configuration............................................................................................... ....................... 318 10-4 loop detection time of watchdog timer...................................................................................... ................ 321 10-5 interval time of interval timer............................................................................................ ........................... 322 11-1 configuration of csin ...................................................................................................... .............................. 325 11-2 configuration of csi4 ...................................................................................................... .............................. 331 11-3 csin configuration ......................................................................................................... ............................... 344 11-4 sckn pin output status..................................................................................................... ........................... 369 11-5 son pin output status ...................................................................................................... ............................ 369 11-6 configuration of i 2 cn ............................................................................................................................. ........ 373 11-7 intiicn generation timing and wait control................................................................................. ............... 414 11-8 extension code bit definitions ............................................................................................. ......................... 415 11-9 status during arbitration and interrupt request generation timing.......................................................... ... 417 11-10 wait periods .............................................................................................................. .................................... 418 11-11 wait time ................................................................................................................. ..................................... 421 11-12 configuration of uartn .................................................................................................... ............................ 434 11-13 relationship between main clock and baud rate............................................................................. ........... 446 11-14 receive error causes ...................................................................................................... ............................. 452 12-1 configuration of a/d converter ............................................................................................. ........................ 456 13-1 internal ram area usable in dma ............................................................................................ .................... 473 13-2 start factor settings...................................................................................................... ................................ 478
32 user?s manual u15109ej3v0ud list of tables (3/4) table no. title page 17-1 table for wiring of adapter for pd70f3089y flash programming (fa-144gj-uen) .................................496 17-2 signal generation of dedicated flash programmer (pg-fp3)................................................................... ...499 17-3 pins used by serial interfaces ............................................................................................. .........................501 17-4 list of communication modes ................................................................................................ .......................505 17-5 flash memory control commands .............................................................................................. ..................506 17-6 response commands .......................................................................................................... .........................506 18-1 transfer rate and maximum number of transfer bytes in communication mode 1 ....................................508 18-2 contents of control bits................................................................................................... ..............................512 18-3 control field for locked slave unit ........................................................................................ .......................513 18-4 control field for unlocked slave unit...................................................................................... ......................513 18-5 control field acknowledge signal output conditions ......................................................................... ..........514 18-6 contents of telegraph length bit........................................................................................... .......................515 18-7 internal registers of iebus controller ..................................................................................... ......................524 18-8 reset conditions of flags in isr register .................................................................................. ..................536 18-9 interrupt source list ...................................................................................................... ................................545 18-10 communication error cause processing list................................................................................. ...............546 19-1 overview of functions ...................................................................................................... .............................559 19-2 configuration of messages and buffers ...................................................................................... ..................562 19-3 addresses of m_dlcn (n = 00 to 31) ......................................................................................... ...................576 19-4 addresses of m_ctrln (n = 00 to 31)........................................................................................ ..................579 19-5 addresses of m_timen (n = 00 to 31)........................................................................................ ...................580 19-6 addresses of m_datanx (n = 00 to 31, x = 0 to 7)........................................................................... ............582 19-7 addresses of m_idln and m_idhn (n = 00 to 31) .............................................................................. ..........584 19-8 addresses of m_confn (n = 00 to 31) ........................................................................................ .................586 19-9 addresses of m_statn (n = 00 to 31) ........................................................................................ ..................588 19-10 addresses of sc_statn (n = 00 to 31) ...................................................................................... ..................590 19-11 addresses of cnmaskla and cnmaskha (a = 0 to 3, n = 1, 2) ................................................................. .607 19-12 example when adding captured time stamp counter value to last 2 bytes of transmit message...........632 19-13 storage priority for data frame reception ................................................................................. ..................635 19-14 storage priority for remote frame reception............................................................................... ................635 19-15 priority of same priority level ........................................................................................... ............................635 19-16 frame type ................................................................................................................ ...................................639 19-17 rtr frame settings........................................................................................................ ..............................641 19-18 frame format setting (ide bit) and number of identifier (id) bits......................................................... .......641
user?s manual u15109ej3v0ud 33 list of tables (4/4) table no. title page 19-19 data length code settings ................................................................................................. .......................... 642 19-20 operation in error status................................................................................................. .............................. 646 19-21 operation when third bit of intermission is dominant level................................................................ ........ 646 19-22 field definitions of error frame .......................................................................................... .......................... 647 19-23 field definition of overload frame........................................................................................ ........................ 648 19-24 determination of bus priority............................................................................................. ............................ 649 19-25 bit stuffing .............................................................................................................. ....................................... 649 19-26 types of errors........................................................................................................... ................................... 650 19-27 error frame output timing ................................................................................................. .......................... 650 19-28 types of error statuses................................................................................................... .............................. 651 19-29 error counter............................................................................................................. .................................... 652 b-1 symbols in operand description.............................................................................................. ..................... 725 b-2 symbols used for op code.................................................................................................... ....................... 726 b-3 symbols used for operation description ...................................................................................... ................ 726 b-4 symbols used for flag operation ............................................................................................. .................... 727 b-5 condition codes............................................................................................................. ............................... 727
34 user?s manual u15109ej3v0ud chapter 1 introduction the v850/sc1, v850/sc2, and v850/sc3 are products in nec?s v850 series of single-chip microcontrollers designed for low-power operation. 1.1 general the v850/sc1, v850/sc2, and v850/sc3 are 32-bit single-chip microcontrollers that include the v850 series? cpu core, and peripheral functions such as rom/ram, a timer/counter, serial interfaces, an a/d converter, and a dma controller. the v850/sc2 is equivalent to the v850/sc1, but with an iebus (inter equipment bus tm ) controller added to the peripheral functions. the v850/sc3 has an fcan (full controller area network) controller added to the peripheral functions. in addition to high real-time response characteristics and 1-clock-pitch basic instructions, the v850/sc1, v850/sc2, and v850/sc3 can realize multiply, saturated operation, and bit manipulation instructions by means of a hardware multiplier. table 1-1 shows the outline of the v850/sc1, v850/sc2, and v850/sc3 lineup. table 1-1. product lineup of v850/sc1, v850/sc2, and v850/sc3 product name rom commercial name part number type size ram size fcan iebus pd703068y mask rom 512 kb 24 kb ?? v850/sc1 pd70f3089y flash memory 512 kb 24 kb ?? pd703069y mask rom 512 kb 24 kb ? v850/sc2 pd70f3089y flash memory 512 kb 24 kb ? 1 channel pd703088y 512 kb 24 kb 1 channel ? pd703089y mask rom 512 kb 24 kb ? v850/sc3 pd70f3089y flash memory 512 kb 24 kb 2 channels ?
chapter 1 introduction user?s manual u15109ej3v0ud 35 1.2 v850/sc1 1.2.1 features (v850/sc1) { number of instructions: 74 { minimum instruction execution time 50 ns (operating at 20 mhz, external power supply 5 v, regulator output 3.3 v) { general-purpose registers 32 bits 32 registers { instruction set signed multiplication (16 16 32): 100 ns (operating at 20 mhz) (able to execute instructions in parallel continuously without creating any register hazards) saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space 16 mb of linear address space (for programs and data) external expansion: expandable to 4 mb memory block allocation function: 2 mb per block programmable wait function idle state insertion function { external bus interface 16-bit data bus (address/data multiplexed) address bus: separate output possible 3 v to 5 v interface enabled bus hold function external wait function { internal memory pd703068y (mask rom: 512 kb/ram: 24 kb) pd70f3089y (flash memory: 512 kb/ram: 24 kb) { interrupts and exceptions non-maskable interrupts: 2 sources maskable interrupts: 49 sources software exceptions: 32 sources exception trap: 1 source { i/o lines total: 124 (12 input ports and 112 i/o ports) 3 v to 5 v interface enabled { timer/counter 16-bit timer: 8 channels (tm0, tm1, tm7 to tm12) 16-bit timer: 2 channels (tm5, tm6) { watch timer when operating on subclock or main clock: 1 channel operation using the subclock or main clock is also possible in the idle mode. { watchdog timer 1 channel
chapter 1 introduction 36 user?s manual u15109ej3v0ud { serial interfaces (sio) asynchronous serial interface (uart) 3-wire serial i/o (csi) i 2 c bus interface (i 2 c) 8- to 16-bit variable-length serial interface csi (8-bit)/uart: 1 channel csi (8- to 16-bit variable)/uart: 1 channel csi (8-bit)/i 2 c: 2 channels csi (8- or 16-bit): 2 channels uart: 2 channels dedicated baud rate generator: 5 channels { a/d converter 10-bit resolution: 12 channels { dma controller internal ram on-chip peripheral i/o: 6 channels { rom correction 4 correction addresses specifiable { regulator 3.5 v to 5.5 v input internal 3.3 v { key return function 4 to 8 pins selectable, falling edge fixed { clock generator during main clock or subclock operation 5-level cpu clock (including sub operations) { power save functions halt/idle/stop modes { package 144-pin plastic lqfp (20 20 mm) { cmos structure all static circuits 1.2.2 application fields (v850/sc1) av equipment such as car audio and home audio 1.2.3 ordering information (v850/sc1) part number package internal rom pd703068ygj- -uen pd70f3089ygj-uen note 144-pin plastic lqfp (20 20) 144-pin plastic lqfp (20 20) mask rom flash memory note under development remarks 1. indicates rom code suffix. 2. romless devices are not provided.
chapter 1 introduction user?s manual u15109ej3v0ud 37 1.2.4 pin configuration (top view) (v850/sc1) 144-pin plastic lqfp (20 20) ? pd703068ygj- -uen ? pd70f3089ygj-uen p80/ani8 p81/ani9 p82/ani10 p83/ani11 portgnd0 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/ad8 p51/ad9 p52/ad10 p53/ad11 p54/ad12 p55/ad13 p56/ad14 p57/ad15 portv dd0 p60/a16 p61/a17 p62/a18 p63/a19 p64/a20 p65/a21 p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p94/astb p95/hldak p96/hldrq clkout p141/so3/txd1 p140/si3/rxd1 p133 p132 p131 p130 portv dd2 p127/to11 p126/to10 p125/so6 p124/si6 p123/sck6 p04/intp3 p122/so5 p121/si5 p120/sck5 portgnd1 p27 p26 p25/to9 p24/ti91 p23/ti90 p22/sck2/scl1 p21/so2 p20/si2/sda1 p37/intp9 p36/a15/intp8 p35/a14/intp7 p34/a13/ti71 p33/to8 p32/ti81 p31/ti80 p30/ti6/to6 p00/nmi x2 x1 gnd0 cpureg v dd0 reset mode/v pp note p10/si0/sda0 p11/so0 p12/sck0/scl0 p01/intp0 p13/si4/rxd0 p14/so4/txd0 p15/sck4/asck0 p16 p17/ti5/to5 p110/a1/wait p111/a2 p112/a3 p113/a4 p114 p115 p02/intp1 p116 p117 portv dd1 p100/a5/kr0/to7 p101/a6/kr1/ti70 p102/a7/kr2/ti00 p103/a8/kr3/ti01 p104/a9/kr4/to0 p105/a10/kr5/ti10 p106/a11/kr6/ti11 p107/a12/kr7/to1 p03/intp2 xt2 xt1 gnd2 adcgnd adcv dd p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 p176/vm45 p175 p174 gnd1 p173 p172 v dd1 p171 p170 p07/intp6 p157/ti121 p156/ti120 p155/to12 p154/ti111 p153/ti110 p152/asck3 p151/txd3 p150/rxd3 p06/intp5 p147/ti101 p146/ti100 p145/asck2 p144/txd2 p143/rxd2 p05/intp4/adtrg p142/sck3/asck1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 note pd703068y: mode pd70f3089y: v pp (connect to either gnd0, gnd1, or gnd2 in normal operation mode)
chapter 1 introduction 38 user ? s manual u15109ej3v0ud pin names (v850/sc1) a1 to a21: address bus p120 to p127: port 12 ad0 to ad15: address/data bus p130 to p133: port 13 adcgnd: ground for analog p140 to p147: port 14 adcv dd power supply for analog p150 to p157: port 15 adtrg: a/d trigger input p170 to p176: port 17 ani0 to ani11: analog input rd: read strobe asck0 to asck3: asynchronous serial clock reset: reset astb: address strobe r/w: read/write status clkout: clock output rxd0 to rxd3: receive data cpureg: regulator control sck0, sck2 to dstb: data strobe sck6: serial clock gnd0 to gnd2: ground scl0, scl1: serial clock hldak: hold acknowledge sda0, sda1: serial data hldrq: hold request si0, si2 to si6: serial input intp0 to intp9: interrupt request from peripherals so0, so2 to so6: serial output kr0 to kr7 : key return ti00, ti01, ti10, lben: lower byte enable ti11, ti100, ti101, mode: mode ti110, ti111, ti120, nmi: non-maskable interrupt request ti121, ti5, ti6, ti70, portgnd0, ti71, ti80, ti81, portgnd1: ground for ports ti90, ti91: timer input portv dd0 to to0, to1, portv dd2 : power supply for ports to5 to to12: timer output p00 to p07: port 0 txd0 to txd3: transmit data p10 to p17: port 1 uben: upper byte enable p20 to p27: port 2 v dd0 , v dd1 : power supply p30 to p37: port 3 vm45: v dd = 4.5 v monitor output p40 to p47: port 4 v pp : programming power supply p50 to p57: port 5 wait: wait p60 to p65: port 6 wrh: write strobe high-level data p70 to p77: port 7 wrl: write strobe low-level data p80 to p83: port 8 x1, x2: crystal for main clock p90 to p96: port 9 xt1, xt2: crystal for sub-clock p100 to p107: port 10 p110 to p117: port 11
chapter 1 introduction user ? s manual u15109ej3v0ud 39 1.2.5 function blocks (v850/sc1) (1) internal block diagram rom cpu pc hldrq (p96) hldak (p95) ad0 to ad15 (p40 to p47, p50 to p57) a16 to a21 (p60 to p65) a1 to a15 (p34 to p36, p100 to p107, p110 to 113) astb (p94) dstb/rd (p93) r/w/wrh (p92) 0uben (p91) lben/wrl (p90) wait(p110) multiplier 16 16 32 rom correction 32-bit barrel shifter system registers general-purpose registers 32 bits 32 512 kb ram 24 kb intc sio csi0/i 2 c0 csi2/i 2 c1 csi3/uart1 csi4/uart0 csi6 uart2 so0 si0/sda0 sck0/scl0 timer counter (16-bit timer) tm0, tm1 tm7 to tm12 tm5, tm6 nmi intp0 to intp9 ti00, ti01,ti10, ti11 ti70, ti71, ti80, ti81 ti90, ti91, ti100, ti101 ti110, ti111, ti120, ti121 to0, to1, to7 to to12 ti5, to5, ti6, to6 so2 si2/sda1 sck2/scl1 so3/txd1 si3/rxd1 sck3/asck1 so4/txd0 si4/rxd0 sck4/asck0 so5 si5 sck5 key return function dmac: 6 ch watch timer watchdog timer kr0 to kr7 so6 si6 sck6 txd2 rxd2 asck2 uart3 txd3 rxd3 asck3 alu ports instruction queue bcu p170 to p176 p150 to p157 p140 to p147 p130 to p133 p120 to p127 p110 to p117 p100 to p107 p90 to p96 p80 to p83 p70 to p77 p60 to p65 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p17 p00 to p07 portv dd0 to portv dd2 portgnd0, portgnd1 a/d converter clkout x1 x2 xt1 xt2 reset v dd0 gnd0 vm45 v dd0 gnd0 vm45 v dd1 portv dd0 portv dd1 portv dd2 portgnd0 portgnd1 gnd1 gnd2 v pp /mode note cpureg adcv dd adcgnd ani0 to ani11 adtrg cg 3.3 v regulator csi5 note pd703068y: mode pd70f3089y: v pp (connect to either gnd0, gnd1, or gnd2 in normal operating mode)
chapter 1 introduction 40 user ? s manual u15109ej3v0ud (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions. (b) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an instruction queue. (c) rom this consists of a 512 kb mask rom or flash memory mapped to the address space starting at 00000000h. rom can be accessed by the cpu in one clock cycle during instruction fetch. (d) ram this consists of a 24 kb ram mapped to the address space starting at ffff9000h. ram can be accessed by the cpu in one clock cycle during data access. (e) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp9) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) clock generator (cg) the clock generator includes two types of oscillators: one for the main clock (f xx ) and one for the subclock (f xt ), generates five types of clocks (f xx , f xx /2, f xx /4, f xx /8, and f xt ), and supplies one of them as the operating clock for the cpu (f cpu ). (g) timer/counter a ten-channel 16-bit timer/event counter is incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. (h) watch timer this timer counts the reference time period (0.5 second) for counting the clock (the 32.768 khz subclock or the 8.388 mhz main clock). at the same time, the watch timer can be used as an interval timer for the main clock. (i) watchdog timer a watchdog timer is provided to detect inadvertent program loops and system abnormalities, etc. it can also be used as an interval timer. when used as a watchdog timer, it generates a non-maskable interrupt request (intwdt) after an overflow occurs. when used as an interval timer, it generates a maskable interrupt request (intwdtm) after an overflow occurs.
chapter 1 introduction user ? s manual u15109ej3v0ud 41 (j) serial interfaces (sio) the v850/sc1 includes four kinds of serial interfaces: an asynchronous serial interface (uartm), a 3- wire serial i/o (csin), and an i 2 c bus interface (i 2 cx), which can use up to eight channels at the same time. two of these channels are switchable between the uart and csi and another two are switchable between csi and i 2 c. for uartm, data is transferred via the txdm and rxdm pins. for csin, data is transferred via the son, sin, and sckn pins. for i 2 cx, data is transferred via the sdax and sclx pins. for uart and csi4, a dedicated baud rate generator is provided. remark m = 0 to 3 n = 0, 2 to 6 x = 0, 1 (k) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 12 analog input pins. conversion is performed using the successive approximation method. (l) dma controller a six-channel dma controller is incorporated. this controller transfers data between the internal ram and on-chip peripheral i/o devices in response to interrupt requests sent by on-chip peripheral i/o. (m) ports as shown below, the following ports have general-purpose port functions and control pin functions. port i/o port function control function port 0 8-bit i/o nmi, external interrupt, a/d converter trigger port 1 8-bit i/o serial interface, timer i/o port 2 8-bit i/o serial interface, timer i/o port 3 8-bit i/o timer i/o, external address bus, external interrupt port 4 8-bit i/o port 5 8-bit i/o external address/data bus port 6 6-bit i/o external address bus port 7 8-bit input port 8 4-bit input a/d converter analog input port 9 7-bit i/o external bus interface control signal i/o port 10 8-bit i/o timer i/o, key return input, external address bus port 11 8-bit i/o wait control, external address bus port 12 8-bit i/o serial interface, timer output port 13 4-bit i/o ? port 14 8-bit i/o serial interface, timer input port 15 8-bit i/o serial interface, timer i/o port 17 7-bit i/o general- purpose port v dd0 = 4.5 v monitor output
chapter 1 introduction 42 user ? s manual u15109ej3v0ud 1.3 v850/sc2 1.3.1 features (v850/sc2) { number of instructions: 74 { minimum instruction execution time 53 ns (operating at 18.87 mhz, external power supply 5 v, regulator output 3.3 v) { general-purpose registers 32 bits 32 registers { instruction set signed multiplication (16 16 32): 106 ns (operating at 18.87 mhz) (able to execute instructions in parallel continuously without creating any register hazards) saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space 16 mb of linear address space (for programs and data) external expansion: expandable to 4 mb memory block allocation function: 2 mb per block programmable wait function idle state insertion function { external bus interface 16-bit data bus (address/data multiplexed) address bus: separate output possible 3 v to 5 v interface enabled bus hold function external wait function { internal memory pd703069y (mask rom: 512 kb/ram: 24 kb) pd70f3089y (flash memory: 512 kb/ram: 24 kb) { interrupts and exceptions non-maskable interrupts: 2 sources maskable interrupts: 51 sources software exceptions: 32 sources exception trap: 1 source { i/o lines total: 124 (12 input ports and 112 i/o ports) 3 v to 5 v interface enabled { timer/counter 16-bit timer: 8 channels (tm0, tm1, tm7 to tm12) 16-bit timer: 2 channels (tm5, tm6) { watch timer when operating on subclock or main clock: 1 channel operation using the subclock or main clock is also possible in the idle mode. { watchdog timer 1 channel
chapter 1 introduction user ? s manual u15109ej3v0ud 43 { serial interfaces (sio) asynchronous serial interface (uart) 3-wire serial i/o (csi) i 2 c bus interface (i 2 c) 8- to 16-bit variable-length serial interface csi (8-bit)/uart: 1 channel csi (8- to 16-bit variable)/uart: 1 channel csi (8-bit)/i 2 c: 2 channels csi (8- or 16-bit): 2 channels uart: 2 channels dedicated baud rate generator: 5 channels { a/d converter 10-bit resolution: 12 channels { dma controller internal ram on-chip peripheral i/o: 6 channels { rom correction 4 correction addresses specifiable { regulator 3.5 v to 5.5 v input internal 3.3 v { key return function 4 to 8 pins selectable, falling edge fixed { clock generator during main clock or subclock operation 5-level cpu clock (including sub operations) { power save functions halt/idle/stop modes { iebus controller 1 channel { package 144-pin plastic lqfp (20 20 mm) { cmos structure all static circuits 1.3.2 application fields (v850/sc2) car audio equipment 1.3.3 ordering information (v850/sc2) part number package internal rom pd703069ygj- -uen pd70f3089ygj-uen note 144-pin plastic lqfp (20 20) 144-pin plastic lqfp (20 20) mask rom flash memory note under development remarks 1. indicates rom code suffix. 2. romless devices are not provided.
chapter 1 introduction 44 user ? s manual u15109ej3v0ud 1.3.4 pin configuration (top view) (v850/sc2) 144-pin plastic lqfp (20 20) ? pd703069ygj- -uen ? pd70f3089ygj-uen p80/ani8 p81/ani9 p82/ani10 p83/ani11 portgnd0 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/ad8 p51/ad9 p52/ad10 p53/ad11 p54/ad12 p55/ad13 p56/ad14 p57/ad15 portv dd0 p60/a16 p61/a17 p62/a18 p63/a19 p64/a20 p65/a21 p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p94/astb p95/hldak p96/hldrq clkout p141/so3/txd1 p140/si3/rxd1 p133 p132 p131 p130 portv dd2 p127/to11 p126/to10 p125/so6 p124/si6 p123/sck6 p04/intp3 p122/so5 p121/si5 p120/sck5 portgnd1 p27/ietx0 p26/ierx0 p25/to9 p24/ti91 p23/ti90 p22/sck2/scl1 p21/so2 p20/si2/sda1 p37/intp9 p36/a15/intp8 p35/a14/intp7 p34/a13/ti71 p33/to8 p32/ti81 p31/ti80 p30/ti6/to6 p00/nmi x2 x1 gnd0 cpureg v dd0 reset mode/v pp note p10/si0/sda0 p11/so0 p12/sck0/scl0 p01/intp0 p13/si4/rxd0 p14/so4/txd0 p15/sck4/asck0 p16 p17/ti5/to5 p110/a1/wait p111/a2 p112/a3 p113/a4 p114 p115 p02/intp1 p116 p117 portv dd1 p100/a5/kr0/to7 p101/a6/kr1/ti70 p102/a7/kr2/ti00 p103/a8/kr3/ti01 p104/a9/kr4/to0 p105/a10/kr5/ti10 p106/a11/kr6/ti11 p107/a12/kr7/to1 p03/intp2 xt2 xt1 gnd2 adcgnd adcv dd p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 p176/vm45 p175 p174 gnd1 p173 p172 v dd1 p171 p170 p07/intp6 p157/ti121 p156/ti120 p155/to12 p154/ti111 p153/ti110 p152/asck3 p151/txd3 p150/rxd3 p06/intp5 p147/ti101 p146/ti100 p145/asck2 p144/txd2 p143/rxd2 p05/intp4/adtrg p142/sck3/asck1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 note pd703069y: mode pd70f3089y: v pp (connect to either gnd0, gnd1, or gnd2 in normal operating mode)
chapter 1 introduction user ? s manual u15109ej3v0ud 45 pin names (v850/sc2) a1 to a21: address bus p100 to p107: port 10 ad0 to ad15: address/data bus p110 to p117: port 11 adcgnd: ground for analog p120 to p127: port 12 adcv dd power supply for analog p130 to p133: port 13 adtrg: a/d trigger input p140 to p147: port 14 ani0 to ani11: analog input p150 to p157: port 15 asck0 to asck3: asynchronous serial clock p170 to p176: port 17 astb: address strobe rd: read strobe clkout: clock output reset: reset cpureg: regulator control r/w: read/write status dstb: data strobe rxd0 to rxd3: receive data gnd0 to gnd2: ground sck0, sck2 to hldak: hold acknowledge sck6: serial clock hldrq: hold request scl0, scl1: serial clock ierx0: iebus receive data sda0, sda1: serial data ietx0: iebus transmit data si0, si2 to si6: serial input intp0 to intp9: interrupt request from peripherals so0, so2 to so6: serial output kr0 to kr7 : key return ti00, ti01, ti10, lben: lower byte enable ti11, ti100, ti101, mode: mode ti110, ti111, ti120, nmi: non-maskable interrupt request ti121, ti5, ti6, ti70, portgnd0, ti71, ti80, ti81, portgnd1: ground for ports ti90, ti91: timer input portv dd0 to to0, to1, portv dd2 : power supply for ports to5 to to12: timer output p00 to p07: port 0 txd0 to txd3: transmit data p10 to p17: port 1 uben: upper byte enable p20 to p27: port 2 v dd0 , v dd1 : power supply p30 to p37: port 3 vm45: v dd = 4.5 v monitor output p40 to p47: port 4 v pp : programming power supply p50 to p57: port 5 wait: wait p60 to p65: port 6 wrh: write strobe high-level data p70 to p77: port 7 wrl: write strobe low-level data p80 to p83: port 8 x1, x2: crystal for main clock p90 to p96: port 9 xt1, xt2: crystal for sub-clock
chapter 1 introduction 46 user ? s manual u15109ej3v0ud 1.3.5 function blocks (v850/sc2) (1) internal block diagram rom cpu pc hldrq (p96) hldak (p95) ad0 to ad15 (p40 to p47, p50 to p57) a16 to a21 (p60 to p65) a1 to a15 (p34 to p36, p100 to p107, p110 to 113) astb (p94) dstb/rd (p93) r/w/wrh (p92) uben (p91) lben/wrl (p90) wait (p110) multiplier 16 16 32 rom correction 32-bit barrel shifter system registers general-purpose registers 32 bits 32 512 kb ram 24 kb intc sio csi0/i 2 c0 csi2/i 2 c1 csi3/uart1 csi6 uart2 so0 si0/sad0 sck0/scl0 timer counter (16-bit timer) tm0, tm1, tm7 to tm12 tm5, tm6 nmi intp0 to intp9 ti00, ti01,ti10, ti11 ti70, ti71, ti80, ti81 ti90, ti91, ti100, ti101 ti110, ti111, ti120, ti121 to0, to1, to7 to to12 ti5, to5, ti6, to6 so2 si2/sda1 sck2/scl1 so3/txd1 si3/rxd1 sck3/asck1 so4/txd0 si4/rxd0 sck4/asck0 so5 si5 sck5 key return function dmac: 6 ch watch timer watchdog timer iebus kr0 to kr7 so6 si6 sck6 txd2 rxd2 asck2 uart3 txd3 rxd3 asck3 ietx0 ierx0 alu ports instruction queue bcu p170 to p176 p150 to p157 p140 to p147 p130 to p133 p120 to p127 p110 to p117 p100 to p107 p90 to p96 p80 to p83 p70 to p77 p60 to p65 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p17 p00 to p07 portv dd0 to portv dd2 portgnd0, portgnd1 a/d converter clkout x1 x2 xt1 xt2 reset adcv dd adcgnd ani0 to ani11 adtrg cg v dd0 gnd0 vm45 v dd0 gnd0 vm45 v dd1 portv dd0 portv dd1 portv dd2 portgnd0 portgnd1 gnd1 gnd2 v pp /mode note cpureg 3.3 v regulator csi4/uart0 csi5 note pd703069y: mode pd70f3089y: v pp (connect to either gnd0, gnd1, or gnd2 in normal operating mode)
chapter 1 introduction user ? s manual u15109ej3v0ud 47 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions. (b) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an instruction queue. (c) rom this consists of a 512 kb mask rom or flash memory mapped to the address space starting at 00000000h. rom can be accessed by the cpu in one clock cycle during instruction fetch. (d) ram this consists of a 24 kb ram mapped to the address space starting at ffff9000h. ram can be accessed by the cpu in one clock cycle during data access. (e) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp9) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) clock generator (cg) the clock generator includes two types of oscillators: one for the main clock (f xx ) and one for the subclock (f xt ), generates five types of clocks (f xx , f xx /2, f xx /4, f xx /8, and f xt ), and supplies one of them as the operating clock for the cpu (f cpu ). (g) timer/counter a ten-channel 16-bit timer/event counter is incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. (h) watch timer this timer counts the reference time period (0.5 second) for counting the clock (the 32.768 khz subclock or the 8.388 mhz main clock). at the same time, the watch timer can be used as an interval timer for the main clock. (i) watchdog timer a watchdog timer is provided to detect inadvertent program loops and system abnormalities, etc. it can also be used as an interval timer. when used as a watchdog timer, it generates a non-maskable interrupt request (intwdt) after an overflow occurs. when used as an interval timer, it generates a maskable interrupt request (intwdtm) after an overflow occurs.
chapter 1 introduction 48 user ? s manual u15109ej3v0ud (j) serial interfaces (sio) the v850/sc2 includes four kinds of serial interfaces: an asynchronous serial interface (uartm), a 3- wire serial i/o (csin), and an i 2 c bus interface (i 2 cx), which can use up to eight channels at the same time. two of these channels are switchable between the uart and csi and another two are switchable between csi and i 2 c. for uartm, data is transferred via the txdm and rxdm pins. for csin, data is transferred via the son, sin, and sckn pins. for i 2 cx, data is transferred via the sdax and sclx pins. for uart and csi4, a dedicated baud rate generator is provided. remark m = 0 to 3 n = 0, 2 to 6 x = 0, 1 (k) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 12 analog input pins. conversion is performed using the successive approximation method. (l) dma controller a six-channel dma controller is incorporated. this controller transfers data between the internal ram and on-chip peripheral i/o devices in response to interrupt requests sent by on-chip peripheral i/o. (m) ports as shown below, the following ports have general-purpose port functions and control pin functions. port i/o port function control function port 0 8-bit i/o nmi, external interrupt, a/d converter trigger port 1 8-bit i/o serial interface, timer i/o port 2 8-bit i/o serial interface, timer i/o, iebus data i/o port 3 8-bit i/o timer i/o, external address bus, external interrupt port 4 8-bit i/o port 5 8-bit i/o external address/data bus port 6 6-bit i/o external address bus port 7 8-bit input port 8 4-bit input a/d converter analog input port 9 7-bit i/o external bus interface control signal i/o port 10 8-bit i/o timer i/o, key return input, external address bus port 11 8-bit i/o wait control, external address bus port 12 8-bit i/o serial interface, timer output port 13 4-bit i/o ? port 14 8-bit i/o serial interface, timer input port 15 8-bit i/o serial interface, timer i/o port 17 7-bit i/o general- purpose port v dd0 = 4.5 v monitor output (n) iebus controller the iebus controller is a small digital data transmission system for transferring data between units and is incorporated in the v850/sc2 only.
chapter 1 introduction user ? s manual u15109ej3v0ud 49 1.4 v850/sc3 1.4.1 features (v850/sc3) { number of instructions: 74 { minimum instruction execution time 50 ns (operating at 20 mhz, external power supply 5 v, regulator output 3.3 v) { general-purpose registers 32 bits 32 registers { instruction set signed multiplication (16 16 32): 100 ns (operating at 16 mhz) (able to execute instructions in parallel continuously without creating any register hazards) saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space 16 mb of linear address space (for programs and data) external expansion: expandable to 4 mb memory block allocation function: 2 mb per block programmable wait function idle state insertion function { external bus interface 16-bit data bus (address/data multiplexed) 3 v to 5 v interface enabled bus hold function external wait function { internal memory pd703088y, 703089y (mask rom: 512 kb/ram: 24 kb) pd70f3089y (flash memory: 512 kb/ram: 24 kb) { interrupts and exceptions non-maskable interrupts: 2 sources maskable interrupts: 53 sources ( pd703088y) 56 sources ( pd703089y, 70f3089y) software exceptions: 32 sources exception trap: 1 source { i/o lines total: 124 (12 input ports and 112 i/o ports) 3 v to 5 v interface enabled { timer/counter 16-bit timer: 8 channels (tm0, tm1, tm7 to tm12) 16-bit timer: 2 channels (tm5, tm6) { watch timer when operating on subclock or main clock: 1 channel operation using the subclock or main clock is also possible in the idle mode. { watchdog timer 1 channel
chapter 1 introduction 50 user ? s manual u15109ej3v0ud { serial interfaces (sio) asynchronous serial interface (uart) 3-wire serial i/o (csi) i 2 c bus interface (i 2 c) 8- to 16-bit variable-length serial interface csi (8-bit)/uart: 1 channel csi (8- to 16-bit variable)/uart: 1 channel csi (8-bit)/i 2 c: 2 channels csi (8- or 16-bit): 2 channels uart: 2 channels dedicated baud rate generator: 5 channels { a/d converter 10-bit resolution: 12 channels { dma controller internal ram on-chip peripheral i/o: 6 channels { rom correction 4 correction addresses specifiable { regulator 3.5 v to 5.5 v input internal 3.3 v { key return function 4 to 8 pins selectable, falling edge fixed { clock generator during main clock or subclock operation 5-level cpu clock (including sub operations) { power save functions halt/idle/stop modes { fcan controller 2 channels ( pd703089y, 70f3089y) 1 channel ( pd703088y) { package 144-pin plastic lqfp (20 20 mm) { cmos structure all static circuits 1.4.2 application fields (v850/sc3) car audio equipment 1.4.3 ordering information (v850/sc3) part number package internal rom pd703088ygj- -uen note pd703089ygj- -uen note pd70f3089ygj-uen note 144-pin plastic lqfp (20 20) 144-pin plastic lqfp (20 20) 144-pin plastic lqfp (20 20) mask rom mask rom flash memory note under development remarks 1. indicates rom code suffix. 2. romless devices are not provided.
chapter 1 introduction user ? s manual u15109ej3v0ud 51 1.4.4 pin configuration (top view) (v850/sc3) 144-pin plastic lqfp (20 20) ? pd703088ygj- -uen ? pd703089ygj- -uen ? pd70f3089ygj-uen p80/ani8 p81/ani9 p82/ani10 p83/ani11 portgnd0 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/ad8 p51/ad9 p52/ad10 p53/ad11 p54/ad12 p55/ad13 p56/ad14 p57/ad15 portv dd0 p60/a16 p61/a17 p62/a18 p63/a19 p64/a20 p65/a21 p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p94/astb p95/hldak p96/hldrq clkout p141/so3/txd1 p140/si3/rxd1 p133 p132 p131 p130 portv dd2 p127/to11 p126/to10 p125/so6 p124/si6 p123/sck6 p04/intp3 p122/so5 p121/si5 p120/sck5 portgnd1 p27 p26 p25/to9 p24/ti91 p23/ti90 p22/sck2/scl1 p21/so2 p20/si2/sda1 p37/intp9 p36/a15/intp8 p35/a14/intp7 p34/a13/ti71 p33/to8 p32/ti81 p31/ti80 p30/ti6/to6 p00/nmi x2 x1 gnd0 cpureg v dd0 reset mode/v pp note 1 p10/si0/sda0 p11/so0 p12/sck0/scl0 p01/intp0 p13/si4/rxd0 p14/so4/txd0 p15/sck4/asck0 p16 p17/ti5/to5 p110/a1/wait p111/a2 p112/a3 p113/a4 p114/cantx1 p115/canrx1 p02/intp1 p116/cantx2 note 2 p117/canrx2 note 2 portv dd1 p100/a5/kr0/to7 p101/a6/kr1/ti70 p102/a7/kr2/ti00 p103/a8/kr3/ti01 p104/a9/kr4/to0 p105/a10/kr5/ti10 p106/a11/kr6/ti11 p107/a12/kr7/to1 p03/intp2 xt2 xt1 gnd2 adcgnd adcv dd p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 p176/vm45 p175 p174 gnd1 p173 p172 v dd1 p171 p170 p07/intp6 p157/ti121 p156/ti120 p155/to12 p154/ti111 p153/ti110 p152/asck3 p151/txd3 p150/rxd3 p06/intp5 p147/ti101 p146/ti100 p145/asck2 p144/txd2 p143/rxd2 p05/intp4/adtrg p142/sck3/asck1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 notes 1. pd703088y, 703089y: mode pd70f3089y: v pp (connect to either gnd0, gnd1, or gnd2 in normal operating mode) 2. cantx2 and canrx2 are available only for the pd703089y and 70f3089y.
chapter 1 introduction 52 user ? s manual u15109ej3v0ud pin names (v850/sc3) a16 to a21: address bus p80 to p83: port 8 ad0 to ad15: address/data bus p90 to p96: port 9 adcgnd: ground for analog p100 to p107: port 10 adcv dd power supply for analog p110 to p117: port 11 adtrg: a/d trigger input p120 to p127: port 12 ani0 to ani11: analog input p130 to p133: port 13 asck0 to asck3: asynchronous serial clock p140 to p147: port 14 astb: address strobe p150 to p157: port 15 canrx1, canrx2: fcan receive data p170 to p176: port 17 cantx1, cantx2: fcan transmit data reset: reset clkout: clock output r/w: read/write status cpureg: regulator control rxd0 to rxd3: receive data dstb: data strobe sck0, sck2 to gnd0 to gnd2: ground sck6: serial clock hldak: hold acknowledge scl0, scl1: serial clock hldrq: hold request sda0, sda1: serial data intp0 to intp9: interrupt request from peripherals si0, si2 to si6: serial i nput kr0 to kr7 : key return so0, so2 to so6: serial output lben: lower byte enable ti00, ti01, ti10, mode: mode ti11, ti100, ti101, nmi: non-maskable interrupt request ti110, ti111, ti120, portgnd0, ti121, ti5, ti6, ti70, portgnd1: ground for ports ti71, ti80, ti81, portv dd0 to ti90, ti91: timer input portv dd2 : power supply for ports to0, to1, p00 to p07: port 0 to5 to to12: timer output p10 to p17: port 1 txd0 to txd3: transmit data p20 to p27: port 2 uben: upper byte enable p30 to p37: port 3 v dd0 , v dd1 : power supply p40 to p47: port 4 vm45: v dd = 4.5 v monitor output p50 to p57: port 5 v pp : programming power supply p60 to p65: port 6 wait: wait p70 to p77: port 7 x1, x2: crystal for main clock xt1, xt2: crystal for sub-clock
chapter 1 introduction user ? s manual u15109ej3v0ud 53 1.4.5 function blocks (v850/sc3) (1) internal block diagram rom cpu pc hldrq (p96) hldak (p95) ad0 to ad15 (p40 to p47, p50 to p57) a16 to a21 (p60 to p65) astb (p94) dstb/rd (p93) r/w/wrh (p92) uben (p91) lben/wrl (p90) wait (p110) multiplier 16 16 32 rom correction 32-bit barrel shifter system registers general-purpose registers 32 bits 32 512 kb ram 24 kb intc sio csi0/i 2 c0 csi2/i 2 c1 csi3/uart1 csi6 uart2 so0 si0/sad0 sck0/scl0 timer counter (16-bit timer) tm0, tm1, tm7 to tm12 tm5, tm6 nmi intp0 to intp9 ti00, ti01,ti10, ti11 ti70, ti71, ti80, ti81 ti90, ti91, ti100, ti101 ti110, ti111, ti120, ti121 to0, to1, to7 to to12 ti5, to5, ti6, to6 so2 si2/sda1 sck2/scl1 so3/txd1 si3/rxd1 sck3/asck1 so4/txd0 si4/rxd0 sck4/asck0 so5 si5 sck5 key return function dmac: 6 ch watch timer watchdog timer kr0 to kr7 so6 si6 sck6 txd2 rxd2 asck2 uart3 txd3 rxd3 asck3 fcan cantx1 canrx1 cantx2 note 1 canrx2 note 1 alu ports instruction queue bcu p170 to p176 p150 to p157 p140 to p147 p130 to p133 p120 to p127 p110 to p117 p100 to p107 p90 to p96 p80 to p83 p70 to p77 p60 to p65 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p17 p00 to p07 portv dd0 to portv dd2 portgnd0, portgnd1 a/d converter clkout x1 x2 xt1 xt2 reset cg v dd0 gnd0 vm45 v dd0 gnd0 vm45 cpureg 3.3 v regulator v dd1 portv dd0 portv dd1 portv dd2 portgnd0 portgnd1 gnd1 gnd2 v pp /mode note 2 csi4/uart0 csi5 csi2/i 2 c1 csi2/i 2 c1 adcv dd adcgnd ani0 to ani11 adtrg notes 1. pd703089y, 70f3089y only 2. pd703088y, 703089y: mode pd70f3089y: v pp (connect to either gnd0, gnd1, or gnd2 in normal operating mode)
chapter 1 introduction 54 user ? s manual u15109ej3v0ud (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions. (b) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an instruction queue. (c) rom this consists of a 512 kb mask rom or flash memory mapped to the address space starting at 00000000h. rom can be accessed by the cpu in one clock cycle during instruction fetch. (d) ram this consists of a 24 kb ram mapped to the address space starting at ffff9000h. ram can be accessed by the cpu in one clock cycle during data access. (e) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp9) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) clock generator (cg) the clock generator includes two types of oscillators: one for the main clock (f xx ) and one for the subclock (f xt ), generates five types of clocks (f xx , f xx /2, f xx /4, f xx /8, and f xt ), and supplies one of them as the operating clock for the cpu (f cpu ). (g) timer/counter a ten-channel 16-bit timer/event counter is incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. (h) watch timer this timer counts the reference time period (0.5 second) for counting the clock (the 32.768 khz subclock or the 8.388 mhz main clock). at the same time, the watch timer can be used as an interval timer for the main clock. (i) watchdog timer a watchdog timer is provided to detect inadvertent program loops and system abnormalities, etc. it can also be used as an interval timer. when used as a watchdog timer, it generates a non-maskable interrupt request (intwdt) after an overflow occurs. when used as an interval timer, it generates a maskable interrupt request (intwdtm) after an overflow occurs.
chapter 1 introduction user ? s manual u15109ej3v0ud 55 (j) serial interfaces (sio) the v850/sc3 includes four kinds of serial interfaces: an asynchronous serial interface (uartm), a 3- wire serial i/o (csin), and an i 2 c bus interface (i 2 cx), which can use up to eight channels at the same time. two of these channels are switchable between the uart and csi and another two are switchable between csi and i 2 c. for uartm, data is transferred via the txdm and rxdm pins. for csin, data is transferred via the son, sin, and sckn pins. for i 2 cx, data is transferred via the sdax and sclx pins. for uart and csi4, a dedicated baud rate generator is provided. remark m = 0 to 3 n = 0, 2 to 6 x = 0, 1 (k) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 12 analog input pins. conversion is performed using the successive approximation method. (l) dma controller a six-channel dma controller is incorporated. this controller transfers data between the internal ram and on-chip peripheral i/o devices in response to interrupt requests sent by on-chip peripheral i/o. (m) ports as shown below, the following ports have general-purpose port functions and control pin functions. port i/o port function control function port 0 8-bit i/o nmi, external interrupt, a/d converter trigger port 1 8-bit i/o serial interface, timer i/o port 2 8-bit i/o serial interface, timer i/o port 3 8-bit i/o timer i/o, external address bus, external interrupt port 4 8-bit i/o port 5 8-bit i/o external address/data bus port 6 6-bit i/o external address bus port 7 8-bit input port 8 4-bit input a/d converter analog input port 9 7-bit i/o external bus interface control signal i/o port 10 8-bit i/o timer i/o, key return input, external address bus port 11 8-bit i/o wait control, fcan data i/o, external address bus port 12 8-bit i/o serial interface, timer output port 13 4-bit i/o ? port 14 8-bit i/o serial interface, timer input port 15 8-bit i/o serial interface, timer i/o port 17 7-bit i/o general- purpose port v dd0 = 4.5 v monitor output (n) fcan controller the fcan controller is a small digital data transmission system for transferring data between units. a two-channel fcan controller is incorporated in the pd703089y and 70f3089y (fcan1, fcan2). a one-channel fcan controller is incorporated in the pd703088y (fcan1).
user?s manual u15109ej3v0ud 56 chapter 2 pin functions 2.1 list of pin functions the names and functions of the pins in the v850/sc1, v850/sc2, and v850/sc3 are described below, divided into port pins and non-port pins. there are six types of pin i/o buffer power supplies: portv dd0 to portv dd2 , v dd0 , v dd1 , and adcv dd . the relationship between these power supplies and the pins is described below. table 2-1. pin i/o buffer power supplies (a) pd70f3089y power supply corresponding pins usable voltage range portv dd0 note 1 p40 to p47, p50 to p57, p60 to p65, p90 to p96, clkout 3.0 v portv dd0 5.5 v portv dd1 note 1 p00 to p03, p10 to p17, p30 to p37, p100 to p107, p110 to p117 3.0 v portv dd1 5.5 v note 2 portv dd2 note 1 p04 to p07, p20 to p27, p120 to p127, p130 to p133, p140 to p147, p150 to p157 3.0 v portv dd2 5.5 v note 2 v dd0 reset when a/d converter not used: 4.0 v v dd0 5.5 v when a/d converter used: 4.5 v v dd0 = adcv dd 5.5 v v dd1 p170 to p176 4.0 v v dd1 5.5 v adcv dd p70 to p77, p80 to p83 when a/d converter not used: 4.0 v adcv dd 5.5 v when a/d converter used: 4.5 v v dd0 = adcv dd 5.5 v notes 1. the electrical specifications differ between an operating frequency of 4 to 17 mhz and an operating frequency of 4 to 20 mhz. 2. when the fcan controller is used: portv dd1 portv dd2 (due to the supply voltage conditions of the in-circuit emulator) caution the conditions for the power supplies are as follows. portv dd0 portv dd1 portv dd2 v dd0 = v dd1 = adcv dd
chapter 2 pin functions user?s manual u15109ej3v0ud 57 (b) other than pd70f3089y power supply corresponding pins usable voltage range portv dd0 note 1 p40 to p47, p50 to p57, p60 to p65, p90 to p96, clkout 3.0 v portv dd0 5.5 v portv dd1 note 1 p00 to p03, p10 to p17, p30 to p37, p100 to p107, p110 to p117 3.0 v portv dd1 5.5 v note 2 portv dd2 note 1 p04 to p07, p20 to p27, p120 to p127, p130 to p133, p140 to p147, p150 to p157 3.0 v portv dd2 5.5 v note 2 v dd0 reset when a/d converter not used: 3.5 v v dd0 5.5 v when a/d converter used: 4.5 v v dd0 = adcv dd 5.5 v v dd1 p170 to p176 3.5 v v dd1 5.5 v adcv dd p70 to p77, p80 to p83 when a/d converter not used: 3.5 v adcv dd 5.5 v when a/d converter used: 4.5 v v dd0 = adcv dd 5.5 v notes 1. the electrical specifications differ between an operating frequency of 4 to 17 mhz and an operating frequency of 4 to 20 mhz. 2. when the fcan controller is used: portv dd1 portv dd2 (due to the supply voltage conditions of the in-circuit emulator) caution the conditions for the power supplies are as follows. portv dd0 portv dd1 portv dd2 v dd0 = v dd1 = adcv dd the differences in the pins of the v850/sc1, v850/sc2, and v850/sc3 are shown below. table 2-2. differences in pins of v850/sc1, v850/sc2, and v850/sc3 v850/sc1 v850/sc2 v850/sc3 pin pd703068y pd70f3089y pd703069y pd70f3089y pd703088y pd703089y pd70f3089y v pp not available available not available available not available available a1 to a5 available not available ietx0 not available available not available ierx0 not available available not available cantx1, canrx1 not available available cantx2, canrx2 not available not available available
chapter 2 pin functions user?s manual u15109ej3v0ud 58 (1) port pins (1/4) pin name i/o pull function alternate function p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 p05 intp4/adtrg p06 intp5 p07 i/o no port 0 8-bit i/o port input/output can be specified in 1-bit units. intp6 p10 si0/sda0 p11 so0 p12 sck0/scl0 p13 si4/rxd0 p14 so4/txd0 p15 sck4/asck0 p16 ? p17 i/o no port 1 8-bit i/o port input/output can be specified in 1-bit units. only p10 and p12 can be specified as n-ch open-drain pins. ti5/to5 p20 si2/sda1 p21 so2 p22 sck2/scl1 p23 ti90 p24 ti91 p25 to9 p26 ierx0 note 1 p27 i/o no port 2 8-bit i/o port input/output can be specified in 1-bit units. only p20 and p22 can be specified as n-ch open-drain pins. ietx0 note 1 p30 ti6/to6 p31 ti80 p32 ti81 p33 to8 p34 ti71, a13 note 2 p35 intp7/a14 note 2 p36 intp8/a15 note 2 p37 i/o no port 3 8-bit i/o port input/output can be specified in 1-bit units. intp9 notes 1. only for the v850/sc2 2. only for the v850/sc1 and v850/sc2 remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u15109ej3v0ud 59 (2/4) pin name i/o pull function alternate function p40 ad0 p41 ad1 p42 ad2 p43 ad3 p44 ad4 p45 ad5 p46 ad6 p47 i/o no port 4 8-bit i/o port input/output can be specified in 1-bit units. ad7 p50 ad8 p51 ad9 p52 ad10 p53 ad11 p54 ad12 p55 ad13 p56 ad14 p57 i/o no port 5 8-bit i/o port input/output can be specified in 1-bit units. ad15 p60 a16 p61 a17 p62 a18 p63 a19 p64 a20 p65 i/o no port 6 6-bit i/o port input/output can be specified in 1-bit units. a21 p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 input no port 7 8-bit input port ani7 p80 ani8 p81 ani9 p82 ani10 p83 input no port 8 4-bit input port ani11 remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u15109ej3v0ud 60 (3/4) pin name i/o pull function alternate function p90 lben/wrl note 1 p91 uben p92 r/w/wrh note 1 p93 dstb/rd note 1 p94 astb p95 hldak p96 i/o no port 9 7-bit i/o port input/output can be specified in 1-bit units. hldrq p100 kr0/to7/a5 note 1 p101 kr1/ti70/a6 note 1 p102 kr2/ti00/a7 note 1 p103 kr3/ti01/a8 note 1 p104 kr4/to0/a9 note 1 p105 kr5/ti10/a10 note 1 p106 kr6/ti11/a11 note 1 p107 i/o yes port 10 8-bit i/o port input/output can be specified in 1-bit units. kr7/to1/a12 note 1 p110 wait/a1 note 1 p111 a2 note 1 p112 a3 note 1 p113 a4 note 1 p114 cantx1 note 2 p115 canrx1 note 2 p116 cantx2 note 3 p117 i/o no port 11 8-bit i/o port input/output can be specified in 1-bit units. canrx2 note 3 p120 sck5 p121 si5 p122 so5 p123 sck6 p124 si6 p125 so6 p126 to10 p127 i/o no port 12 8-bit i/o port input/output can be specified in 1-bit units. to11 p130 ? p131 ? p132 ? p133 i/o no port 13 4-bit i/o port input/output can be specified in 1-bit units. ? notes 1. only for the v850/sc1 and v850/sc2 2. only for the v850/sc3 3. only for the pd703089y, 70f3089y remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u15109ej3v0ud 61 (4/4) pin name i/o pull function alternate function p140 si3/rxd1 p141 so3/txd1 p142 sck3/asck1 p143 rxd2 p144 txd2 p145 asck2 p146 ti100 p147 i/o no port 14 8-bit i/o port input/output can be specified in 1-bit units. ti101 p150 rxd3 p151 txd3 p152 asck3 p153 ti110 p154 ti111 p155 to12 p156 ti120 p157 i/o yes port 15 8-bit i/o port input/output can be specified in 1-bit units. ti121 p170 ? p171 ? p172 ? p173 ? p174 ? p175 ? p176 i/o no port 17 7-bit i/o port input/output can be specified in 1-bit units. vm45 remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u15109ej3v0ud 62 (2) non-port pins (1/4) pin name i/o pull function alternate function a1 p110/wait a2 to a4 no p111 to p113 a5 p100/kr0/to7 a6 p101/kr1/ti70 a7 p102/kr2/ti00 a8 p103/kr3/ti01 a9 p104/kr4/to0 a10 p105/kr5/ti10 a11 p106/kr6/ti11 a12 yes p107/kr7/to1 a13 p34/ti71 a14 p35/intp7 a15 output no lower address bus used for external memory expansion (v850/sc1 and v850/sc2 only) p36/intp8 a16 to a21 output no higher address bus used for external memory expansion p60 to p65 ad0 to ad15 i/o no 16-bit multiplexed address/data bus used for external memory expansion p40 to p47, p50 to p57 adcgnd ? ? ground potential for a/d converter ? adcv dd ? ? power supply pin and reference voltage pin for a/d converter ? adtrg input no a/d converter external trigger input p05/intp4 ani0 to ani11 input no analog input to a/d converter p70 to p77, p80 to p83 asck0 baud rate clock input for uart0 p15/sck4 asck1 baud rate clock input for uart1 p142/sck3 asck2 baud rate clock input for uart2 p145 asck3 input no baud rate clock input for uart3 p152 astb output no external address strobe signal output p94 canrx1 can1 receive data input note 1 p115 canrx2 input can2 receive data input note 2 p117 cantx1 can1 transmit data output note 1 p114 cantx2 output no can2 transmit data output note 2 p116 clkout output ? internal system clock output ? cpureg ? ? connection of regulator output stabilization capacitance ? dstb output no external data strobe signal output p93/rd note 3 gnd0 to gnd2 ?? ground potential ? notes 1. only for the v850/sc3 2. only for the pd703089y and 70f3089y 3. only for the v850/sc1 and v850/sc2 remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u15109ej3v0ud 63 (2/4) pin name i/o pull function alternate function hldak output bus hold acknowledge output p95 hldrq input no bus hold request input p96 ierx0 input iebus data input (v850/sc2 only) p26 ietx0 output no iebus data output (v850/sc2 only) p27 intp0 to intp3 external interrupt request input (analog noise elimination) p01 to p04 intp4 p05/adtrg intp5 external interrupt request input (digital noise elimination) p06 intp6 external interrupt request input (digital noise elimination for remote control) p07 intp7 p35/a14 note 1 intp8 p36/a15 note 1 intp9 input yes external interrupt request input (analog noise elimination) p37 kr0 p100/a5 note 1 /to7 kr1 p101/a6 note 1 /ti70 kr2 p102/a7 note 1 /ti00 kr3 p103/a8 note 1 /ti01 kr4 p104/a9 note 1 /to0 kr5 p105/a10 note 1 /ti10 kr6 p106/a11 note 1 /ti11 kr7 input yes key return input p107/a12 note 1 /t01 lben output no external data bus?s lower byte enable signal output p90/wrl note 1 mode ?? specifies operation mode (other than pd78f38089y) v pp note 2 nmi input no non-maskable interrupt request input (analog noise elimination) p00 portgnd0 ? portgnd1 ?? ground potential for ports ? portv dd0 positive power supply for ports (p40 to p47, p50 to p57, p60 to p65, p90 to p96, clkout) ? portv dd1 positive power supply for ports (p00 to p03, p10 to p17, p30 to p37, p100 to p107, p110 to p117) ? portv dd2 ?? positive power supply for ports (p04 to p07, p20 to p27, p120 to p127, p130 to p133, p140 to p147, p150 to p157) ? r/w output no external read/write status output p92/wrh note 1 rd output no read strobe signal output (v850/sc1 and v850/sc2 only) p93/dstb reset input ? system reset input ? rxd0 p13/si4 rxd1 p140/si3 rxd2 p143 rxd3 input no serial receive data input for uart0, uart1, uart2, uart3 p150 sck0 p12/scl0 sck2 p22/scl1 sck3 i/o no serial clock i/o (3-wire type) for csi0, csi2, csi3 p142/asck1 notes 1. only for the v850/sc1 and v850/sc2 2. only for the pd70f3089y remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u15109ej3v0ud 64 (3/4) pin name i/o pull function alternate function sck4 serial clock i/o (3-wire type) for variable-length csi4 p15/asck0 sck5 p120 sck6 i/o no serial clock i/o (3-wire type) for csi5, csi6 p123 scl0 serial clock i/o for i 2 c0 p12/sck0 scl1 i/o no serial clock i/o for i 2 c1 p22/sck2 sda0 serial transmit/receive data input for i 2 c0 p10/si0 sda1 i/o no serial transmit/receive data input for i 2 c1 p20/si2 si0 p10/sda0 si2 p20/sda1 si3 input no serial receive data input (3-wire type) for csi0, csi2, csi3 p140/rxd1 si4 serial receive data input (3-wire type) for variable-length csi4 p13/rxd0 si5 p121 si6 input no serial receive data input (3-wire type) for csi5, csi6 p124 so0 p11 so2 p21 so3 output no serial transmit data output (3-wire type) for csi0, csi2, csi3 p141/txd1 so4 no serial transmit data output (3-wire type) for variable-length csi4 p14/txd0 so5 no p122 so6 output no serial transmit data output (3-wire type) for csi5, csi6 p125 ti00 external count clock input for tm0/ external capture trigger input for tm0 p102/a7 note /kr2 ti01 external capture trigger input for tm0 p103/a8 note /kr3 ti10 external count clock input for tm1/ external capture trigger input for tm1 p105/a10 note /kr5 ti11 yes external capture trigger input for tm1 p106/a11 note /kr6 ti100 external count clock input for tm10/ external capture trigger input for tm10 p146 ti101 no external capture trigger input for tm10 p147 ti110 external count clock input for tm11/ external capture trigger input for tm11 p153 ti111 input no external capture trigger input for tm11 p154 ti120 external count clock input for tm12/ external capture trigger input for tm12 p156 ti121 external capture trigger input for tm12 p157 ti5 p17/to5 ti6 input no external count clock input for tm5, tm6 p30/to6 note only for the v850/sc1 and v850/sc2 remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u15109ej3v0ud 65 (4/4) pin name i/o pull function alternate function ti70 yes external count clock input for tm7/ external capture trigger input for tm7 p101/a6 note 1 /kr1 ti71 external capture trigger input for tm7 p34/a13 note 1 ti80 external count clock input for tm8/ external capture trigger input for tm8 p31 ti81 no external capture trigger input for tm8 p32 ti90 external count clock input for tm9/ external capture trigger input for tm9 p23 ti91 input no external capture trigger input for tm9 p24 to0 p104/a9 note 1 /kr4 to1 yes p107/a12 note 1 /kr7 to10 p126 to11 p127 to12 p155 to5 no pulse signal output for tm0, tm1, tm10 to tm12, tm5 p17/ti5 to6 no p30/ti6 to7 yes p100/a5 note 1 /kr0 to8 p33 to9 output no pulse signal output for tm6 to tm9 p25 txd0 p14/so4 txd1 p141/so3 txd2 p144 txd3 output no serial transmit data output for uart0, uart1, uart2, uart3 p151 uben output no higher byte enable signal output for external data bus p91 v dd0 positive power supply pin (reset) ? v dd1 ?? positive power supply pin (p170 to p176) ? vm45 output no v dd0 = 4.5 v monitor output p176 v pp ?? high-voltage application pin for program write/verify ( pd70f3089y only) mode note 2 wait input no control signal input for inserting wait in bus cycle p 110/a1 note 1 wrh higher byte write strobe signal output for external data bus (v850/sc1, v850/sc2 only) p92/r/w wrl output no lower byte write strobe signal output for external data bus (v850/sc1, v850/sc2 only) p90/lben x1 input ? x2 ? ? resonator connection for main clock ? xt1 input ? xt2 ? ? resonator connection for subclock ? notes 1. only for the v850/sc1 and v850/sc2 2. other than pd70f3089y remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u15109ej3v0ud 66 2.2 pin states the operation states of pins in various operating modes are described below. table 2-3. pin operation states in various operating modes operating mode pin reset note 1 halt mode/ idle state idle mode/ stop mode bus hold bus cycle inactive note 2 ad0 to ad15 hi-z hi-z hi-z hi-z hi-z a1 to a15 hi-z held held held held note 3 a16 to a21 hi-z held hi-z hi-z held note 3 lben, uben hi-z held hi-z hi-z held note 3 r/w hi-z h hi-z hi-z h dstb, wrl, wrh, rd hi-z h hi-z hi-z h astb hi-z h hi-z hi-z h hldrq ? operating ? operating operating hldak hi-z operating hi-z l operating wait ????? clkout hi-z operating note 4 l operating note 4 operating note 4 notes 1. pins (except the clkout pin) are used as port pins (input mode) after reset. 2. the bus cycle inactivation timing occurs when the internal memory area is specified by the program counter (pc) in the external expansion mode. 3. ? when the external memory area has not been accessed even once after reset is released and the external expansion mode is set: undefined ? when the bus cycle is inactivated after access to the external memory area, or when the external memory area has not been accessed even once after the external expansion mode is released and set again: the state of the external bus cycle when the external memory area accessed last is held. 4. low level (l) when in clock output inhibit mode remark hi-z: high impedance held: state during previously set external bus cycle is held l: low-level output h: high-level output ? : input without sampling
chapter 2 pin functions user?s manual u15109ej3v0ud 67 2.3 description of pin functions (1) p00 to p07 (port 0) 3-state i/o p00 to p07 function as an 8-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as an nmi input, external interrupt request inputs, and the external trigger for the a/d converter. the pin?s valid edge is specified by the egp0 and egn0 registers. (a) port function p00 to p07 can be set to input or output in 1-bit units using the port 0 mode register (pm0). (b) alternate functions (i) nmi (non-maskable interrupt request) input this is a non-maskable interrupt request signal input pin. (ii) intp0 to intp6 (interrupt request from peripherals) input these are external interrupt request input pins. (iii) adtrg (a/d trigger input) input this is the a/d converter?s external trigger input pin. this pin is controlled by a/d converter mode register 1 (adm1).
chapter 2 pin functions user?s manual u15109ej3v0ud 68 (2) p10 to p17 (port 1) 3-state i/o p10 to p17 function as an 8-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as i/o pins for the serial interface and timer/counter. p10 and p12 can be selected as normal output or n-ch open-drain output pins. (a) port function p10 to p17 can be set to input or output in 1-bit units using the port 1 mode register (pm1). (b) alternate functions (i) si0, si4 (serial input 0, 4) input these are the serial receive data input pins for csi0 and csi4. (ii) so0, so4 (serial output 0, 4) output these are the serial transmit data output pins for csi0 and csi4. (iii) sck0, sck4 (serial clock 0, 4) 3-state i/o these are the serial clock i/o pins for csi0 and csi4. (iv) sda0 (serial data 0) i/o this is the serial transmit/receive data i/o pin for i 2 c0. (v) scl0 (serial clock 0) i/o this is the serial clock i/o pin for i 2 c0. (vi) rxd0 (receive data 0) input this is the serial receive data input pin for uart0. (vii) txd0 (transmit data 0) output this is the serial transmit data output pin for uart0. (viii) asck0 (asynchronous serial clock 0) input this is the serial baud rate clock input pin for uart0. (ix) ti5 (timer input 5) input this is the external count clock input pin for timer 5. (x) to5 (timer output 5) output this is the pulse signal output pin for timer 5.
chapter 2 pin functions user?s manual u15109ej3v0ud 69 (3) p20 to p27 (port 2) 3-state i/o p20 to p27 function as an 8-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as i/o pins for the serial interface, timer/counter, and iebus data. (a) port function p20 to p27 can be set to input or output in 1-bit units using the port 2 mode register (pm2). (b) alternate functions (i) si2 (serial input 2) input this is the serial receive data input pin for csi2. (ii) so2 (serial output 2) output this is the serial transmit data output pin for csi2. (iii) sck2 (serial clock 2) 3-state i/o this is the serial clock i/o pin for csi2. (iv) sda1 (serial data 1) ... input this is the serial transmit/receive data i/o pin for i 2 c1. (v) scl1 (serial clock 1) ... i/o this is the serial clock i/o pin for i 2 c1. (vi) ti90 (timer input 90) ... input this is the external count clock input and external capture trigger input pin for timer 9. (vii) ti91 (timer input 91) ... input this is the external capture trigger input pin for timer 9. (viii) to9 (timer output 9) ... output this is the pulse signal output pin for timer 9. (ix) ierx0 (iebus receive data) ... input this is the iebus data input signal. ierx0 is available only for the v850/sc2. (x) ietx0 (iebus transmit data) ... output this is the iebus data output signal. ietx0 is available only for the v850/sc2.
chapter 2 pin functions user?s manual u15109ej3v0ud 70 (4) p30 to p37 (port 3) 3-state i/o p30 to p37 function as an 8-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as i/o pins for the timer/counter, an address bus (a13 to a15) for external memory expansion, and external interrupt request inputs. (a) port function p30 to p37 can be set to input or output in 1-bit units using the port 3 mode register (pm3). (b) alternate functions (i) ti6 (timer input 6) input this is the external count clock input pin for timer 6. (ii) ti71 (timer input 71) input this is the external capture trigger input pin for timer 7. (iii) ti80 (timer input 80) input this is the external count clock input and external capture trigger input pin for timer 8. (iv) ti81 (timer input 81) input this is the external capture trigger input pin for timer 8. (v) to6, to8 (timer output 6, 8) output these are the pulse signal output pins for timer 6 and timer 8. (vi) a13 to a15 (address 13 to 15) output these pins comprise an address bus for external access and operate as the a13 to a15 (22-bit address) output pins. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle to inactive, these pins hold the address of the bus cycle immediately before. a13 to a15 are available only for the v850/sc1 and v850/sc2. (vii) intp7 to intp9 (interrupt request from peripherals) input these are external interrupt request input pins.
chapter 2 pin functions user?s manual u15109ej3v0ud 71 (5) p40 to p47 (port 4) 3-state i/o p40 to p47 function as an 8-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as a time division address/data bus (ad0 to ad7) when memory is expanded externally. (a) port function p40 to p47 can be set to input or output in 1-bit units using the port 4 mode register (pm4). (b) alternate function (external expansion mode) p40 to p47 can be specified as ad0 to ad7 using the memory expansion mode register (mm). (i) ad0 to ad7 (address/data 0 to 7) 3-state i/o these pins comprise a multiplexed address/data bus for external access. at the address timing (t1 state), these pins operate as the ad0 to ad7 (22-bit address) output pins. at the data timing (t2, tw, t3), they operate as lower 8-bit i/o bus pins for 16-bit data. the output changes in synchronization with the rising edge of the clock in each state in the bus cycle. when the timing sets the bus cycle to inactive, these pins go into a high-impedance state. (6) p50 to p57 (port 5) 3-state i/o p50 top57 function as an 8-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as a time division address/data bus (ad8 to ad15) when memory is expanded externally. (a) port function p50 to p57 can be set to input or output in 1-bit units using the port 5 mode register (pm5). (b) alternate function (external expansion mode) p50 to p57 can be specified as ad8 to ad15 using the memory expansion mode register (mm). (i) ad8 to ad15 (address/data 8 to 15) 3-state i/o these pins comprise a multiplexed address/data bus for external access. at the address timing (t1 state), these pins operate as the ad8 to ad15 (22-bit address) output pins. at the data timing (t2, tw, t3), they operate as higher 8-bit i/o bus pins for 16-bit data. the output changes in synchronization with the rising edge of the clock in each state of the bus cycle. when the timing sets the bus cycle to inactive, these pins go into a high-impedance state.
chapter 2 pin functions user?s manual u15109ej3v0ud 72 (7) p60 to p65 (port 6) 3-state i/o p60 to p65 function as a 6-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as an address bus (a16 to a21) when memory is expanded externally. during 8-bit access of port 6, the higher two bits are ignored during a write operation and are read as ?00? during a read operation. (a) port function p60 to p65 can be set to input or output in 1-bit units using the port 6 mode register (pm6). (b) alternate function (external expansion mode) p60 to p65 can be specified as a16 to a21 using the memory expansion mode register (mm). (i) a16 to a21 (address 16 to 21) output these pins comprise an address bus for external access. these pins operate as the higher 6-bit address output pins within a 22-bit address. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle to inactive, these pins hold the address of the bus cycle immediately before. (8) p70 to p77 (port 7), p80 to p83 (port 8) input p70 to p77 function as an 8-bit input-only port in which all pins are fixed as input pins. p80 to p83 function as a 4-bit input-only port in which all pins are fixed as input pins. in addition to input ports, these pins can also be used as analog input pins of the a/d converter for the alternate function. however, they cannot be switched between input ports and analog input pins. (a) port function p70 to p77 and p80 to p83 are input-only pins. (b) alternate function p70 to p77 also function as pins ani0 to ani7 and p80 to p83 also function as ani8 to ani11, but these alternate functions are not switchable. (i) ani0 to ani11 (analog input 0 to 11) input these are analog input pins for the a/d converter. connect a capacitor between adcv dd and adcgnd to prevent noise-related operation faults. also, do not apply voltage that is outside the range for adcv dd and adcgnd to pins that are being used as inputs for the a/d converter. if it is possible for noise above the adcv dd range or below the adcgnd range to enter, clamp these pins using a diode that has a small v f value.
chapter 2 pin functions user?s manual u15109ej3v0ud 73 (9) p90 to p96 (port 9) 3-state i/o p90 to p96 function as a 7-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as control signal output pins, and bus hold control signal output pins when memory is expanded externally. during 8-bit access of port 9, the highest bit is ignored during a write operation and is read as ?0? during a read operation. (a) port function p90 to p96 can be set to input or output in 1-bit units using the port 9 mode register (pm9). (b) alternate function (external expansion mode) p90 to p96 can be specified as control signal outputs for external memory expansion using the memory expansion mode register (mm). (i) lben (lower byte enable) output this is the lower byte enable signal output pin for the external 16-bit data bus. during byte access to the odd-numbered addresses, these pins are set to inactive (high level). the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle to inactive, this pin holds the address of the bus cycle immediately before. (ii) uben (upper byte enable) output this is the upper byte enable signal output pin for the external 16-bit data bus. during byte access of even-numbered addresses, these pins are set to inactive (high level). the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle to inactive, this pin holds the address of the bus cycle immediately before. access uben lben ad0 word access 0 0 0 halfword access 0 0 0 even-numbered address 1 0 0 byte access odd-numbered address 0 1 1 (iii) r/w (read/write status) output this is the output pin for the status signal that indicates whether the bus cycle is a read cycle or a write cycle during external access. high level is set during the read cycle and low level is set during the write cycle. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. high level is set when the timing sets the bus cycle to inactive. (iv) dstb (data strobe) output this is the output pin for the access strobe signal for the external data bus. output becomes active (low level) during the t2 and tw states of the bus cycle. output becomes inactive (high level) when the timing sets the bus cycle to inactive. (v) astb (address strobe) output this is the output pin for the latch strobe signal for the external address bus. output becomes active (low level) in synchronization with the falling edge of the clock during the t1 state of the bus cycle, and becomes inactive (high level) in synchronization with the falling edge of the clock during the t3 state of the bus cycle. output becomes inactive when the timing sets the bus cycle to inactive.
chapter 2 pin functions user?s manual u15109ej3v0ud 74 (vi) hldak (hold acknowledge) output this is the output pin for the acknowledge signal that indicates the high impedance status for the address bus, data bus, and control bus when the v850/sc1, v850/sc2, and v850/sc3 receive a bus hold request. the address bus, data bus, and control bus are set to high impedance when this signal is active. (vii) hldrq (hold request) input this is the input pin by which an external device requests the v850/sc1, v850/sc2, and v850/sc3 to release the address bus, data bus, and control bus. this pin accepts asynchronous input for clkout. when this pin is active, the address bus, data bus, and control bus are set to high impedance. this occurs either when the v850/sc1, v850/sc2, and v850/sc3 complete execution of the current bus cycle, or immediately if no bus cycle is being executed. the hldak signal is then set to active and the bus is released. (viii) wrl (write strobe low-level data) output this is the write strobe signal output pin for the lower data of the external 16-bit data bus. this is output in the same write cycle as dstb. wrl is available only for the v850/sc1 and v850/sc2. (ix) wrh (write strobe high-level data) output this is the write strobe signal output pin for the higher data of the external 16-bit data bus. this is output in the same write cycle as dstb. wrh is available only for the v850/sc1 and v850/sc2. (x) rd (read) output this is the read strobe signal output pin for the external 16-bit data bus. this is output in the same read cycle as dstb. rd is available only for the v850/sc1 and v850/sc2.
chapter 2 pin functions user?s manual u15109ej3v0ud 75 (10) p100 to p107 (port 10) 3-state i/o p100 to p107 function as an 8-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as timer/counter i/o pins, key return inputs, and an address bus (a5 to a12) for external memory expansion. (a) port function p100 to p107 can be set to input or output in 1-bit units using the port 10 mode register (pm10). (b) alternate functions (i) kr0 to kr7 (key return 0 to 7) ... input these are key interrupt input pins. their operations are specified by the key return mode register (krm). (ii) ti00, ti10, ti70 (timer input 00, 10, 70) ... input these are external count clock input and external capture trigger input pins for timers 0, 1, and 7. (iii) ti01, ti11 (timer input 01, 11) ... input these are external capture trigger input pins for timers 0 and 1. (iv) to0, to1, to7 (timer output 0, 1, 7) ... output these are pulse signal output pins for timers 0, 1, and 7. (v) a5 to a12 (address 5 to 12) ... output these pins comprise an address bus for external access and operate as the a5 to a12 (22-bit address) output pins. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle to inactive, these pins hold the address of the bus cycle immediately before. a5 to a12 are available only for the v850/sc1 and v850/sc2.
chapter 2 pin functions user?s manual u15109ej3v0ud 76 (11) p110 to p117 (port 11) 3-state i/o p110 to p117 function as an 8-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as fcan data i/o pins, the control signal (wait) that inserts waits into the bus cycle and an address data bus (a1 to a4) for external memory expansion. (a) port function p110 to p117 can be set to input or output in 1-bit units using the port 11 mode register (pm11). (b) alternate functions (i) wait (wait) input this is the input pin for the control signal used to insert waits into the bus cycle. this pin is sampled at the falling edge of the clock during the t2 or tw state of the bus cycle. on/off switching of the wait function is performed by the port alternate-function control register (pac). (ii) canrx1, canrx2 (can receive data 1, 2) input these are data input signals for can1 and can2. canrx1 is available only for the v850/sc3. canrx2 is available only for the pd703089y and 70f3089y. (iii) cantx1, cantx2 (can transmit data 1, 2) output these are data output signals for can1 and can2. cantx1 is available only for the v850/sc3. cantx2 is available only for the pd703089y and 70f3089y. (iv) a1 to a4 (address 1 to 4) these pins comprise an address bus for external access and operate as the a1 to a4 (22-bit address) output pins. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets bus cycle to inactive, these pins hold the address of the bus cycle immediately before. a1 to a4 are available only for the v850/sc1 and v850/sc2.
chapter 2 pin functions user?s manual u15109ej3v0ud 77 (12) p120 to p127 (port 12) 3-state i/o p120 to p127 function as an 8-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as i/o pins for the serial interface, and outputs for the timer/counter. (a) port function p120 to p127 can be set to input or output in 1-bit units using the port 12 mode register (pm12). (b) alternate functions (i) si5, si6 (serial input 5, 6) input these are the serial receive data input pins for csi5 and csi6. (ii) so5, so6 (serial output 5, 6) output these are the serial transmit data output pins for csi5 and csi6. (iii) sck5, sck6 (serial clock 5, 6) 3-state i/o these are the serial clock i/o pins for csi5 and csi6. (iv) to10, to11 (timer output 10, 11) output these are the pulse signal output pins for timers 10 and 11. (13) p130 to p133 (port 13) 3-state i/o p130 to p133 function as a 4-bit i/o port in which input and output can be specified in 1-bit units. these pins can only be used as i/o port pins.
chapter 2 pin functions user?s manual u15109ej3v0ud 78 (14) p140 to p147 (port 14) 3-state i/o p140 to p147 function as an 8-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as i/o pins for the serial interface, and inputs for the timer/counter. (a) port function p140 to p147 can be set to input or output in 1-bit units using the port 14 mode register (pm14). (b) alternate functions (i) si3 (serial input 3) input this is the serial receive data input pin for csi3. (ii) so3 (serial output 3) output this is the serial transmit data output pin for csi3. (iii) sck3 (serial clock 3) 3-state i/o this is the serial clock i/o pin for csi3. (iv) rxd1 (receive data 1) input this is the serial receive data input pin for uart1. (v) txd1 (transmit data 1) output this is the serial transmit data output pin for uart1. (vi) asck1 (asynchronous serial clock 1) ... input this is the serial baud rate clock input pin for uart1. (vii) ti100 (timer input 100) input this is the external count clock input and external capture trigger input pin for timer 10. (viii) ti101 (timer input 101) input this is the external capture trigger input pin for timer 10.
chapter 2 pin functions user?s manual u15109ej3v0ud 79 (15) p150 to p157 (port 15) 3-state i/o p150 to p157 function as an 8-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as i/o pins for the serial interface and the timer/counter. (a) port function p150 to p157 can be set to input or output in 1-bit units using the port 15 mode register (pm15). (b) alternate functions (i) rxd3 (receive data 3) ... input this is the serial receive data input pin for uart3. (ii) txd3 (transmit data 3) ... output this is the serial transmit data output pin for uart3. (iii) asck3 (asynchronous serial clock 3) ... input this is the serial baud rate clock input pin for uart3. (iv) ti110 (timer input 110) ... input this is the external count clock input and external capture trigger input pin for timer 11. (v) ti111 (timer input 111) ... input this is the external capture trigger input pin for timer 11. (vi) ti120 (timer input 120) ... input this is the external count clock input and external capture trigger input pin for timer 12. (vii) ti121 (timer input 121) ... input this is the external capture trigger input pin for timer 12. (viii) to12 (timer output 12) ... output this is the pulse signal output pin for timer 12.
chapter 2 pin functions user?s manual u15109ej3v0ud 80 (16) p170 to p176 (port 17) 3-state i/o p170 to p176 function as a 7-bit i/o port in which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as v dd0 = 4.5 v monitor output. during 8-bit access of port 17, the highest bit is ignored during a write operation and is read as ?0? during a read operation. (a) port function p170 to p176 can be set to input or output in 1-bit units using the port 17 mode register (pm17). (b) alternate function (i) vm45 (v dd0 = = = = 4.5 v monitor output) ? output this is the v dd0 = 4.5 v monitor output pin. (17) reset (reset) input reset is a signal that is input asynchronously and has a constant low level width regardless of the status of the operating clock. when this signal is input, a system reset is executed as the first priority ahead of all other operations. in addition to being used for ordinary initialization/start operations, this signal can also be used to cancel a standby mode (halt, idle, or stop mode). (18) mode (mode) this is pin used in other than the pd78f3089. connect to gnd0 to gnd2 in normal operating mode. (19) clkout (clock output) output this pin outputs internally generated bus clocks. (20) x1, x2 (crystal) these pins are used to connect the resonator that generates the main clock. (21) xt1, xt2 (crystal for sub-clock) these pins are used to connect the resonator that generates the subclock. (22) adcv dd (power supply for analog) this is the analog power supply pin for the a/d converter and alternate-function ports. this pin also functions as a reference voltage pin for the a/d converter. (23) adcgnd (ground for analog) this is the ground pin for the a/d converter and alternate-function ports. (24) cpureg (regulator control) this is the regulator pin for the cpu power supply. connect this pin to gnd0 to gnd2 via a capacitor of 1 f (recommended value).
chapter 2 pin functions user?s manual u15109ej3v0ud 81 (25) portv dd0 to portv dd2 (power supply for port) these are positive power supply pins for i/o ports and alternate-function pins. (26) portgnd0, portgnd1 (ground for port) these are ground pins for i/o ports and alternate-function pins (except for the alternate-function ports of the bus interface). (27) v dd0 , v dd1 (power supply) these are positive power supply pins. v dd0 and v dd1 pins should be connected to a positive power source. (28) gnd0 to gnd2 (ground) these are ground pins. all the gnd0 to gnd2 pins should be grounded. (29) v pp (programming power supply) this is the positive power supply pin used for flash memory programming mode. this pin is used in the pd70f3089y. connect to either gnd0, gnd1, or gnd2 in normal operating mode.
chapter 2 pin functions user?s manual u15109ej3v0ud 82 2.4 pin i/o circuit types, i/o buffer power supply and connection of unused pins (1/3) pin alternate function i/o circuit type i/o buffer power supply recommended connection p00 nmi p01 to p03 intp0 to intp2 portv dd1 input: independently connect to portv dd1 , portgnd0, or portgnd1 via a resistor. output: leave open. p04 intp3 p05 intp4/adtrg p06, p07 intp5, intp6 8 portv dd2 input: independently connect to portv dd2 , portgnd0, or portgnd1 via a resistor. output: leave open. p10 si0/sda0 10 p11 so0 5 p12 sck0/scl0 10 p13 si4/rxd0 8 p14 so4/txd0 5 p15 sck4/asck0 8 p16 ? 5 p17 ti5/to5 8 portv dd1 input: independently connect to portv dd1 , portgnd0, or portgnd1 via a resistor. output: leave open. p20 si2/sda1 10 p21 so2 5 p22 sck2/scl1 10 p23, p24 ti90, ti91 8 p25 to9 5 p26 ierx0 note 1 8 p27 ietx0 note 1 5 portv dd2 input: independently connect to portv dd2 , portgnd0, or portgnd1 via a resistor. output: leave open. p30 ti6/to6 p31, p32 ti80, ti81 8 p33 to8 5 p34 ti71/a13 note 2 p35, p36 intp7/a14 note 2 , intp8/a15 note 2 p37 intp9 8 portv dd1 input: independently connect to portv dd1 , portgnd0, or portgnd1 via a resistor. output: leave open. p40 to p47 ad0 to ad7 portv dd0 p50 to p57 ad8 to ad15 portv dd0 p60 to p65 a16 to a21 5 portv dd0 input: independently connect to portv dd0 , portgnd0, or portgnd1 via a resistor. output: leave open. notes 1. only for the v850/sc2 2. only for the v850/sc1 and v850/sc2
chapter 2 pin functions user?s manual u15109ej3v0ud 83 (2/3) pin alternate function i/o circuit type i/o buffer power supply recommended connection p70 to p77 ani0 to ani7 9 adcv dd p80 to p83 ani8 to ani11 9 adcv dd independently connect to adcv dd or adcgnd via a resistor. p90 lben/wrl note 1 p91 uben p92 r/w/wrh note 1 p93 dstb/rd note 1 p94 astb p95 hldak p96 hldrq 5portv dd0 input: independently connect to portv dd0 , portgnd0, or portgnd1 via a resistor. output: leave open. p100 kr0/to7/a5 note 1 p101 kr1/ti70/a6 note 1 p102 kr2/ti00/a7 note 1 p103 kr3/ti01/a8 note 1 p104 kr4/to0/a9 note 1 p105 kr5/ti10/a10 note 1 p106 kr6/ti11/a11 note 1 p107 kr7/to1/a12 note 1 8-a portv dd1 input: independently connect to portv dd1 , portgnd0 or portgnd1 via a resistor. when connecting to portgnd0 or portgnd1, disconnect on-chip pull-up resistors by software. output: leave open. p110 wait/a1 note 1 p111 to p113 a2 to a4 note 1 p114 cantx1 note 2 5 p115 canrx1 note 2 8 p116 cantx2 note 3 5 p117 canrx2 note 3 8 portv dd1 input: independently connect to portv dd1 , portgnd0, or portgnd1 via a resistor. output: leave open. p120 sck5 p121 si5 8 p122 so5 5 p123 sck6 p124 si6 8 p125 so6 p126, p127 to10, to11 5 portv dd2 input: independently connect to portv dd2 , portgnd0, or portgnd1 via a resistor. output: leave open. p130 to p133 ? 5portv dd2 input: independently connect to portv dd2 , portgnd0, or portgnd1 via a resistor. output: leave open. notes 1. only for the v850/sc1 and v850/sc2 2. only for the v850/sc3 3. only for the pd703089y and 70f3089y
chapter 2 pin functions user?s manual u15109ej3v0ud 84 (3/3) pin alternate function i/o circuit type i/o buffer power supply recommended connection p140 si3/rxd1 8 p141 so3/txd1 5 p142 sck3/asck1 p143 rxd2 8 p144 txd2 5 p145 asck2 p146, p147 ti100, ti101 8 portv dd2 input: independently connect to portv dd2 , portgnd0, or portgnd1 via a resistor. output: leave open. p150 rxd3 8 p151 txd3 5 p152 asck3 p153, p154 ti110, ti111 8 p155 to12 5 p156, p157 ti120, ti121 8 porv dd2 input: independently connect to portv dd2 , portgnd0, or portgnd1 via a resistor. output: leave open. p170 to p175 ? p176 vm45 5v dd1 input: independently connect to v dd1 , portgnd0, or portgnd1 via a resistor. output: leave open. clkout ? 4portv dd0 leave open. reset ? 2v dd0 ? x1, x2 ?? ? xt1, xt2 ?? cpureg ? cpureg ??? ? v pp note 1 mode ? v dd0 connect to either gnd0, gnd1, or gnd2. mode note 2 v pp ? v dd0 connect to either gnd0, gnd1, or gnd2. v dd0 , v dd1 ??? ? gnd0 to gnd2 ??? ? adcv dd ??? ? adcgnd ??? ? portv dd0 to portv dd2 ??? ? portgnd0, portgnd1 ??? ? notes 1. pd70f3089y 2. other than pd70f3089y
chapter 2 pin functions user?s manual u15109ej3v0ud 85 2.5 pin i/o circuits type 2 in schmitt-triggered input with hysteresis characteristics type 8-a pullup enable in/out data output disable n-ch p-ch p-ch v dd v dd type 4 out output disable n-ch data p-ch v dd push-pull output that can be set for high impedance output (both p-ch and n-ch off). type 9 + ? n-ch p-ch input enable v ref (threshold voltage) comparator type 5 output disable input enable in/out data n-ch p-ch v dd type 10 in/out data open drain output disable n-ch p-ch v dd type 8 in/out data output disable n-ch p-ch v dd
user?s manual u15109ej3v0ud 86 chapter 3 cpu functions the cpu of the v850/sc1, v850/sc2, and v850/sc3 is based on risc architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 features ? minimum instruction execution time: v850/sc1: 50 ns (@ 20 mhz internal operation) v850/sc2: 53 ns (@ 18.87 mhz internal operation) v850/sc3: 62.5 ns (@ 16 mhz internal operation) ? address space: 16 mb linear ? general-purpose registers: 32 bits 32 ? internal 32-bit architecture ? five-stage pipeline control ? multiplication/division instructions ? saturated operation instructions ? one-clock 32-bit shift instruction ? load/store instructions with long/short format ? four types of bit manipulation instructions set1 clr1 not1 tst1
chapter 3 cpu functions user?s manual u15109ej3v0ud 87 3.2 cpu register set the cpu registers of the v850/sc1, v850/sc2, and v850/sc3 can be classified into two categories: a general- purpose program register set and a dedicated system register set. all the registers have a 32-bit width. for details, refer to v850 series architecture user?s manual . figure 3-1. cpu register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 zero register reserved for address register stack pointer (sp) global pointer (gp) text pointer (tp) element pointer (ep) link pointer (lp) pc program counter psw program status word ecr exception cause register fepc fepsw fatal error pc fatal error psw eipc eipsw exception/interrupt pc exception/interrupt psw 31 0 31 0 31 0 31 0 31 0 31 0 system register set program register set
chapter 3 cpu functions user ? s manual u15109ej3v0ud 88 3.2.1 program register set the program register set includes general-purpose registers and a program counter. (1) general-purpose registers thirty-two general-purpose registers, r0 to r31, are available. any of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers. also, r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. therefore, before using these registers, their contents must be saved so that they are not lost. the contents must be restored to the registers after the registers have been used. r2 is sometimes used by a real-time os. r2 can be used as a variable register when the real-time os that is used does not use r2. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register working register for generating 32-bit immediate r2 address/data variable register (when r2 is not used by the real-time os being used) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to access global variable in data area r5 text pointer register to indicate the start of the text area note r6 to r29 address/data variable registers r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling functions pc program counter holds instruction address during program execution note area in which program code is mapped. (2) program counter (pc) this register holds the address of the instruction under execution. the lower 24 bits of this register are valid, and bits 31 to 24 are fixed to 0. if a carry occurs from bit 23 to 24, it is ignored. bit 0 is fixed to 0, and branching to an odd address is not possible. after reset: 00000000h symbol 31 24 23 1 0 pc fixed to 0 address of instruction under execution 0
chapter 3 cpu functions user ? s manual u15109ej3v0ud 89 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. table 3-2. system register numbers no. system register name usage operation 0eipc 1 eipsw interrupt status saving registers these registers save the pc and psw when an exception or interrupt occurs. because only one set of these registers is available, their contents must be saved when multiple interrupts are enabled. 2 fepc 3 fepsw nmi status saving registers these registers save the pc and psw when an nmi occurs. 4 ecr interrupt source register if an exception, maskable interrupt, or nmi occurs, this register will hold the information referencing the interrupt source. the higher 16 bits of this register are called fecc, to which the exception code of the nmi is set. the lower 16 bits are called eicc, to which the exception code of the exception/interrupt is set. 5 psw program status word the program status word is a collection of flags that indicate the program status (instruction execution result) and cpu status. 6 to 31 reserved to read/write these system registers, specify the system register number indicated by the system register load/store instruction (ldsr or stsr instruction). (1) interrupt source register (ecr) after reset: 00000000h symbol 31 16 15 0 ecr fecc eicc fecc exception code of nmi (for the exception code, refer to table 7-1 .) eicc exception code of exception/interrupt
chapter 3 cpu functions user ? s manual u15109ej3v0ud 90 (2) program status word (psw) (1/2) after reset: 00000020h 31 876543210 psw rfu np ep id sat cy ov s z rfu reserved field (fixed to 0). np non-maskable interrupt (nmi) servicing status 0 nmi servicing not under execution. 1 nmi servicing under execution. this flag is set (1) when an nmi is acknowledged, and disables multiple interrupts. for details, refer to 7.2.3 np flag. ep exception processing status 0 exception processing not under execution. 1 exception processing under execution. this flag is set (1) when an exception is generated. interrupt requests can be acknowledged when this bit is set. for details, refer to 7.4.3 ep flag. id maskable interrupt servicing specification 0 maskable interrupt acknowledgement enabled. 1 maskable interrupt acknowledgement disabled. this flag is set (1) when a maskable interrupt request is acknowledged. for details, refer to 7.3.6 id flag. sat note saturation detection of operation result of saturation operation instruction 0 not saturated. this flag is not cleared (0) if the result of saturated operation instruction execution is not saturated while this flag is set (1). to clear (0) this flag, write the psw directly. 1 saturated. cy detection of carry or borrow of operation result 0 overflow has not occurred. 1 overflow occurred. ov note detection of overflow during operation 0 overflow has not occurred. 1 overflow occurred. s note detection of operation result positive/negative 0 the operation result was positive or 0. 1 the operation result was negative.
chapter 3 cpu functions user ? s manual u15109ej3v0ud 91 (2/2) z detection of operation result zero 0 the operation result was not 0. 1 the operation result was 0. note the result of a saturation-processed operation is determined by the contents of the ov and s bits in the saturation operation. simply setting (1) the ov bit will set (1) the sat bit in a saturation operation. flag status status of operation result sat ov s saturation-processed operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (not exceeding the maximum) 0 negative (not exceeding the maximum) retains the value before operation 0 1 operation result itself
chapter 3 cpu functions user ? s manual u15109ej3v0ud 92 3.3 operating modes the v850/sc1, v850/sc2, and v850/sc3 have the following operating modes. (1) normal operating mode (single-chip mode) after the system has been released from the reset state, the pins related to the bus interface are set to port mode, execution branches to the reset entry address of the internal rom, and the instruction processing written in the internal rom is started. external expansion mode can be entered by setting the memory ex pansion mode register (mm) via an instruction, enabling an external device to be connected to the external memory area. (2) flash memory programming mode this mode is provided only in the pd70f3089y. the internal flash memory can be programmed or erased when the v pp voltage is applied to the v pp pin. v pp operating mode 0 normal operating mode 7.8 v flash memory programming mode v dd setting prohibited
chapter 3 cpu functions user ? s manual u15109ej3v0ud 93 3.4 address space 3.4.1 cpu address space the cpu of the v850/sc1, v850/sc2, and v850/sc3 has 32-bit architecture and supports up to 4 gb of linear address space (data space) during operand addressing (data access). when referencing instruction addresses, a linear address space (program space) of up to 16 mb is supported. the cpu address space is shown below. figure 3-2. cpu address space ffffffffh cpu address space program area (16 mb linear) data area (4 gb linear) 01000000h 00ffffffh 00000000h
chapter 3 cpu functions user ? s manual u15109ej3v0ud 94 3.4.2 imaging the 4 gb cpu address space can be viewed as 256 images of a 16 mb physical address space. in other words, the same 16 mb block is accessed regardless of the values of bits 31 to 24 of the cpu address. the address space imaging is shown below. because the higher 8 bits of a 32-bit cpu address are ignored and the cpu address is only seen as a 24-bit external physical address, the physical location xx000000h is equally referenced by multiple address values 00000000h, 01000000h, 02000000h, ... fe000000h, ff000000h. figure 3-3. address space imaging ffffffffh ff000000h feffffffh image cpu address space image image image image fe000000h fdffffffh 02000000h 01ffffffh 01000000h 00ffffffh 00000000h physical address space on-chip peripheral i/o internal ram (access prohibited) internal rom xxffffffh xx000000h
chapter 3 cpu functions user ? s manual u15109ej3v0ud 95 3.4.3 wrap-around of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. even if a carry or borrow occurs from bit 23 to 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain 0. therefore, the lower-limit address of the program space, address 00000000h, and the upper-limit address 00ffffffh are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. caution no instruction can be fetched from the 4 kb area of 00fff000h to 00ffffffh because this area is defined as peripheral i/o area. therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area. figure 3-4. program space 00fffffeh 00ffffffh 00000000h 00000001h program space program space (+) direction ( ? ) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit address of the program space, address 00000000h, and the upper-limit address ffffffffh are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. figure 3-5. data space fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction ( ? ) direction
chapter 3 cpu functions user ? s manual u15109ej3v0ud 96 3.4.4 memory map the v850/sc1, v850/sc2, and v850/sc3 reserve areas as shown below. figure 3-6. memory map xxffffffh on-chip peripheral i/o area internal ram area fcan address area internal flash memory/ rom area on-chip peripheral i/o area internal ram area fcan address area external memory area internal flash memory/ rom area single-chip mode single-chip mode (external expansion mode) 16 mb 1 mb 4 kb xxfff000h xxffefffh xx100000h xx0fffffh xx000000h xxff8000h xxff7fffh 28 kb
chapter 3 cpu functions user ? s manual u15109ej3v0ud 97 3.4.5 area (1) internal rom/flash memory area an area of 1 mb maximum is reserved for the internal rom/flash memory area. 512 kb are available for the addresses xx000000h to xx07ffffh. addresses xx080000h to xx0fffffh are an access-prohibited area figure 3-7. internal rom/flash memory area x x 0 f f f f f h x x 0 8 0 0 0 0 h x x 0 7 f f f f h x x 0 0 0 0 0 0 h access-prohibited area internal rom/ flash memory
chapter 3 cpu functions user ? s manual u15109ej3v0ud 98 interrupt/exception table the v850/sc1, v850/sc2, and v850/sc3 increase the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. the collection of these handler addresses is called an interrupt/exception table, which is located in the internal rom area. when an interrupt/exception request is granted, execution jumps to the handler address, and the program written at that memory address is executed. the sources of interrupts/exceptions, and the corresponding addresses are shown below. table 3-3. interrupt/exception table start address of interrupt/exception table interrupt/exception source start address of interrupt/exception table interrupt/exception source 00000000h reset 00000210h intsr0/intcsi4 00000010h nmi 00000220h intst0 00000020h intwdt 00000230h intkr 00000040h trap0n (n = 0 to f) 00000240h intce1 note 2 /intie1 note 3 00000050h trap1n (n = 0 to f) 00000250h intcr1 note 2 /intie2 note 3 00000060h ilgop 00000260h intct1 note 2 00000080h intwdtm 00000270h intcme note 2 00000090h intp0 00000280h inttm80 000000a0h intp1 00000290h inttm81 000000b0h intp2 000002a0h inttm90 000000c0h intp3 000002b0h inttm91 000000d0h intp4 000002c0h intsr1/intcsi3 000000e0h intp5 000002d0h intst1 000000f0h intp6 000002e0h intdma3 00000100h intcsi5 000002f0h intdma4 00000110h intad 00000300h intdma5 00000120h intdma0 00000310h intce2 note 4 00000130h intdma1 00000320h intcr2 note 4 00000140h intdma2 00000330h intct2 note 4 00000150h inttm00 00000340h intp7 00000160h inttm01 00000350h intsr2 00000170h inttm10 00000360h intst2 00000180h inttm11 00000370h intsr3 00000190h inttm70 00000380h intst3 000001a0h inttm71 00000390h inttm100 000001b0h intcsi6 000003a0h inttm101 000001c0h inttm5/intp8 note 1 000003b0h inttm110 000001d0h intwtn 000003c0h inttm111 000001e0h intwtni 000003d0h inttm120 000001f0h intiic0/intcsi0 000003e0h inttm121 00000200h inttm6/intp9 note 1 000003f0h intiic1/intcsi2 notes 1. when using intp8 or intp9, stop tm5 and tm6 (tcem0 bit of tmcm0 register = 0) and do not use them. when using tm5 or tm6, do not specify edges for intp8 and intp9 (egp1n bit of egp1 register = 0 and egn1n bit of egn1 register = 0) and do not use them as external interrupts (they can be used as ports) (n = 6, 7). 2. only for the v850/sc3 3. only for the v850/sc2 4. only for the pd703089y and 70f3089y
chapter 3 cpu functions user ? s manual u15109ej3v0ud 99 (2) internal ram area an area of 28 kb maximum is reserved for the internal ram area. 24 kb are available for the addresses xxff9000h to xxffefffh. addresses xxff8000h to xxff8fffh are an access-prohibited area figure 3-8. internal ram area x x f f e f f f h x x f f 9 0 0 0 h x x f f 8 f f f h x x f f 8 0 0 0 h access-prohibited area internal ram
chapter 3 cpu functions user ? s manual u15109ej3v0ud 100 (3) on-chip peripheral i/o area a 4 kb area of addresses fff000h to ffffffh is reserved as an on-chip peripheral i/o area. the v850/sc1, v850/sc2, and v850/sc3 are provided with a 1 kb area of addresses fff000h to fff3ffh as a physical on- chip peripheral i/o area. the rest of the area (fff400h to ffffffh) shows images of these addresses. peripheral i/o registers associated with the operating mode specification and state monitoring for the on-chip peripherals are all memory-mapped to the on-chip peripheral i/o area. program fetches are not allowed in this area. figure 3-9. on-chip peripheral i/o area xxffffffh xxfffc00h xxfffbffh xxfff800h xxfff7ffh xxfff400h xxfff3ffh xxfff000h image image image physical on-chip peripheral i/o 3ffh 000h image peripheral i/o cautions 1. the least significant bit of an address is not decoded since all registers reside on an even address. if an odd address (2n + 1) in the peripheral i/o area is referenced (accessed in byte units), the register at the next lowest even address (2n) will be accessed. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined, if the access is a read operation. if a write access is made, only the data in the lower 8 bits is written to the register. 3. if a register with address n that can be accessed only in halfword units is accessed in word units, the operation is replaced with two halfword operations. the first operation (lower 16 bits) accesses the register with address n and the second operation (higher 16 bits) accesses the register with address n + 2. 4. if a register with address n that can be accessed in word units is accessed with a word operation, the operation is replaced with two halfword operations. the first operation (lower 16 bits) accesses the register with address n and the second operation (higher 16 bits) accesses the register with address n + 2. 5. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed.
chapter 3 cpu functions user ? s manual u15109ej3v0ud 101 (4) external memory the v850/sc1, v850/sc2, and v850/sc3 can use an area of up to 16 mb (xx100000h to xxff7fffh) for external memory accesses (in single-chip mode: external expansion). 64 kb, 256 kb, 1 mb, or 4 mb of physical external memory can be allocated when the external expansion mode is specified. in other than the physical external memory area, images of the physical external memory can be seen. the internal ram area and on-chip peripheral i/o area are not subject to external memory access. caution addresses xxnff800h to xxnfffffh (n = 3, 7, b) constitute an access-prohibited area because this is an fcan address area. figure 3-10. external memory area (when expanded to 64 kb, 256 kb, or 1 mb) xxffffffh xx000000h physical external memory xffffh x0000h on-chip peripheral i/o internal ram image image image internal rom xxff7fffh xx100000h external memory
chapter 3 cpu functions user ? s manual u15109ej3v0ud 102 figure 3-11. external memory area (when expanded to 4 mb) xxffffffh xx000000h physical external memory fcan address area external memory 3fffffh 3ff800h 3ff7ffh 000000h on-chip peripheral i/o internal ram image image xxff7fffh xxc00000h xxbfffffh xx800000h xx7fffffh xx400000h xx3fffffh xx100000h xx0fffffh internal rom image
chapter 3 cpu functions user ? s manual u15109ej3v0ud 103 3.4.6 external expansion mode the v850/sc1, v850/sc2, and v850/sc3 allow external devices to be connected to the external memory space using the pins of ports 4, 5, 6, and 9. to connect an external device, the port pins must be set in the external expansion mode using the memory expansion mode register (mm). in the v850/sc1 and v850/sc2, the address bus (a1 to a15) is set to multiplexed output with the data bus (d1 to d15), however, separate output is also available by setting the memory address output mode register (mam) (see the user ? s manual of the relevant in-circuit emulator about debugging when using the separate bus). caution because the a1 pin and wait pin are alternate-function pins for the v850/sc1 and v850/sc2, the wait pin based wait function cannot be used when using a separate bus (programmable wait can be used, however). similarly, a separate bus cannot be used when the wait pin based wait function is being used. because the v850/sc1, v850/sc2, and v850/sc3 are fixed to single-chip mode in the normal operating mode, the pins related to the bus interface are set to port mode, disabling use of the external memory. when the external memory is used (external expansion mode), specify the mm register or mam register by program (for the v850/sc1 and v850/sc2) or specify the mm register by program (for the v850/sc3).
chapter 3 cpu functions user ? s manual u15109ej3v0ud 104 (1) memory expansion mode register (mm) this register sets the mode of each pin of ports 4, 5, 6, and 9 in the v850/sc1, v850/sc2, and v850/sc3. in the external expansion mode, an external device can be connected to an external memory area of up to 4 mb. however, the external device cannot be connected to the internal ram area, on-chip peripheral i/o area, and internal rom area in the single-chip mode (and even if the external device is connected physically, it cannot be accessed). the mm register can be read/written in 8- or 1-bit units. however, bits 4 to 7 are fixed to 0. after reset: 00h r/w address: fffff04ch symbol7654<3><2><1><0> mm 0 0 0 0 mm3 mm2 mm1 mm0 mm3 p95 and p96 operating modes 0 port mode 1 external expansion mode (hldak: p95, hldrq: p96) mm2 mm1 mm0 address space port 4 port 5 port 6 port 9 000 ? port mode 0 1 1 64 kb expansion mode 1 0 0 256 kb expansion mode 101 1 mb expansion mode 11 4 mb expansion mode ad0 to ad7 ad8 to ad15 a16, a17 a18, a19 a20, a21 lben, uben, r/w, dstb, astb, wrl note , wrh note , rd note other than above rfu (reserved) note only for the v850/sc1 and v850/sc2 caution before switching to the external expansion mode, be sure to set p93 and p94 of port 9 (p9) to 1. remark for details of the operation of each port pin, refer to 2.3 description of pin functions .
chapter 3 cpu functions user ? s manual u15109ej3v0ud 105 (2) memory address output mode register (mam) this register sets the mode of ports 3, 10, and 11 in the v850/sc1 and v850/sc2. separate output can be set for the address bus (a1 to a15) in the external expansion mode. the mam register can be written in 8-bit units. if read is performed, undefined values will be read. however, bits 3 to 7 are fixed to 0. after reset: 00h w address: fffff068h symbol76543210 mam 0 0 0 0 0 mam2 mam1 mam0 mam2 mam1 mam0 address space port 11 port 10 port 3 000 ? port mode 0 1 0 32 bytes 0 1 1 512 bytes 100 8 kb 101 16 kb 110 32 kb 111 64 kb a1 to a4 a5 to a8 a9 to a12 a13 a14 a15 other than above setting prohibited caution the memory address output mode register (mam) cannot be debugged by an in-circuit emulator. also, switching to a separate bus is not possible by setting the mam register using software. for details, refer to the user ? s manual of the relevant in-circuit emulator. remark for details of the operation of each port, see 2.3 description of pin functions . p34 to p36, p100 to p107, and p110 to p113 are used for separate bus output. the procedure for performing separate bus output is shown below. <1> set the pn bit of port m (pm) used for separate output to 0 (m = 3, 10, 11). <2> set the pmn bit of the port m mode register (pmm) to 0 (output mode) (m = 3, 10, 11). <3> when the port to be used for the separate bus is used as an alternate-function pin for other than the separate bus, turn off the function that uses the alternate-function pin. <4> set the memory address output mode register (mam). <5> set the memory expansion mode register (mm). remark when m = 3: n = 34 to 36 when m = 10: n = 100 to 107 when m = 11: n = 110 to 113
chapter 3 cpu functions user ? s manual u15109ej3v0ud 106 3.4.7 recommended use of address space the architecture of the v850/sc1, v850/sc2, and v850/sc3 requires that a register that serves as a pointer be secured for address generation when accessing operand data in the data space. operand data can be accessed directly from an instruction in the 32 kb above and below the address in this pointer register. however, the general- purpose registers that can be used as a pointer register are limited. therefore, by minimizing the deterioration of address calculation performance when changing the pointer value, the number of usable general-purpose registers for handling variables is maximized, and the program size can be saved because instructions for calculating pointer addresses are not required. to enhance the efficiency of using the pointer in connection with the memory maps of the v850/sc1, v850/sc2, and v850/sc3, the following points are recommended: (1) program space of the 32 bits of the pc (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. therefore, a continuous 16 mb space, starting from address 00000000h, unconditionally corresponds to the memory map of the program space. (2) data space for the efficient use of resources utilizing the wrap-around feature of the data space, the continuous 8 mb address spaces 00000000h to 007fffffh and ff800000h to ffffffffh of the 4 gb cpu are used as the data space. with the v850/sc1, v850/sc2, and v850/sc3, a 16 mb physical address space is seen as 256 images in the 4 gb cpu address space. the highest bit (bit 23) of this 24-bit address is assigned as an address sign-extended to 32 bits. (a) application of wrap-around for example, when r = r0 (zero register) is specified for the ld/st disp16 [r] instruction, an addressing range of 00000000h 32 kb can be referenced by a sign-extended, 16-bit displacement value. all resources including on-chip hardware can therefore be accessed with one pointer. the zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers for the pointer. figure 3-12. application of wrap-around internal rom area on-chip peripheral i/o area internal ram area 4 kb 24 kb 0007ffffh 00007fffh (r =) 00000000h fffff000h access prohibited area 4 kb ffff9000h ffff8000h 32 kb
chapter 3 cpu functions user ? s manual u15109ej3v0ud 107 figure 3-13. recommended memory map (flash memory version) ffffffffh fffff400h fffff3ffh 00000000h 16 mb 8 mb internal rom internal rom external memory internal ram internal peripheral i/o note 1 program space data space on-chip peripheral i/o internal ram external memory internal peripheral i/o internal ram access prohibited area external memory external memory internal rom xxffffffh xxfff400h xxfff3ffh xxfff000h xxffefffh xxff9000h xxff8fffh xxff8000h xxff7fffh xx100000h xx0fffffh xx080000h xx07ffffh xx800000h xx7fffffh xx000000h fffff000h ffffefffh ffff8000h ffff7fffh ff800000h ff7fffffh 01000000h 00ffffffh 00fff000h 00ffefffh 00ff8000h 00ff7fffh 00800000h 007fffffh 00100000h 000fffffh 00080000h 0007ffffh note 2 notes 1. this area cannot be used as a program area. 2. addresses xxnf800h to xxnffffh (n = 3, 7, b) constitute an fcan address area and cannot be accessed during external expansion. remarks 1. the arrows indicate the recommended area. 2. this is a recommended memory map for the pd70f3089y.
chapter 3 cpu functions user ? s manual u15109ej3v0ud 108 3.4.8 peripheral i/o registers (1/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff000h port 0 p0 ? fffff002h port 1 p1 ? fffff004h port 2 p2 ? fffff006h port 3 p3 ? fffff008h port 4 p4 ? fffff00ah port 5 p5 ? fffff00ch port 6 p6 r/w ? 00h note fffff00eh port 7 p7 ? fffff010h port 8 p8 r ? undefined fffff012h port 9 p9 ? fffff014h port 10 p10 ? fffff016h port 11 p11 ? fffff018h port 12 p12 ? fffff01ah port 13 p13 ? fffff01ch port 14 p14 ? fffff01eh port 15 p15 ? 00h note fffff020h port 0 mode register pm0 ? ffh fffff022h port 1 mode register pm1 ? ffh fffff024h port 2 mode register pm2 ? fffff026h port 3 mode register pm3 ? fffff028h port 4 mode register pm4 ? fffff02ah port 5 mode register pm5 ? ffh fffff02ch port 6 mode register pm6 ? 3fh fffff032h port 9 mode register pm9 ? 7fh fffff034h port 10 mode register pm10 ? ffh fffff036h port 11 mode register pm11 ? fffff038h port 12 mode register pm12 ? ffh fffff03ah port 13 mode register pm13 ? 0fh fffff03ch port 14 mode register pm14 ? fffff03eh port 15 mode register pm15 ? ffh fffff040h port alternate-function control register pac ? fffff042h port alternate-function control register 2 pac2 ? fffff048h port 17 p17 ? fffff04ch memory expansion mode register mm ? 00h fffff058h port 17 mode register pm17 r/w ? 7fh note resetting initializes registers to input mode, so the pin level is read during a read operation. the output latch is initialized to 00h.
chapter 3 cpu functions user ? s manual u15109ej3v0ud 109 (2/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff060h data wait control register dwc ffffh fffff062h bus cycle control register bcc aaaah fffff064h system control register note 1 syc r/w ? fffff068h memory address output mode register note 1 mam w 00h fffff070h power save control register psc ? c0h fffff074h processor clock control register pcc ? 03h fffff076h poc control register pocc 00h fffff078h system status register sys r/w ? 00h fffff07ah poc status register pocs r held note 2 fffff07ch vm45 control register vm45c fffff094h pull-up resistor option register 10 pu10 ? fffff0a2h port 1 function register pf1 ? fffff0a4h port 2 function register pf2 ? fffff0c0h rising edge specification register 0 egp0 ? fffff0c2h falling edge specification register 0 egn0 ? fffff0c4h rising edge specification register 1 egp1 ? fffff0c6h falling edge specification register 1 egn1 r/w ? 00h fffff0d0h 16-bit timer register 10 tm10 r fffff0d2h 16-bit capture/compare register 100 cr100 note 3 fffff0d4h 16-bit capture/compare register 101 cr101 0000h fffff0d6h prescaler mode register 100 prm100 r/w fffff0d8h 16-bit timer mode control register 10 tmc10 ? fffff0dah capture/compare control register 10 crc10 ? fffff0dch timer output control register 10 toc10 ? fffff0deh prescaler mode register 101 prm101 00h fffff0e0h 16-bit timer register 11 tm11 r fffff0e2h 16-bit capture/compare register 110 cr110 note 3 fffff0e4h 16-bit capture/compare register 111 ce111 0000h fffff0e6h prescaler mode register 110 prm110 r/w fffff0e8h 16-bit timer mode control register 11 tmc11 ? fffff0eah capture/compare control register 11 crc11 ? fffff0ech timer output control register 11 toc11 ? fffff0eeh prescaler mode register 111 prm111 00h fffff0f0h 16-bit timer register 12 tm12 r fffff0f2h 16-bit capture/compare register 120 cr120 fffff0f4h 16-bit capture/compare register 121 cr121 note 3 0000h notes 1. only for the v850/sc1 and v850/sc2 2. this value is 03h only after a power-on-clear reset. this cannot be reset by reset signal input or watchdog timer. 3. in compare mode: r/w in capture mode: r
chapter 3 cpu functions user ? s manual u15109ej3v0ud 110 (3/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff0f6h prescaler mode register 120 prm120 fffff0f8h 16-bit timer mode control register 12 tmc12 ? fffff0fah capture/compare control register 12 crc12 ? fffff0fch timer output control register 12 toc12 ? fffff0feh prescaler mode register 121 prm121 00h fffff100h interrupt control register wdtic ? fffff102h interrupt control register pic0 ? fffff104h interrupt control register pic1 ? fffff106h interrupt control register pic2 ? fffff108h interrupt control register pic3 ? fffff10ah interrupt control register pic4 ? fffff10ch interrupt control register pic5 ? fffff10eh interrupt control register pic6 ? fffff110h interrupt control register csic5 ? fffff112h interrupt control register adic ? fffff114h interrupt control register dmaic0 ? fffff116h interrupt control register dmaic1 ? fffff118h interrupt control register dmaic2 ? fffff11ah interrupt control register tmic00 ? fffff11ch interrupt control register tmic01 ? fffff11eh interrupt control register tmic10 ? fffff120h interrupt control register tmic11 ? fffff122h interrupt control register tmic70 ? fffff124h interrupt control register tmic71 ? fffff126h interrupt control register csic6 ? fffff128h interrupt control register tmic5 ? fffff12ah interrupt control register wtnic ? fffff12ch interrupt control register wtniic ? fffff12eh interrupt control register csic0 ? fffff130h interrupt control register tmic6 ? fffff132h interrupt control register csic4 ? fffff134h interrupt control register stic0 ? fffff136h interrupt control register kric ? fffff138h interrupt control register note 1 ? fffff13ah interrupt control register note 2 ? fffff13ch interrupt control register note 3 canic3 ? fffff13eh interrupt control register note 3 canic7 r/w ? 47h notes 1. canic1 (v850/sc3)/iebic1 (v850/sc2) 2. canic2 (v850/sc3)/iebic2 (v850/sc2) 3. only for the v850/sc3
chapter 3 cpu functions user ? s manual u15109ej3v0ud 111 (4/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff140h interrupt control register tmic80 ? fffff142h interrupt control register tmic81 ? fffff144h interrupt control register tmic90 ? fffff146h interrupt control register tmic91 ? fffff148h interrupt control register csic3 ? fffff14ah interrupt control register stic1 ? fffff14ch interrupt control register dmaic3 ? fffff14eh interrupt control register dmaic4 ? fffff150h interrupt control register dmaic5 ? fffff152h interrupt control register note canic4 ? fffff154h interrupt control register note canic5 ? fffff156h interrupt control register note canic6 ? fffff158h interrupt control register pic7 ? fffff15ah interrupt control register sric2 ? fffff15ch interrupt control register stic2 ? fffff15eh interrupt control register sric3 ? fffff160h interrupt control register stic3 ? fffff162h interrupt control register tmic100 ? fffff164h interrupt control register tmic101 r/w ? 47h fffff166h in-service priority register ispr r ? 00h fffff168h interrupt control register tmic110 ? fffff16ah interrupt control register tmic111 ? fffff16ch interrupt control register tmic120 ? fffff16eh interrupt control register tmci121 r/w ? 47h fffff170h command register prcmd w undefined fffff172h interrupt control register csic2 ? 47h fffff180h dma peripheral i/o address register 0 dioa0 fffff182h dma internal ram address register 0 dra0 fffff184h dma byte count register 0 dbc0 undefined fffff186h dma channel control register 0 dchc0 ? 00h fffff190h dma peripheral i/o address register 1 dioa1 fffff192h dma internal ram address register 1 dra1 fffff194h dma byte count register 1 dbc1 undefined fffff196h dma channel control register 1 dchc1 ? 00h fffff1a0h dma peripheral i/o address register 2 dioa2 fffff1a2h dma internal ram address register 2 dra2 fffff1a4h dma byte count register 2 dbc2 r/w undefined note available only for the pd703089y and 70f3089y.
chapter 3 cpu functions user ? s manual u15109ej3v0ud 112 (5/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff1a6h dma channel control register 2 dchc2 ? 00h fffff1b0h dma peripheral i/o address register 3 dioa3 fffff1b2h dma internal ram address register 3 dra3 fffff1b4h dma byte count register 3 dbc3 undefined fffff1b6h dma channel control register 3 dchc3 ? 00h fffff1c0h dma peripheral i/o address register 4 dioa4 fffff1c2h dma internal ram address register 4 dra4 fffff1c4h dma byte count register 4 dbc4 undefined fffff1c6h dma channel control register 4 dchc4 ? 00h fffff1d0h dma peripheral i/o address register 5 dioa5 fffff1d2h dma internal ram address register 5 dra5 fffff1d4h dma byte count register 5 dbc5 undefined fffff1d6h dma channel control register 5 dchc5 r/w ? 00h fffff200h 16-bit timer register 0 tm0 r fffff202h 16-bit capture/compare register 00 cr00 fffff204h 16-bit capture/compare register 01 cr01 note 0000h fffff206h prescaler mode register 00 prm00 fffff208h 16-bit timer mode control register 0 tmc0 ? fffff20ah capture/compare control register 0 crc0 ? fffff20ch timer output control register 0 toc0 ? fffff20eh prescaler mode register 01 prm01 r/w 00h fffff210h 16-bit timer register 1 tm1 r fffff212h 16-bit capture/compare register 10 cr10 fffff214h 16-bit capture/compare register 11 cr11 note 0000h fffff216h prescaler mode register 10 prm10 fffff218h 16-bit timer mode control register 1 tmc1 ? fffff21ah capture/compare control register 1 crc1 ? fffff21ch timer output control register 1 toc1 ? fffff21eh prescaler mode register 11 prm11 fffff230h asynchronous serial interface mode register 2 asim2 r/w ? fffff232h asynchronous serial interface status register 2 asis2 r ? fffff234h baud rate generator control register 2 brgc2 r/w 00h fffff236h transmit shift register 2 txs2 w fffff238h receive buffer register 2 rxb2 r ffh fffff23ah baud rate generator mode control register 20 brgmc 20 r/w 00h note in compare mode: r/w in capture mode: r
chapter 3 cpu functions user ? s manual u15109ej3v0ud 113 (6/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff23ch baud rate generator mode control register 21 brgmc 21 r/w fffff240h clocked serial interface mode register 5 csim5 ? fffff242h clocked serial interface clock select register 5 csick5 r/w ? 00h fffff244h clocked serial interface receive buffer register 5 sirb5 0000h fffff246h clocked serial interface receive buffer register l5 sirbl5 r 00h fffff248h clocked serial interface transmit buffer register 5 sotb5 0000h fffff24ah clocked serial interface transmit buffer register l5 sotbl5 r/w ? 00h fffff24ch clocked serial interface read-only receive buffer register 5 sirbe5 0000h fffff24eh clocked serial interface read-only receive buffer register l5 sirbel5 r ? 00h fffff250h clocked serial interface initial transmit buffer register 5 sotbf5 0000h fffff252h clocked serial interface initial transmit buffer register l5 sotbfl5 r/w ? 00h fffff254h serial i/o shift register 5 sio5 0000h fffff256h serial i/o shift register l5 siol5 r ? 00h fffff260h clocked serial interface mode register 6 csim6 ? 0000h fffff262h clocked serial interface clock select register 6 csick6 r/w ? 00h fffff264h clocked serial interface receive buffer register 6 sirb6 0000h fffff266h clocked serial interface receive buffer register l6 sirbl6 r 00h fffff268h clocked serial interface transmit buffer register 6 sotb6 0000h fffff26ah clocked serial interface transmit buffer register l6 sotbl6 r/w ? 00h fffff26ch clocked serial interface read-only receive buffer register 6 sirbe6 0000h fffff26eh clocked serial interface read-only receive buffer register l6 sirbel6 r ? 00h fffff270h clocked serial interface initial transmit buffer register 6 sotbf6 0000h fffff272h clocked serial interface initial transmit buffer register l6 sotbfl6 r/w ? 00h fffff274h serial i/o shift register 6 sio6 000h fffff276h serial i/o shift register l6 siol6 r ? fffff284h timer clock select register 60 tcl60 00h fffff286h timer mode control register 60 tmc60 r/w ? 04h note note although the hardware status is initialized to 04h, 00h is readout if read.
chapter 3 cpu functions user ? s manual u15109ej3v0ud 114 (7/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff28ah 16-bit counter 6 tm6 r fffff28ch 16-bit compare register 6 cr6 0000h fffff28eh timer clock select register 61 tcl61 fffff2a0h serial i/o shift register 0 sio0 fffff2a2h serial operation mode register 0 csim0 ? fffff2a4h serial clock select register 0 csis0 fffff2b0h asynchronous serial interface mode register 3 asim3 r/w ? fffff2b2h asynchronous serial interface status register 3 asis3 r ? fffff2b4h baud rate generator control register 3 brgc3 r/w 00h fffff2b6h transmit shift register 3 txs3 w fffff2b8h receive buffer register 3 rxb3 r ffh fffff2bah baud rate generator mode control register 30 brgmc 30 fffff2bch baud rate generator mode control register 31 brgmc 31 fffff2c0h serial i/o shift register 2 sio2 fffff2c2h serial operation mode register 2 csim2 ? fffff2c4h serial clock select register 2 csis2 fffff2d0h serial i/o shift register 3 sio3 fffff2d2h serial operation mode register 3 csim3 ? fffff2d4h serial clock select register 3 csis3 00h fffff2e0h variable-length serial i/o shift register 4 sio4 0000h fffff2e2h variable-length serial control register 4 csim4 ? fffff2e4h variable-length serial setting register 4 csib4 ? fffff2e6h baud rate generator source clock select register 4 brgcn4 00h fffff2e8h baud rate output clock select register 4 brgck4 7fh fffff300h asynchronous serial interface mode register 0 asim0 r/w ? fffff302h asynchronous serial interface status register 0 asis0 r ? fffff304h baud rate generator control register 0 brgc0 r/w 00h fffff306h transmission shift register 0 txs0 w fffff308h reception buffer register 0 rxb0 r ffh fffff30eh baud rate generator mode control register 00 brgmc00 fffff310h asynchronous serial interface mode register 1 asim1 r/w ? fffff312h asynchronous serial interface status register 1 asis1 r ? fffff314h baud rate generator control register 1 brgc1 r/w 00h fffff316h transmit shift register 1 txs1 w fffff318h receive buffer register 1 rxb1 r ffh
chapter 3 cpu functions user ? s manual u15109ej3v0ud 115 (8/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff31eh baud rate generator mode control register 10 brgmc10 fffff320h baud rate generator mode control register 01 brgmc01 fffff322h baud rate generator mode control register 11 brgmc11 fffff334h timer clock select register 50 tcl50 00h fffff336h timer mode control register 50 tmc50 r/w ? 04h note fffff33ah 16-bit counter 5 tm5 r fffff33ch 16-bit compare register 5 cr5 0000h fffff33eh timer clock select register 51 tcl51 fffff340h iic control register 0 iicc0 r/w ? fffff342h iic status register 0 iics0 r ? fffff344h iic clock select register 0 iiccl0 ? fffff346h slave address register 0 sva0 fffff348h iic shift register 0 iic0 fffff34ah iic function expansion register 0 iicx0 ? fffff34ch iic clock expansion register 0 iicce0 fffff350h iic control register 1 iicc1 r/w ? fffff352h iic status register 1 iics1 r ? fffff354h iic clock select register 1 iiccl1 ? fffff356h slave address register 1 sva1 fffff358h iic shift register 1 iic1 fffff35ah iic function expansion register 1 iicx1 ? fffff35ch iic clock expansion register 1 iicce1 fffff360h watch timer mode register wtnm ? fffff364h watch timer clock select register wtncs fffff366h watch timer high-speed clock select register wtnhc fffff368h iic flag register 0 iicf0 ? fffff36ah iic flag register 1 iicf1 ? fffff36ch correction control register corcn ? fffff36eh correction request register corrq ? 00h fffff370h correction address register 0 corad0 fffff374h correction address register 1 corad1 fffff378h correction address register 2 corad2 fffff37ch correction address register 3 corad3 00000000h fffff380h oscillation stable time select register osts 01h fffff382h watchdog timer clock select register wdcs fffff384h watchdog timer mode register wdtm ? fffff38eh dma start factor expansion register dmas r/w ? 00h note although the hardware status is initialized to 04h, 00h is readout if read.
chapter 3 cpu functions user ? s manual u15109ej3v0ud 116 (9/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff390h 16-bit timer register 8 tm8 r fffff392h 16-bit capture/compare register 80 cr80 fffff394h 16-bit capture/compare register 81 cr81 note 1 0000h fffff396h prescaler mode register 80 prm80 fffff398h 16-bit timer mode control register 8 tmc8 ? fffff39ah capture/compare control register 8 crc8 ? fffff39ch timer output control register 8 toc8 ? fffff39eh prescaler mode register 81 prm81 r/w 00h fffff3a0h 16-bit timer register 7 tm7 r fffff3a2h 16-bit capture/compare register 70 cr70 fffff3a4h 16-bit capture/compare register 71 cr71 note 1 0000h fffff3a6h prescaler mode register 70 prm70 fffff3a8h 16-bit timer mode control register 7 tmc7 ? fffff3aah capture/compare control register 7 crc7 ? fffff3ach timer output control register 7 toc7 ? fffff3aeh prescaler mode register 71 prm71 r/w 00h fffff3b0h 16-bit timer register 9 tm9 r fffff3b2h 16-bit capture/compare register 90 cr90 fffff3b4h 16-bit capture/compare register 91 cr91 note 1 0000h fffff3b6h prescaler mode register 90 prm90 fffff3b8h 16-bit timer mode control register 9 tmc9 ? fffff3bah capture/compare control register 9 crc9 ? fffff3bch timer output control register 9 toc9 ? fffff3beh prescaler mode register 91 prm91 fffff3c0h a/d converter mode register 1 adm1 ? fffff3c2h analog input channel specification register ads r/w ? 00h fffff3c4h a/d conversion result register adcr 0000h fffff3c6h a/d conversion result register h (higher 8 bits) adcrh r fffff3c8h a/d converter mode register 2 adm2 ? fffff3d0h key return mode register krm ? fffff3d4h noise elimination control register ncc fffff3e0h iebus control register note 2 bcr ? 00h fffff3e2h iebus local unit register note 2 uar fffff3e4h iebus slave address register note 2 sar r/w fffff3e6h iebus partner address register note 2 par r 0000h notes 1. in compare mode: r/w in capture mode: r 2. only for the v850/sc2
chapter 3 cpu functions user ? s manual u15109ej3v0ud 117 (10/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff3e8h iebus control data register note cdr fffff3eah iebus telegraph length register note dlr 01h fffff3ech iebus data register note dr r/w fffff3eeh iebus unit status register note usr r ? fffff3f0h iebus interrupt status register note isr r/w ? 00h fffff3f2h iebus slave status register note ssr ? 41h fffff3f4h iebus communication success counter note scr 01h fffff3f6h iebus transmit counter note ccr r 20h fffff3f8h iebus clock select register note ieclk r/w 00h note only for the v850/sc2
chapter 3 cpu functions user ? s manual u15109ej3v0ud 118 3.4.9 specific registers specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. the write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, the system status register (sys) is notified. the v850/sc1, v850/sc2, and v850/sc3 have two specific registers, the power save control register (psc) and processor clock control register (pcc). for details of the psc register, refer to 4.3.1 (2) power save control register (psc), and for details of the pcc register, refer to 4.3.1 (1) processor clock control register (pcc). the following sequence shows data setting in the specific registers. <1> disable dma operation. <2> set the psw np bit to 1 (interrupt disabled). <3> write any 8-bit data in the command register (prcmd). <4> write the set data in the specific registers (by the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> return the psw np bit to 0 (interrupt disable canceled). <6> if necessary, enable dma operation. no special sequence is required when reading the specific registers. cautions 1. if an interrupt request or a dma request is acknowledged between the time prcmd is generated (<3>) and the specific register write operation (<4>) that follows immediately after, the write operation to the specific register is not performed and a protection error (prerr bit of sys register = 1) may occur. therefore, set the np bit of psw to 1 (<2>) to disable the acknowledgement of int/nmi or to disable dma transfer. the above also applies when a bit manipulation instruction is used to set a specific register. a description example is given below. [description example]: in case of pcc register ldsr rx.5 ; np bit = 1 st.b r0, prcmd[r0] ; write to prcmd st.b rd, pcc[r0] ; pcc register setting ldsr ry, 5 ; np bit = 0 . . . remark the above example assumes that rd (pcc set value), rx (value to be written to psw), and ry (value rewritten to psw) are already set. when saving the value of the psw, the value of the psw prior to setting the np bit must be transferred to the ry register. 2. always stop dma prior to accessing specific registers. 3. if data is set to the psc register to set idle mode or stop mode, a dummy instruction needs to be inserted for correct execution of the routine after idle or stop mode is released. for details, refer to 4.6 cautions on power save function.
chapter 3 cpu functions user ? s manual u15109ej3v0ud 119 (1) command register (prcmd) the command register (prcmd) is a register used when write-accessing the specific register to prevent incorrect writing to the specific registers due to erroneous program execution. this register can be written in 8-bit units. it becomes undefined in a read cycle. the occurrence of illegal store operations can be checked by the prerr bit of the sys register. after reset: undefined w address: fffff170h symbol76543210 prcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 regn registration code 0/1 any 8-bit data remark n = 0 to 7 (2) system status register (sys) this register is assigned status flags showing the operating state of the entire system. this register can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff078h symbol765<4>3210 sys 0 0 0 prerr 0 0 0 0 prerr detection of protection error 0 protection error did not occur 1 protection occurred the operating conditions of the prerr flag are shown below. (a) set conditions (prerr = 1) (1) when a write operation to the specific register took place in a state where the store instruction operation for the recent peripheral i/o was not a write operation to the prcmd register (2) when the first store instruction operation following a write operation to the prcmd register is to any peripheral i/o register apart from a specific register (including the prcmd register and sys register) (b) reset conditions: (prerr = 0) (1) when 0 is written to the prerr flag of the sys register (however, excluding the case of remark 1 ) (2) at system reset remarks 1. if 0 is written to the prerr bit immediately after a write operation to the prcmd register, the prerr bit is set to 1 (because the sys register is not a specific register). 2. if the prcmd register is written again immediately after a write operation to the prcmd register, the prerr bit of the sys register is set to 1 (because the sys register is not a specific register).
user?s manual u15109ej3v0ud 120 chapter 4 clock generation function 4.1 general the clock generator is a circuit that generates the clock pulses that are supplied to the cpu and peripheral hardware. there are two types of system clock oscillators. (1) main clock oscillator the v850/sc1 and v850/sc3 have an oscillation frequency of 4 to 20 mhz and the v850/sc2 4 to 18.87 mhz. oscillation can be stopped by setting the stop mode or by setting the processor clock control register (pcc). oscillation is also stopped during a reset. in idle mode, supplying the peripheral clock to the clock timer only is possible. therefore, in idle mode, it is possible to operate the clock timer without using the subclock oscillator. cautions 1. when the main clock oscillator is stopped by reset input or stop mode setting, the oscillation stabilization time is secured after the stop mode is canceled. this oscillation stabilization time is set via the oscillation stabilization time select register (osts). the watchdog timer is used to count the oscillation stabilization time. 2. if the main clock halt is released by clearing mck to 0 after the main clock is stopped by setting the mck bit in the pcc register to 1, the oscillation stabilization time is not secured. 3. external clock input is disabled. (2) subclock oscillator this circuit has an oscillation frequency of 32.768 khz. its oscillation is not stopped when the stop mode is set, nor when a reset is input. when the subclock oscillator is not used, the frc bit in the processor clock control register (pcc) can be set to disable use of the internal feedback resistor. this enables a reduction in current consumption in the stop mode.
chapter 4 clock generation function user ? s manual u15109ej3v0ud 121 4.2 configuration figure 4-1. clock generator f xt f xt f xx /8 f xx stp, mck frc prescaler prescaler x2 x1 xt2 xt1 idle main clock oscillator subclock oscillator idle control idle control selector clock supplied to watch timer, etc. clock supplied to peripheral hardware halt halt control cpu clock (f cpu ) clkout f xx /4 f xx /2 ck2 to ck0 4.3 clock output function this function outputs the cpu clock via the clkout pin. when clock output is enabled, the cpu clock is output via the clkout pin. when it is disabled, a low-level signal is output via the clkout pin. output is stopped in the idle or stop mode (fixed to low level). this function is controlled via the dclk1 and dclk0 bits in the psc register. a high-impedance status is set during the reset period. after reset is canceled, a low level is output. caution while clkout is being output, changing the cpu clock (ck2 to ck0 bits of pcc register) is disabled.
chapter 4 clock generation function 122 user ? s manual u15109ej3v0ud 4.3.1 control registers (1) processor clock control register (pcc) this is a specific register. it can be written to only when a specified combination of sequences is used (see 3.4.9 specific registers ). this register can be read/written in 8- or 1-bit units. after reset: 03h r/w address: fffff074h <7> <6> 5 4 3 <2> 1 0 pcc frc mck 0 0 0 ck2 ck1 ck0 frc selection of internal feedback resistor for subclock 0use 1 do not use mck operation of main clock 0 operate 1stop ck2 notes 1, 2 ck1 ck0 selection of cpu clock 000f xx 001f xx /2 010f xx /4 011f xx /8 1xxf xt (subclock) notes 1. it is recommended to manipulate ck2 in 1-bit units. however, when manipulating the pcc register in 8-bit units, be sure not to change the values of ck1 and ck0. 2. do not set the stop mode when the cpu is operating on the subclock (ck2 = 1). cautions 1. do not change the cpu clock (the values of ck2 to ck0 in the pcc register) while clkout is being output. 2. even if the mck bit is set to 1 during main clock operation, the main clock is not stopped. the cpu clock stops after the subclock is selected. 3. always set bits 5 to 3 to 0. remark x: don ? t care (a) example of main clock operation subclock operation setting <1> ck2 1: bit manipulation instructions are recommended. do not change ck1 and ck0. <2> subclock operation: it takes up to the following number of instructions for the subclock to start operating after the ck2 bit is set. (cpu clock frequency before setting / subclock frequency) 2 it is therefore necessary to insert waits equivalent to this number using a program.
chapter 4 clock generation function user ? s manual u15109ej3v0ud 123 <3> mck 1: only when the main clock is stopped. (b) example of subclock operation main clock operation setting <1> mck 0: main clock oscillation start <2> insert waits using a program and wait until the main clock oscillation stabilization time elapses. <3> ck2 0: bit manipulation instructions are recommended. do not change ck1 and ck0. <4> main clock operation: it takes up to two instructions to start main clock operation after the ck2 bit is set. (2) power save control register (psc) this is a specific register. it can be written to only when a specified combination of sequences is used. for details, see 3.4.9 specific registers . this register can be read/written in 8- or 1-bit units. after reset: c0h r/w address: fffff070h 76543<2><1>0 psc dclk1 dclk0 0 0 0 idle stp 0 dclk1 dclk0 specification of clkout pin operation 00 output enabled 01 hi-z output note 1 10 setting prohibited 11 output disabled (after reset) idle idle mode setting 0 normal mode 1 idle mode note 2 stp stop mode setting 0 normal mode 1 stop mode note 3 notes 1. hi-z cannot be output from the in-circuit emulator. 2. when idle mode is canceled, this bit is automatically reset to 0. 3. when stop mode is canceled, this bit is automatically reset to 0. caution the dclk0 and dclk1 bits should be manipulated in 8-bit units.
chapter 4 clock generation function 124 user ? s manual u15109ej3v0ud (3) oscillation stabilization time select register (osts) this register can be read/written in 8-bit units. after reset: 01h r/w address: fffff380h 76543210 osts 0 0 0 0 0 osts2 osts1 osts0 selection of oscillation stabilization time f xx osts2 osts1 osts0 clock 20 mhz 18.87 mhz 16 mhz 0002 16 /f xx 3.3 ms 3.5 ms 4.10 ms 0012 18 /f xx (after reset) 13.1 ms 13.9 ms 16.4 ms 0102 19 /f xx 26.2 ms 27.8 ms 32.8 ms 0112 20 /f xx 52.4 ms 55.6 ms 65.5 ms 1002 21 /f xx 104.9 ms 111.1 ms 131 ms other than above setting prohibited
chapter 4 clock generation function user ? s manual u15109ej3v0ud 125 4.4 power save functions 4.4.1 general this product provides the following power saving functions. these modes can be combined and switched to suit the target application, thus enabling the effective implementation of low-power systems. (1) halt mode in this mode, the clock oscillator continues to operate but the cpu operating clock is stopped. a clock continues to be supplied for other on-chip peripheral functions to maintain the operation of those functions. this enables the system ? s total power consumption to be reduced. a special-purpose instruction (the halt instruction) is used to switch to halt mode. (2) idle mode this mode stops the entire system by stopping the cpu operating clock as well as the operating clock for on-chip peripheral functions while the clock oscillator is still operating. however, the subclock continues to operate and supplies a clock to the on-chip peripheral functions. when this mode is canceled, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. when the idle bit in the power save control register (psc) is set (1), the system switches to idle mode. (3) software stop mode this mode stops the entire system by stopping the main clock oscillators. the subclock continues to be supplied to keep on-chip peripheral functions operating. if the subclock is not used, ultra-low-power-consumption mode (leak current only) is set. stop mode setting is prohibited if the cpu is operating via the subclock. if the stp bit of the psc register is set (1), the system enters stop mode. (4) subclock operation in this mode, the cpu clock is set to operate using the subclock and the mck bit of the pcc register is set (1) to set low-power-consumption mode in which the entire system operates using only the subclock. when halt mode has been set, the cpu operating clock is stopped so that power consumption can be reduced. when idle mode has been set, the cpu operating clock and some peripheral functions (dmac and bcu) are stopped to enable an even greater reduction in power consumption than when in halt mode.
chapter 4 clock generation function 126 user ? s manual u15109ej3v0ud 4.4.2 halt mode (1) settings and operating states in this mode, the clock oscillator continues to operate but the cpu operating clock is stopped. a clock continues to be supplied for other on-chip peripheral functions to maintain the operation of those functions. when halt mode is set while the cpu is idle, it enables the system ? s total power consumption to be reduced. when in halt mode, execution of programs is stopped but the contents of all registers and on-chip ram are retained as they were just before halt mode was set. in addition, all on-chip peripheral functions that do not depend on instruction processing by the cpu continue operating. halt mode can be set by executing the halt instruction. it can be set when the cpu is operating via either the main clock or subclock. the operating statuses in the halt mode are listed in table 4-1. (2) cancellation of halt mode halt mode can be canceled by an nmi request, an unmasked maskable interrupt request, or reset input. (a) cancellation by interrupt request halt mode is canceled regardless of the priority level when an nmi request or an unmasked maskable interrupt request occurs. however, the following occurs if halt mode was set as part of an interrupt servicing routine. (i) when an interrupt request that has a lower priority level than the interrupt currently being serviced occurs, only halt mode is canceled and the lower-priority interrupt request is not acknowledged. the interrupt request itself is retained. (ii) when an interrupt request (including nmi request) that has a higher priority level than the interrupt currently being serviced occurs, halt mode is canceled and the interrupt request is acknowledged. (b) cancellation by reset pin input this is the same as for normal reset operations.
chapter 4 clock generation function user ? s manual u15109ej3v0ud 127 table 4-1. operating statuses in halt mode (1/2) when cpu operates on main clock when cpu operates on subclock halt mode setting item when subclock does not exist when subclock exists when main clock oscillation continues when main clock oscillation is stopped cpu stopped rom correction stopped clock generator oscillation for main clock and subclock clock supply to cpu is stopped 16-bit timer (tm0) operating operates when intwtni is selected as count clock (f xt is selected for watch timer) 16-bit timer (tm1) operating stopped 16-bit timer (tm5) operates when main clock is selected for count clock operating operates when f xt is selected for count clock 16-bit timer (tm6) operating stopped 16-bit timer (tm7 to tm12) operating stopped watch timer operates when main clock is selected for count clock operating operates when f xt is selected for count clock watchdog timer operating (interval timer only) csi0, csi2 to csi6 operating operates when an external clock is selected as the serial clock i 2 c0, i 2 c1 operating stopped serial interface uart0 to uart3 operating operates when an external clock is selected as the baud rate clock iebus (v850/sc2 only) operating stopped fcan1, fcan2 note (v850/sc3 only) operating stopped a/d converter operating stopped dma0 to dma5 operating port function held external bus interface only bus hold function operates note available only for the pd703089y and 70f3089y.
chapter 4 clock generation function 128 user ? s manual u15109ej3v0ud table 4-1. operating statuses in halt mode (2/2) when cpu operates on main clock when cpu operates on subclock halt mode setting item when subclock does not exist when subclock exists when main clock oscillation continues when main clock oscillation is stopped nmi operating intp0 to intp3, intp7 to intp9 operating intp4 and intp5 operating stopped external interrupt request intp6 operates when main clock is selected for noise eliminator operating operates when f xt is selected for noise eliminator key return function operating ad0 to ad15 high impedance note 1 a1 to a15 note 2 held note 1 (high impedance when hldak = 0) a16 to a21 held note 1 (high impedance when hldak = 0) lben, uben held note 1 (high impedance when hldak = 0) r/w dstb, wrl note 2 , wrh note 2 , rd note 2 astb high-level output note 1 (high impedance when hldak = 0) in external expansion mode hldak operating notes 1. even when the halt instruction has been executed, the instruction fetch operation continues until the on-chip instruction prefetch queue becomes full. once it is full, operation stops in the state shown in table 4-1. 2. only for the v850/sc1 and v850/sc2
chapter 4 clock generation function user ? s manual u15109ej3v0ud 129 4.4.3 idle mode (1) settings and operating states this mode stops the entire system except the watch timer by stopping the on-chip main clock supply while the clock oscillator is still operating. supply to the subclock continues. when this mode is canceled, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. when in idle mode, program execution is stopped and the contents of all registers and internal ram are retained as they were just before idle mode was set. in addition, on-chip peripheral functions are stopped (except for peripheral functions that are operating with the subclock). external bus hold requests (hldrq) are not acknowledged. when the idle bit of the power save control register (psc) is set (1), the system switches to idle mode. the operating statuses in idle mode are listed in table 4-2. (2) cancellation of idle mode idle mode can be canceled by a non-maskable interrupt, an unmasked maskable interrupt request output from an operable on-chip peripheral i/o, or reset input. table 4-2. operating statuses in idle mode (1/2) idle mode settings item when subclock exists when subclock does not exist cpu stopped rom correction stopped clock generator both main clock and subclock oscillating clock supply to cpu and on-chip peripheral functions is stopped 16-bit timer (tm0) operates when intwtni is selected as the count clock (f xt is selected for watch timer) stopped 16-bit timer (tm1) stopped 16-bit timer (tm5) operates when f xt is selected for the count clock stopped 16-bit timer (tm6) stopped 16-bit timer (tm7 to tm12) stopped watch timer operating watchdog timer stopped csi0, csi2 to csi6 operates when an external clock is selected as the serial clock i 2 c0, i 2 c1 stopped serial interfaces uart0 to uart3 operates only for transmission when an external clock is selected as the baud rate clock iebus (v850/sc2 only) stopped fcan1, fcan2 note (v850/sc3 only) stopped a/d converter stopped dma0 to dma5 stopped port function held note available only for the pd703089y, 70f3089y.
chapter 4 clock generation function 130 user?s manual u15109ej3v0ud table 4-2. operating statuses in idle mode (2/2) idle mode settings item when subclock exists when subclock does not exist external bus interface stopped nmi operating intp0 to intp3, intp7 to intp9 operating intp4 and intp5 stopped external interrupt request intp6 operates when f xt is selected for the sampling clock stopped key return function operating ad0 to ad15 high impedance a1 to a15 note held a16 to a21 lben, uben r/w dstb, wrl note , wrh note , rd note astb in external expansion mode hldak high impedance note only for the v850/sc1 and v850/sc2
chapter 4 clock generation function user ? s manual u15109ej3v0ud 131 4.4.4 software stop mode (1) settings and operating states this mode stops the entire system by stopping the main clock oscillator supplying the internal main clock. the subclock oscillator continues operating and the internal subclock supply is continued. when the subclock oscillator is not used, if the frc bit in the processor clock control register (pcc) is set (1), the subclock oscillator ? s on-chip feedback resistor is cut. this sets ultra-low-power-consumption mode, in which the only current is the device ? s leak current. in this mode, program execution is stopped and the contents of all registers and internal ram are retained as they were just before software stop mode was set. on-chip peripheral functions are also stopped (but peripheral functions operating on the subclock are not stopped). the external bus hold request (hldrq) is not acknowledged. this mode can be set only when the main clock is being used as the cpu clock. this mode is set when the stp bit in the power save control register (psc) has been set to 1. do not set this mode when the subclock has been selected as the cpu clock. the operating statuses for software stop mode are listed in table 4-3. caution to reduce the current consumption in software stop mode, make the fcan default settings as follows regardless of whether fcan is used or not. <1> set the gom bit of the cgst register to 1 (set gom = 1, clear gom = 0). <2> set bits smno1 and smno0 of the cgmss register to 01. <3> set the gom bit of the cgst register to 0 (set gom = 0, clear gom = 1). for details of fcan settings, refer to chapter 19 fcan controller. (2) cancellation of software stop mode software stop mode can be canceled by a non-maskable interrupt, an unmasked maskable interrupt request output from an operable on-chip peripheral i/o, or reset input. one oscillation stabilization time is secured when the stop mode is canceled.
chapter 4 clock generation function 132 user ? s manual u15109ej3v0ud table 4-3. operating statuses in software stop mode (1/2) mode settings item when subclock exists when subclock does not exist cpu stopped rom correction stopped clock generator oscillation for main clock is stopped and oscillation for subclock continues clock supply to cpu and on-chip peripheral functions is stopped 16-bit timer (tm0) operates when intwtni is selected for the count clock (f xt is selected as the count clock for the watch timer) stopped 16-bit timer (tm1) stopped 16-bit timer (tm5) operates when f xt is selected for the count clock stopped 16-bit timer (tm6) stopped 16-bit timer (tm7 to tm12) stopped watch timer operates when f xt is selected for the count clock stopped (operation disabled) watchdog timer stopped csi0, csi2 to csi6 operates when an external clock is selected as the serial clock i 2 c0, i 2 c1 stopped serial interfaces uart0 to uart3 operates only for transmission when an external clock is selected as the baud rate clock iebus (v850/sc2 only) stopped fcan1, fcan2 note (v850/sc3 only) stopped a/d converter stopped note available only for the pd703089y and 70f3089y.
chapter 4 clock generation function user ? s manual u15109ej3v0ud 133 table 4-3. operating statuses in software stop mode (2/2) mode settings item when subclock exists when subclock does not exist dma0 to dma5 stopped port function held external bus interface stopped nmi operating intp0 to intp3, intp7 to intp9 operating intp4 and intp5 stopped external interrupt request intp6 operates when f xt is selected for the sampling clock stopped key return function operating ad0 to ad15 high impedance a1 to a15 note held a16 to a21 lben, uben r/w dstb, wrl note , wrh note , rd note astb in external expansion mode hldak high impedance note only for the v850/sc1 and v850/sc2
chapter 4 clock generation function 134 user ? s manual u15109ej3v0ud 4.5 oscillation stabilization time the following shows the methods for specifying the length of the oscillation stabilization time required to stabilize the oscillator following cancellation of stop mode. (1) cancellation by non-maskable interrupt or by unmasked maskable interrupt request stop mode is canceled by a non-maskable interrupt or an unmasked maskable interrupt request. when an interrupt is input, the counter (watchdog timer) starts counting and the count time is the length of time that must elapse until the oscillator ? s clock output stabilizes. the oscillation stabilization time is set by the oscillation stabilization time select register (osts). oscillation stabilization time ? wdt count time after the specified amount of time has elapsed, system clock output starts and processing branches to the interrupt handler address. figure 4-2. oscillation stabilization time stop mode is set oscillator is stopped interrupt input oscillation wave main clock stop status oscillation stabilization time count (2) use of reset pin to allocate time (reset pin input) for allocating time with reset pin, refer to chapter 14 reset function . the oscillation stabilization time is 2 18 /f xx , in accordance with the value of the osts register after reset.
chapter 4 clock generation function user?s manual u15109ej3v0ud 135 4.6 cautions on power save function (1) when executing an instruction on the internal rom to set the power save mode (idle or stop mode) during execution of an instruction on the internal rom, nop instructions must be inserted as dummy instructions to execute the routine after the power save mode is released. the sequence for setting the power save mode is as follows. <1> disable dma operation. <2> disable interrupts (set np bit of psw to 1). <3> write an arbitrary 8-bit data to the command register (prcmd). <4> write the setting data to the psc register (using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> enable interrupts (clear np bit of psw to 0). <6> insert nop instructions (two or five instructions). <7> if dma operation is needed, enable dma operation. cautions 1. insert two nop instructions if the value of the id bit of the psw is not changed by executing the instruction that clears the np bit to 0 (<5>), and if changed, insert five nop instructions (<6>). the following shows an example of description. [description example] ldsr rx,5 ;np bit = 1 st.b r0,prcmd[r0] ;write to prcmd st.b rd,psc[r0] ;set psc register ldsr ry,5 ;np bit = 0 nop ;dummy instructions(2 or 5 instructions) nop (next instruction) ;execution routine after idle/stop mode released remark the above example assumes that rd (psc set value), rx (value to be written to psw), and ry (value rewritten to psw) are already set. to save the psw value, transfer the psw value before setting the np bit to the ry register. 2. the instructions (<5> enable interrupt, <6> nop instruction) following the store instruction (<4>) for the psc register that is used to set idle mode or stop mode are executed before the power save mode is entered.
chapter 4 clock generation function 136 user ? s manual u15109ej3v0ud (2) when executing an instruction on the external rom if the v850/sc1, v850/sc2, and v850/sc3 are used under the following conditions, a discrepancy occurs between the address indicated by the program counter (pc) and the address at which an instruction is actually read after the power save mode is released. this may result in the cpu ignoring a 4- or 8-byte instruction from between 4 bytes and 16 bytes after an instruction is executed to write to the psc register, which could in turn result in the execution of an erroneous instruction. caution a pc discrepancy occurs only when all the conditions (i) to (iii) in [conditions] below are met. it does not occur if even one condition is not met. [conditions] (i) setting of power save mode (idle mode or stop mode) while an instruction is being executed on external rom (ii) cancellation of power save mode as the result of an interrupt request (iii) execution of the next instruction when an interrupt request is held pending following cancellation of the power save mode conditions for interrupt request to be held pending: ? when np flag of psw register is ? 1 ? (nmi servicing in progress/set by software) ? when id flag of psw register is ? 1 ? (interrupt request servicing in progress/di instruction/set by software) ? when an interrupt enable (ei) state occurs during interrupt request servicing, but this state is cleared by an interrupt request with the same or lower priority therefore, use the v850/sc1, v850/sc2, and v850/sc3 under the following conditions. [usage conditions] (i) do not use a power save mode (idle mode or stop mode) during instruction execution on external rom. (ii) if it is necessary to use a power save mode during instruction execution on external rom, implement the following software measures. ? insert 6 nop instructions 4 bytes after an instruction that writes to the psc register. ? after the nop instructions, insert a br$+2 instruction to cancel the pc discrepancy.
chapter 4 clock generation function user ? s manual u15109ej3v0ud 137 [workaround program example] ldsr rx,5 ;sets rx value to psw st.b r0,prcmd[r0] ;writes to prcmd st.b rd,psc[r0] ;sets psc register ldsr ry,5 ;returns psw value nop ;6 or more nop instructions nop nop nop nop nop br $+2 ;cancels pc discrepancy remark it is assumed that rd (psc setting value), rx (value written to psw), and ry (value written back to psw) have been set.
user?s manual u15109ej3v0ud 138 chapter 5 port functions 5.1 port configuration the v850/sc1, v850/sc2, and v850/sc3 include 124 i/o port pins from ports 0 to 15 and 17 (12 port pins are input only). there are six pin i/o buffer power supplies; portv dd0 to portv dd2 , v dd0 , v dd1 , and adcv dd , which are described below. table 5-1. pin i/o buffer power supplies (a) pd70f3089y power supply corresponding pins usable voltage range portv dd0 note 1 p40 to p47, p50 to p57, p60 to p65, p90 to p96, clkout 3.0 v portv dd0 5.5 v portv dd1 note 1 p00 to p03, p10 to p17, p30 to p37, p100 to p107, p110 to p117 3.0 v portv dd1 5.5 v note 2 portv dd2 note 1 p04 to p07, p20 to p27, p120 to p127, p130 to p133, p140 to p147, p150 to p157 3.0 v portv dd2 5.5 v note 2 v dd0 reset when a/d converter not used: 4.0 v v dd0 5.5 v when a/d converter used: 4.5 v v dd0 = adcv dd 5.5 v v dd1 p170 to p176 4.0 v v dd1 5.5 v adcv dd p70 to p77, p80 to p83 when a/d converter not used: 4.0 v adcv dd 5.5 v when a/d converter used: 4.5 v v dd0 = adcv dd 5.5 v notes 1. the electrical specifications differ between an operating frequency of 4 to 17 mhz and an operating frequency of 4 to 20 mhz. 2. when the fcan controller is used: portv dd1 portv dd2 (due to the supply voltage conditions of the in-circuit emulator) caution the conditions for the power supplies are as follows. portv dd0 portv dd1 portv dd2 v dd0 = v dd1 = adcv dd
chapter 5 port functions user?s manual u15109ej3v0ud 139 (b) other than pd70f3089y power supply corresponding pins usable voltage range portv dd0 note 1 p40 to p47, p50 to p57, p60 to p65, p90 to p96, clkout 3.0 v portv dd0 5.5 v portv dd1 note 1 p00 to p03, p10 to p17, p30 to p37, p100 to p107, p110 to p117 3.0 v portv dd1 5.5 v note 2 portv dd2 note 1 p04 to p07, p20 to p27, p120 to p127, p130 to p133, p140 to p147, p150 to p157 3.0 v portv dd2 5.5 v note 2 v dd0 reset when a/d converter not used: 3.5 v v dd0 5.5 v when a/d converter used: 4.5 v v dd0 = adcv dd 5.5 v v dd1 p170 to p176 3.5 v v dd1 5.5 v adcv dd p70 to p77, p80 to p83 when a/d converter not used: 3.5 v adcv dd 5.5 v when a/d converter used: 4.5 v v dd0 = adcv dd 5.5 v notes 1. electrical specifications differ between the cases with operating frequency of 4 to 17 mhz and with operating frequency of 4 to 20 mhz. 2. when fcan controller is used: portv dd1 portv dd2 (due to the supply voltage conditions of the in-circuit emulator) caution the condition for power supplies is as follows. portv dd0 portv dd1 portv dd2 v dd0 = v dd1 = adcv dd
chapter 5 port functions user?s manual u15109ej3v0ud 140 5.2 port pin functions 5.2.1 port 0 port 0 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. when using p00 to p04 as the nmi or intp0 to intp3 pins, noise is eliminated by an analog noise eliminator. when using p05 to p07 as the intp4/adtrg, intp5, and intp6 pins, noise is eliminated by a digital noise eliminator. after reset: 00h r/w address: fffff000h 76543210 p0 p07 p06 p05 p04 p03 p02 p01 p00 p0n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p0 is read, the pin levels at that time are read. writing to p0 writes the values to that port. this does not affect the input pins. in output mode: when p0 is read, the values of p0 are read. writing to p0 writes the values to that port, and those values are immediately output. port 0 includes the following alternate functions. table 5-2. port 0 alternate function pins pin name alternate function i/o pull note remark p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 analog noise elimination p05 intp4/adtrg p06 intp5 port 0 p07 intp6 i/o no digital noise elimination note software pull-up function
chapter 5 port functions user?s manual u15109ej3v0ud 141 (1) function of p0 pins port 0 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 0 mode register (pm0). in output mode, the values set to each bit are output to port 0 (p0). when using this port in output mode, either the valid edge of each interrupt request should be made invalid or each interrupt request should be masked (except for nmi requests). when using this port in input mode, the pin statuses can be read by reading p0. also, the values of p0 (output latch) can be read by reading p0 while in output mode. the valid edges of nmi and intp0 to intp6 are specified via the rising edge specification register 0 (egp0) and the falling edge specification register 0 (egn0). when a reset is input, the settings are initialized to input mode. also, the valid edge of each interrupt request becomes invalid (nmi and intp0 to intp6 do not function immediately after reset). (2) noise elimination (a) elimination of noise from nmi and intp0 to intp3 pins an on-chip noise eliminator is provided that uses analog delay to eliminate noise. consequently, if a signal having a constant level is input for longer than a specified time to these pins, it is detected as a valid edge. edge detection occurs only after the specified amount of time has elapsed. (b) elimination of noise from intp4 to intp6 and adtrg pins a digital noise eliminator is provided on chip. this circuit uses digital sampling. a pin?s input level is detected using a sampling clock (f xx ), and noise elimination is performed for the intp4, intp5, and adtrg pins if the same level is not detected three times consecutively. the noise-elimination width can be changed for the intp6 pin (see 7.3.8 (3) noise elimination of intp6 pin ). cautions 1. if the input pulse width is 2 or 3 clocks, whether it will be detected as a valid edge or eliminated as noise is undetermined. to ensure correct detection of a valid edge, constant-level input is required for 3 clocks or more. 2. if noise is occurring in synchronization with the sampling clock, it may not be recognized as noise. in such cases, attach a filter to the input pins to eliminate the noise. 3. noise elimination is not performed when these pins are used as an ordinary input port pins.
chapter 5 port functions user?s manual u15109ej3v0ud 142 (3) control registers (a) port 0 mode register (pm0) pm0 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff020h 76543210 pm0 pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) rising edge specification register 0 (egp0) egp0 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff0c0h <7> <6> <5> <4> <3> <2> <1> <0> egp0 egp07 egp06 egp05 egp04 egp03 egp02 egp01 egp00 egp0n control of rising edge detection (n = 0 to 7) 0 interrupt request signal does not occur at rising edge 1 interrupt request signal occurs at rising edge remark n = 0: control of nmi pin n = 1 to 7: control of intp0 to intp6 pins
chapter 5 port functions user?s manual u15109ej3v0ud 143 (c) falling edge specification register 0 (egn0) egn0 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff0c2h <7> <6> <5> <4> <3> <2> <1> <0> egn0 egn07 egn06 egn05 egn04 egn03 egn02 egn01 egn00 egn0n control of falling edge detection (n = 0 to 7) 0 interrupt request signal does not occur at falling edge 1 interrupt request signal occurs at falling edge remark n = 0: control of nmi pin n = 1 to 7: control of intp0 to intp6 pins (4) block diagram (port 0) figure 5-1. block diagram of p00 to p07 wr pm wr port rd p00/nmi p01/intp0 p02/intp1 p03/intp2 p04/intp3 p05/intp4/adtrg p06/intp5 p07/intp6 selector output latch (p0n) pm0n pm0 internal bus remarks 1. pm0: port 0 mode register rd: port 0 read signal wr: port 0 write signal 2. n = 0 to 7
chapter 5 port functions user ? s manual u15109ej3v0ud 144 5.2.2 port 1 port 1 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. bits 0 and 2 are selectable as normal outputs or n-ch open-drain outputs. after reset: 00h r/w address: fffff002h 76543210 p1 p17 p16 p15 p14 p13 p12 p11 p10 p1n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p1 is read, the pin levels at that time are read. writing to p1 writes the values to that port. this does not affect the input pins. in output mode: when p1 is read, the values of p1 are read. writing to p1 writes the values to that port, and those values are immediately output. port 1 includes the following alternate functions. table 5-3. port 1 alternate function pins pin name alternate function i/o pull note remark p10 si0/sda0 selectable as n-ch open-drain output p11 so0 ? p12 sck0/scl0 selectable as n-ch open-drain output p13 si4/rxd0 p14 so4/txd0 p15 sck4/asck0 p16 ? port 1 p17 ti5/to5 i/o no ? note software pull-up function
chapter 5 port functions user ? s manual u15109ej3v0ud 145 (1) function of p1 pins port 1 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 1 mode register (pm1). in output mode, the values set to each bit are output to port 1 (p1). the port 1 function register (pf1) can be used to specify whether p10 and p12 are normal outputs or n-ch open-drain outputs. when using this port in input mode, the pin statuses can be read by reading p1. also, the values of p1 (output latch) can be read by reading p1 while in output mode. clear p1 and the pm1 register to 0 when using alternate-function pins as outputs. the logical sum (ored result) of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 1 mode register (pm1) pm1 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff022h 76543210 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) port 1 function register (pf1) pf1 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff0a2h 76543210 pf1 00000pf120pf10 pf1n control of normal output/n-ch open-drain output (n = 0, 2) 0 normal output 1 n-ch open-drain output
chapter 5 port functions user ? s manual u15109ej3v0ud 146 (3) block diagram (port 1) figure 5-2. block diagram of p10 and p12 wr pm wr pf wr port rd v dd selector pf1n pf1 pm1n pm1 p-ch n-ch internal bus output latch (p1n) alternate function p10/si0/sda0 p12/sck0/scl0 remarks 1. pf1: port 1 function register pm1: port 1 mode register rd: port 1 read signal wr: port 1 write signal 2. n = 0, 2
chapter 5 port functions user ? s manual u15109ej3v0ud 147 figure 5-3. block diagram of p11, p13 to p15, and p17 wr pm wr port rd selector output latch (p1n) pm1n pm1 internal bus alternate function p11/so0 p13/si4/rxd0 p14/so4/txd0 p15/sck4/asck0 p17/ti5/to5 remarks 1. pm1: port 1 mode register rd: port 1 read signal wr: port 1 write signal 2. n = 1, 3 to 5, 7
chapter 5 port functions user ? s manual u15109ej3v0ud 148 figure 5-4. block diagram of p16 wr pm wr port rd selector output latch (p16) pm16 pm1 internal bus p16 remark pm1: port 1 mode register rd: port 1 read signal wr: port 1 write signal
chapter 5 port functions user ? s manual u15109ej3v0ud 149 5.2.3 port 2 port 2 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. bits 0 and 2 are selectable as normal outputs or n-ch open-drain outputs. after reset: 00h r/w address: fffff004h 76543210 p2 p27 p26 p25 p24 p23 p22 p21 p20 p2n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p2 is read, the pin levels at that time are read. writing to p2 writes the values to that port. this does not affect the input pins. in output mode: when p2 is read, the values of p2 are read. writing to p2 writes the values to that port, and those values are immediately output. port 2 includes the following alternate functions. table 5-4. port 2 alternate function pins pin name alternate function i/o pull note 1 remark p20 si2/sda1 selectable as n-ch open-drain output p21 so2 ? p22 sck2/sck1 selectable as n-ch open-drain output p23 ti90 p24 ti91 p25 to90 p26 ierx0 note 2 port 2 p27 ietx0 note 2 i/o no ? notes 1. software pull-up function 2. only for the v850/sc2
chapter 5 port functions user ? s manual u15109ej3v0ud 150 (1) function of p2 pins port 2 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 2 mode register (pm2). in output mode, the values set to each bit are output to port 2 (p2). also, p20 and p22 are selectable as normal outputs or n-ch open-drain outputs using the port 2 function register (pf2). when using this port in input mode, the pin statuses can be read by reading p2. also, the values of p2 (output latch) can be read by reading p2 while in output mode. clear p2 and the pm2 register to 0 when using alternate-function pins as outputs. the logical sum (ored result) of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 2 mode register (pm2) pm2 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff024h 76543210 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) port 2 function register (pf2) pf2 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff0a4h 76543210 pf2 00000pf220pf20 pf2n control of normal output/n-ch open-drain output (n = 0, 2) 0 normal output 1 n-ch open-drain output
chapter 5 port functions user ? s manual u15109ej3v0ud 151 (3) block diagram (port 2) figure 5-5. block diagram of p20 and p22 wr pm wr pf wr port rd v dd selector pf2n pf2 pm2n pm2 p-ch n-ch internal bus output latch (p2n) alternate function p20/si2/sda1 p22/sck2/scl1 remarks 1. pf2: port 2 function register pm2: port 2 mode register rd: port 2 read signal wr: port 2 write signal 2. n = 0, 2
chapter 5 port functions user ? s manual u15109ej3v0ud 152 figure 5-6. block diagram of p21 and p23 to p27 wr pm wr port rd selector output latch (p2n) pm2n pm2 internal bus alternate function p21/so2 p23/ti90 p24/ti91 p25/to90 p26/ierx0 note p25/ietx0 note note only for the v850/sc2 remarks 1. pm2: port 2 mode register rd: port 2 read signal wr: port 2 write signal 2. n = 1, 3 to 7
chapter 5 port functions user ? s manual u15109ej3v0ud 153 5.2.4 port 3 port 3 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. when using p35 to p37 as the intp7 to intp9 pins, noise is eliminated by an analog eliminator. after reset: 00h r/w address: fffff006h 76543210 p3 p37 p36 p35 p34 p33 p32 p31 p30 p3n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p3 is read, the pin levels at that time are read. writing to p3 writes the values to that port. this does not affect the input pins. in output mode: when p3 is read, the values of p3 are read. writing to p3 writes the values to that port, and those values are immediately output. port 3 includes the following alternate functions. table 5-5. port 3 alternate function pins pin name alternate function i/o pull note 1 remark p30 ti6/to6 p31 ti80 p32 ti81 p33 to8 p34 ti71/a13 note 2 ? p35 intp7/a14 note 2 p36 intp8/a15 note 2 port 3 p37 intp9 i/o no analog noise elimination notes 1. software pull-up function 2. only for the v850/sc1 and v850/sc2
chapter 5 port functions user ? s manual u15109ej3v0ud 154 (1) function of p3 pins port 3 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 3 mode register (pm3). in output mode, the values set to each bit are output to port 3 (p3). when using this port in input mode, the pin statuses can be read by reading p3. also, the values of p3 (output latch) can be read by reading p3 while in output mode. when using the alternate-function intp7 to intp9 pins, noise is eliminated by the analog noise eliminator (the same as the analog noise eliminator for port 0). the valid edge for the intp7 to intp9 pins is specified by the rising edge specification register 1 (egp1) and falling edge specification register 1 (egn1). when using the alternate-function a13 to a15 pins, set this port via the memory address output mode register (mam). clear p3 and the pm3 register to 0 when using alternate-function pins as outputs. the logical sum (ored result) of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. also, the valid edge of each interrupt request becomes invalid (intp7 to intp9 do not function immediately after reset). (2) control registers (a) port 3 mode register (pm3) pm3 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff026h 76543210 pm3 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode
chapter 5 port functions user ? s manual u15109ej3v0ud 155 (b) rising edge specification register 1 (egp1) egp1 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff0c4h <7><6><5>43210 egp1 egp17 egp16 egp15 0 0 0 0 0 egp1n control of rising edge detection (n = 5 to 7) 0 interrupt request signal does not occur at rising edge 1 interrupt request signal occurs at rising edge remark n = 5 to 7: control of intp7 to intp9 pins (c) falling edge specification register 1 (egn1) egn1 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff0c6h <7><6><5>43210 egn1 egn17 egn16 egn15 0 0 0 0 0 egn1n control of falling edge detection (n = 5 to 7) 0 interrupt request signal does not occur at falling edge 1 interrupt request signal occurs at falling edge remark n = 5 to 7: control of intp7 to intp9 pins
chapter 5 port functions user ? s manual u15109ej3v0ud 156 (3) block diagram (port 3) figure 5-7. block diagram of p30 to p37 wr pm wr port rd selector output latch (p3n) pm3n pm3 internal bus alternate function p30/ti6/to6 p31/ti80 p32/ti81 p33/to8 p34/ti71/a13 note p35/intp7/a14 note p36/intp8/a15 note p37/intp9 note only for the v850/sc1 and v850/sc2 remarks 1. pm3: port 3 mode register rd: port 3 read signal wr: port 3 write signal 2. n = 0 to 7
chapter 5 port functions user ? s manual u15109ej3v0ud 157 5.2.5 ports 4 and 5 ports 4 and 5 are 8-bit i/o ports for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff008h, fffff00ah 76543210 pn pn7 pn6 pn5 pn4 pn3 pn2 pn1 pn0 (n = 4, 5) pnx control of output data (in output mode) (n = 4, 5, x = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p4 and p5 are read, the pin levels at that time are read. writing to p4 and p5 writes the values to those ports. this does not affect the input pins. in output mode: when p4 and p5 are read, their values are read. writing to p4 and p5 writes the values to those ports, and those values are immediately output. ports 4 and 5 include the following alternate functions. table 5-6. alternate function pins of ports 4 and 5 pin name alternate function i/o pull note remark p40 ad0 p41 ad1 p42 ad2 p43 ad3 p44 ad4 p45 ad5 p46 ad6 port 4 p47 ad7 i/o no ? p50 ad8 p51 ad9 p52 ad10 p53 ad11 p54 ad12 p55 ad13 p56 ad14 port 5 p57 ad15 i/o no ? note software pull-up function
chapter 5 port functions user ? s manual u15109ej3v0ud 158 (1) functions of p4 and p5 pins ports 4 and 5 are 8-bit i/o ports for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via port 4 mode register (pm4) and port 5 mode register (pm5). in output mode, the values set to each bit are output to port 4 and port 5 (p4 and p5). when using these ports in input mode, the pin statuses can be read by reading p4 and p5. also, the values of p4 and p5 (output latch) can be read by reading p4 and p5 while in output mode. a software pull-up function is not implemented. when using the alternate-function ad0 to ad15 pins, set the pin functions via the memory expansion mode register (mm). this does not affect the pm4 and pm5 registers. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 4 mode register and port 5 mode register (pm4 and pm5) pm4 and pm5 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff028h, fffff02ah 76543210 pmn pmn7 pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 (n = 4, 5) pmnx control of i/o mode (n = 4, 5, x = 0 to 7) 0 output mode 1 input mode
chapter 5 port functions user ? s manual u15109ej3v0ud 159 (3) block diagram (ports 4 and 5) figure 5-8. block diagram of p40 to p47 and p50 to p57 wr pm wr port rd selector output latch (pmn) pmmn pmm internal bus pmn/adx remarks 1. pmm: port m mode register rd: port m read signal wr: port m write signal 2. m = 4, 5 n = 0 to 7 x = 0 to 15
chapter 5 port functions user ? s manual u15109ej3v0ud 160 5.2.6 port 6 port 6 is a 6-bit i/o port for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff00ch 76543210 p6 0 0 p65 p64 p63 p62 p61 p60 p6n control of output data (in output mode) (n = 0 to 5) 0 outputs 0 1 outputs 1 remark in input mode: when p6 is read, the pin levels at that time are read. writing to p6 writes the values to that port. this does not affect the input pins. in output mode: when p6 is read, the values of p6 are read. writing to p6 writes the values to that port, and those values are immediately output. port 6 includes the following alternate functions. table 5-7. port 6 alternate function pins pin name alternate function i/o pull note remark p60 a16 p61 a17 p62 a18 p63 a19 p64 a20 port 6 p65 a21 i/o no ? note software pull-up function
chapter 5 port functions user ? s manual u15109ej3v0ud 161 (1) function of p6 pins port 6 is a 6-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 6 mode register (pm6). in output mode, the values set to each bit are output to port 6 (p6). when using this port in input mode, the pin statuses can be read by reading p6. also, the values of p6 (output latch) can be read by reading p6 while in output mode. a software pull-up function is not implemented. when using the alternate-function a16 to a21 pins, set the pin functions via the memory expansion mode register (mm). this does not affect the pm6 register. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 6 mode register (pm6) pm6 can be read/written in 8- or 1-bit units. after reset: 3fh r/w address: fffff02ch 76543210 pm6 0 0 pm65 pm64 pm63 pm62 pm61 pm60 pm6n control of i/o mode (n = 0 to 5) 0 output mode 1 input mode
chapter 5 port functions user ? s manual u15109ej3v0ud 162 (3) block diagram (port 6) figure 5-9. block diagram of p60 to p65 wr pm wr port rd selector output latch (p6n) pm6n pm6 internal bus p6n/ax remarks 1. pm6: port 6 mode register rd: port 6 read signal wr: port 6 write signal 2. n = 0 to 5 x = 16 to 21
chapter 5 port functions user ? s manual u15109ej3v0ud 163 5.2.7 ports 7 and 8 port 7 is an 8-bit input port and port 8 is a 4-bit input port. both ports are read-only and are accessible in 8- or 1- bit units. after reset: undefined r address: fffff00eh 76543210 p7 p77 p76 p75 p74 p73 p72 p71 p70 p7n pin level (n = 0 to 7) 0/1 read pin level of bit n after reset: undefined r address: fffff010h 76543210 p8 0 0 0 0 p83 p82 p81 p80 p8n pin level (n = 0 to 3) 0/1 read pin level of bit n ports 7 and 8 include the following alternate functions. table 5-8. alternate function pins of ports 7 and 8 pin name alternate function i/o pull note remark p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 port 7 p77 ani7 input no ? p80 ani8 p81 ani9 p82 ani10 port 8 p83 ani11 input no ? note software pull-up function
chapter 5 port functions user ? s manual u15109ej3v0ud 164 (1) functions of p7 and p8 pins port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. the pin statuses can be read by reading port 7 and port 8 (p7 and p8). data cannot be written to p7 or p8. a software pull-up function is not implemented. values read from pins specified as analog inputs are undefined values. do not read values from p7 or p8 during a/d conversion. (2) block diagram (ports 7 and 8) figure 5-10. block diagram of p70 to p77 and p80 to p83 pmn/anix rd internal bus remarks 1. rd: port 7, port 8 read signals 2. m = 7, 8 n = 0 to 7 (m = 7), 0 to 3 (m = 8) x = 0 to 7 (m = 7), 8 to 11 (m = 8)
chapter 5 port functions user ? s manual u15109ej3v0ud 165 5.2.8 port 9 port 9 is a 7-bit i/o port for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff012h 76543210 p9 0 p96 p95 p94 p93 p92 p91 p90 p9n control of output data (in output mode) (n = 0 to 6) 0 outputs 0 1 outputs 1 remark in input mode: when p9 is read, the pin levels at that time are read. writing to p9 writes the values to that port. this does not affect the input pins. in output mode: when p9 is read, the values of p9 are read. writing to p9 writes the values to that port, and those values are immediately output. port 9 includes the following alternate functions. table 5-9. port 9 alternate function pins pin name alternate function i/o pull note 1 remark p90 lben/wrl note 2 p91 uben p92 r/w/wrh note 2 p93 dstb/rd note 2 p94 astb p95 hldak port 9 p96 hldrq i/o no ? notes 1. software pull-up function 2. only for the v850/sc1 and v850/sc2
chapter 5 port functions user ? s manual u15109ej3v0ud 166 (1) function of p9 pins port 9 is a 7-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 9 mode register (pm9). in output mode, the values set to each bit are output to port 9 (p9). when using this port in input mode, the pin statuses can be read by reading p9. also, the values of p9 (output latch) can be read by reading p9 while in output mode. a software pull-up function is not implemented. when using p9 for control signals in expansion mode, set the pin functions via the memory expansion mode register (mm). when a reset is input, the settings are initialized to input mode. caution in the v850/sc1 and v850/sc2, when using port 9 as an i/o port, set the bic bit of the system control register (syc) to 0. note that the bic bit is 0 after system reset. (2) control register (a) port 9 mode register (pm9) pm9 can be read/written in 8- or 1-bit units. after reset: 7fh r/w address: fffff032h 76543210 pm9 0 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm9n control of i/o mode (n = 0 to 6) 0 output mode 1 input mode
chapter 5 port functions user ? s manual u15109ej3v0ud 167 (3) block diagram (port 9) figure 5-11. block diagram of p90 to p96 wr pm wr port rd selector output latch (p9n) pm9n pm9 internal bus p90/lben/wrl note p91/uben p92/r/w/wrh note p93/dstb/rd note p94/astb p95/hldak p96/hldrq note only for the v850/sc1 and v850/sc2 remarks 1. pm9: port 9 mode register rd: port 9 read signal wr: port 9 write signal 2. n = 0 to 6
chapter 5 port functions user ? s manual u15109ej3v0ud 168 5.2.9 port 10 port 10 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. pull-up resistors can be connected in 1-bit units (software pull-up function). when using p100 to p107 as the kr0 to kr7 pins, noise is eliminated by an analog noise eliminator. after reset: 00h r/w address: fffff014h 76543210 p10 p107 p106 p105 p104 p103 p102 p101 p100 p10n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p10 is read, the pin levels at that time are read. writing to p10 writes the values to that port. this does not affect the input pins. in output mode: when p10 is read, the values of p10 are read. writing to p10 writes the values to that port, and those values are immediately output. port 10 includes the following alternate functions. table 5-10. port 10 alternate function pins pin name alternate function i/o pull note 1 remark p100 kr0/to7/a5 note 2 p101 kr1/ti70/a6 note 2 p102 kr2/ti00/a7 note 2 p103 kr3/ti01/a8 note 2 p104 kr4/to0/a9 note 2 p105 kr5/ti10/a10 note 2 p106 kr6/ti11/a11 note 2 port 10 p107 kr7/to1/a12 note 2 i/o yes analog noise elimination notes 1. software pull-up function 2. only for the v850/sc1 and v850/sc2
chapter 5 port functions user ? s manual u15109ej3v0ud 169 (1) function of p10 pins port 10 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 10 mode register (pm10). in output mode, the values set to each bit are output to port 10 (p10). when using this port in input mode, the pin statuses can be read by reading p10. also, the values of p10 (output latch) can be read by reading p10 while in output mode. pull-up resistors can be connected in 1-bit units when specified via pull-up resistor option register 10 (pu10). when used as kr0 to kr7 pins, noise is eliminated by the analog noise eliminator. when used as the a5 to a12 pins in the case of the v850/sc1 and v850/asc2, this port is set via the memory address output mode register (mam). clear p10 and the pm10 register to 0 when using alternate-function pins as outputs. the logical sum (ored result) of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 10 mode register (pm10) pm10 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff034h 76543210 pm10 pm107 pm106 pm105 pm104 pm103 pm102 pm101 pm100 pm10n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) pull-up resistor option register 10 (pu10) pu10 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff094h 76543210 pu10 pu107 pu106 pu105 pu104 pu103 pu102 pu101 pu100 pu10n control of on-chip pull-up resistor connection (n = 0 to 7) 0 do not connect 1 connect
chapter 5 port functions user ? s manual u15109ej3v0ud 170 (3) block diagram (port 10) figure 5-12. block diagram of p100 to p107 p-ch wr pm wr port rd wr pu v dd selector pm10n pm10 pu10n pu10 internal bus output latch (p10n) alternate function p100/kr0/to7/a5 note p101/kr1/ti70/a6 note p102/kr2/ti00/a7 note p103/kr3/ti01/a8 note p104/kr4/to0/a9 note p105/kr5/ti10/a10 note p106//kr6/ti11/a11 note p107/kr7/to1/a12 note note only for the v850/sc1 and v850/sc2 remarks 1. pu10: pull-up resistor option register 10 pm10: port 10 mode register rd: port 10 read signal wr: port 10 write signal 2. n = 0 to 7
chapter 5 port functions user?s manual u15109ej3v0ud 171 5.2.10 port 11 port 11 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. p11 can be read/written in 8- or 1-bit units. turning on and off the wait function and setting use as the cantx1, canrx1, cantx2, and canrx2 pins can be performed via the port alternate-function control register (pac) (cantx2 and canrx2 are available only for the pd703089y and 70f3089y). after reset: 00h r/w address: fffff016h 76543210 p11 p117 p116 p115 p114 p113 p112 p111 p110 p11n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p11 is read, the pin levels at that time are read. writing to p11 writes the values to that port. this does not affect the input pins. in output mode: when p11 is read, the values of p11 are read. writing to p11 writes the values to that port, and those values are immediately output. port 11 includes the following alternate functions. table 5-11. port 11 alternate function pins pin name alternate function i/o pull note 1 remark p110 wait/a1 note 2 p111 a2 note 2 p112 a3 note 2 p113 a4 note 2 p114 cantx1 note 3 p115 canrx1 note 3 p116 cantx2 note 4 port 11 p117 canrx2 note 4 i/o no ? notes 1. software pull-up function 2. only for the v850/sc1 and v850/sc2 3. only for the v850/sc3 4. only for the pd703089y and 70f3089y
chapter 5 port functions user?s manual u15109ej3v0ud 172 (1) function of p11 pins port 11 is an 8-bit port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 11 mode register (pm11). in output mode, the values set to each bit are output to port 11 (p11). when using this port in input mode, the pin statuses can be read by reading p11. also, the values of p11 (output latch) can be read by reading p11 while in output mode. turning on and off the wait function and setting use as the cantx1, canrx1, cantx2, and canrx2 pins can be performed via the port-alternate function control register (pac). when used as the a1 to a4 pins in the case of v850/sc1 and v850/sc2, this port is set via the memory address output mode register (mam). in this case, be sure to set the pm11 register (pm110 to pm113) and p11 (p110 to p113) to 0. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 11 mode register (pm11) pm11 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff036h 76543210 pm11 pm117 pm116 pm115 pm114 pm113 pm112 pm111 pm110 pm11n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode
chapter 5 port functions user?s manual u15109ej3v0ud 173 (b) port alternate-function control register (pac) pac can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff040h 7654321<0> pac pac117 note pac116 note pac115 pac114 0 0 0 wac wac control of wait function 0 wait function off 1 wait function on pac11n control of port alternate function (n = 4 to 7) 0 port function 1 alternate function note bits pac117 and pac116 are available only for the pd703089y and 70f3089y. set bits 7 and 6 to 0 when using the pd703088y.
chapter 5 port functions user?s manual u15109ej3v0ud 174 (3) block diagram (port 11) figure 5-13. block diagram of p110 and p114 to p117 rd wr port wr pm output latch (p11n) pm11n pm11 pac11m, wac pac selector p110/wait/a note 1 p114/cantx1 note 2 p115/canrx1 note 2 p116/cantx2 note 3 p117/canrx2 note 3 alternate function selector internal bus notes 1. only for the v850/sc1 and v850/sc2 2. only for the v850/sc3 3. only for the pd703089y and 70f3089y remarks 1. pm11: port 11 mode register rd: port 11 read signal wr: port 11 write signal pac: port alternate-function control register (pac) 2. n = 0, 4 to 7 m = 4 to 7
chapter 5 port functions user ? s manual u15109ej3v0ud 175 figure 5-14. block diagram of p111 to p113 wr pm wr port rd selector output latch (p11n) pm11n pm11 internal bus p111/a2 note p113/a4 note alternate function note only for the v850/sc1 and v850/sc2 remarks 1. pm11: port 11 mode register rd: port 11 read signal wr: port 11 write signal 2. n = 1 to 3
chapter 5 port functions user ? s manual u15109ej3v0ud 176 5.2.11 port 12 port 12 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. p12 can be read/written in 8- or 1-bit units. when using this port as the sck5, si5, so5, sck6, si6, and so6 pins, set via port alternate-function control register 2 (pac2). after reset: 00h r/w address: fffff018h 76543210 p12 p127 p126 p125 p124 p123 p122 p121 p120 p12n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p12 is read, the pin levels at that time are read. writing to p12 writes the values to that port. this does not affect the input pins. in output mode: when p12 is read, the values of p12 are read. writing to p12 writes the values to that port, and those values are immediately output. port 12 includes the following alternate functions. table 5-12. port 12 alternate function pins pin name alternate function i/o pull note remark p120 sck5 p121 si5 p122 so5 p123 sck6 p124 si6 p125 so6 p126 to10 port 12 p127 to11 i/o no ? note software pull-up function
chapter 5 port functions user ? s manual u15109ej3v0ud 177 (1) function of p12 pins port 12 is an 8-bit port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 12 mode register (pm12). in output mode, the values set to each bit are output to port 12 (p12). when using this port in input mode, the pin statuses can be read by reading p12. also, the values of p12 (output latch) can be read by reading p12 while in output mode. when using this port as the sck5, si5, so5, sck6, si6, and so6 pins, set via port alternate-function control register 2 (pac2). when using this port as the to10 and to11 pins, set p126, p127, pm126, and pm127 to 0. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 12 mode register (pm12) pm12 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff038h 76543210 pm12 pm127 pm126 pm125 pm124 pm123 pm122 pm121 pm120 pm12n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) port alternate-function control register 2 (pac2) pac2 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff042h 76543210 pac2 0 0 pac125 pac124 pac123 pac122 pac121 pac120 pac12n control of port alternate function (n = 0 to 5) 0 port function 1 alternate function
chapter 5 port functions user ? s manual u15109ej3v0ud 178 (3) block diagram (port 12) figure 5-15. block diagram of p120 to p125 rd wr port wr pm output latch (p12n) pm12n pm12 pac12n pac2 selector alternate function selector internal bus remarks 1. pm12: port 12 mode register rd: port 12 read signal wr: port 12 write signal pac2: port alternate-function control register 2 2. n = 0 to 5
chapter 5 port functions user ? s manual u15109ej3v0ud 179 figure 5-16. block diagram of p126 and p127 wr pm wr port rd selector output latch (p12n) pm12n alternate function pm12 internal bus p126/to10 p127/to11 remarks 1. pm12: port 12 mode register rd: port 12 read signal wr: port 12 write signal 2. n = 6, 7
chapter 5 port functions user ? s manual u15109ej3v0ud 180 5.2.12 port 13 port 13 is a 4-bit i/o port for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff01ah 76543210 p13 0 0 0 0 p133 p132 p131 p130 p13n control of output data (in output mode) (n = 0 to 3) 0 outputs 0 1 outputs 1 remark in input mode: when p13 is read, the pin levels at that time are read. writing to p13 writes the values to that port. this does not affect the input pins. in output mode: when p13 is read, the values of p13 are read. writing to p13 writes the values to that port, and those values are immediately output. (1) function of p13 pins port 13 is a 4-bit port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 13 mode register (pm13). in output mode, the values set to each bit are output to port 13 (p13). when using this port in input mode, the pin statuses can be read by reading p13. also, the values of p13 (output latch) can be read by reading p13 while in output mode. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 13 mode register (pm13) pm13 can be read/written in 8- or 1-bit units. after reset: 0fh r/w address: fffff03ah 76543210 pm13 0 0 0 0 pm133 pm132 pm131 pm130 pm13n control of i/o mode (n = 0 to 3) 0 output mode 1 input mode
chapter 5 port functions user ? s manual u15109ej3v0ud 181 (3) block diagram (port 13) figure 5-17. block diagram of p130 to p133 wr pm wr port rd p130 p131 p132 p133 selector output latch (p13n) pm13n pm13 internal bus remarks 1. pm13: port 13 mode register rd: port 13 read signal wr: port 13 write signal 2. n = 0 to 3
chapter 5 port functions user ? s manual u15109ej3v0ud 182 5.2.13 port 14 port 14 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff01ch 76543210 p14 p147 p146 p145 p144 p143 p142 p141 p140 p14n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p14 is read, the pin levels at that time are read. writing to p14 writes the values to that port. this does not affect the input pins. in output mode: when p14 is read, the values of p14 are read. writing to p14 writes the values to that port, and those values are immediately output. port 14 includes the following alternate functions. table 5-13. port 14 alternate function pins pin name alternate function i/o pull note remark p140 si3/rxd1 p141 so3/txd1 p142 sck3/asck1 p143 rxd2 p144 txd2 p145 asck2 p146 ti100 port 14 p147 ti101 i/o no ? note software pull-up function
chapter 5 port functions user ? s manual u15109ej3v0ud 183 (1) function of p14 pins port 14 is an 8-bit port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 14 mode register (pm14). in output mode, the values set to each bit are output to port 14 (p14). when using this port in input mode, the pin statuses can be read by reading p14. also, the values of p14 (output latch) can be read by reading p14 while in output mode. clear p14 and the pm14 register to 0 when using alternate-function pins as outputs. the logical sum (ored result) of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 14 mode register (pm14) pm14 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff03ch 76543210 pm14 pm147 pm146 pm145 pm144 pm143 pm142 pm141 pm140 pm14n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode
chapter 5 port functions user ? s manual u15109ej3v0ud 184 figure 5-18. block diagram of p140 to p147 wr pm wr port rd selector output latch (p14n) pm14n pm14 internal bus alternate function p140/si3/rxd1 p141/so3/txd1 p142/sck3/asck1 p143/rxd2 p144/txd2 p145/asck2 p146/ti100 p147/ti101 remarks 1. pm14: port 14 mode register rd: port 14 read signal wr: port 14 write signal 2. n = 0 to 7
chapter 5 port functions user ? s manual u15109ej3v0ud 185 5.2.14 port 15 port 15 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff01eh 76543210 p15 p157 p156 p155 p154 p153 p152 p151 p150 p15n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p15 is read, the pin levels at that time are read. writing to p15 writes the values to that port. this does not affect the input pins. in output mode: when p15 is read, the values of p15 are read. writing to p15 writes the values to that port, and those values are immediately output. port 15 includes the following alternate functions. table 5-14. port 15 alternate function pins pin name alternate function i/o pull note remark p150 rxd3 p151 txd3 p152 asck3 p153 ti110 p154 ti111 p155 to12 p156 ti120 port 15 p157 ti121 i/o no ? note software pull-up function
chapter 5 port functions user ? s manual u15109ej3v0ud 186 (1) function of p15 pins port 15 is an 8-bit port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 15 mode register (pm15). in output mode, the values set to each bit are output to port 15 (p15). when using this port in input mode, the pin statuses can be read by reading p15. also, the values of p15 (output latch) can be read by reading p15 while in output mode. clear p15 and the pm15 register to 0 when using alternate-function pins as outputs. the logical sum (ored result) of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 15 mode register (pm15) pm15 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff03eh 76543210 pm15 pm157 pm156 pm155 pm154 pm153 pm152 pm151 pm150 pm15n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode
chapter 5 port functions user ? s manual u15109ej3v0ud 187 (3) block diagram (port 15) figure 5-19. block diagram of p150 to p157 wr pm wr port rd selector output latch (p15n) pm15n pm15 internal bus alternate function p150/rxd3 p151/txd3 p152/asck3 p153/ti110 p154/ti111 p155/to12 p156/ti120 p157/ti121 remarks 1. pm15: port 15 mode register rd: port 15 read signal wr: port 15 write signal 2. n = 0 to 7
chapter 5 port functions user ? s manual u15109ej3v0ud 188 5.2.15 port 17 port 17 is a 7-bit i/o port for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff048h 76543210 p17 0 p176 p175 p174 p173 p172 p171 p170 p17n control of output data (in output mode) (n = 0 to 6) 0 outputs 0 1 outputs 1 remark in input mode: when p17 is read, the pin levels at that time are read. writing to p17 writes the values to that port. this does not affect the input pins. in output mode: when p17 is read, the values of p17 are read. writing to p17 writes the values to that port, and those values are immediately output. port 17 includes the following alternate functions. table 5-15. port 17 alternate function pins pin name alternate function i/o pull note remark p170 ? p171 ? p172 ? p173 ? p174 ? p175 ? port 17 p176 vm45 i/o no ? note software pull-up function
chapter 5 port functions user ? s manual u15109ej3v0ud 189 (1) function of p17 pins port 17 is a 7-bit port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 17 mode register (pm17). in output mode, the values set to each bit are output to port 17 (p17). when using this port in input mode, the pin statuses can be read by reading p17. also, the values of p17 (output latch) can be read by reading p17 while in output mode. when using this port as the vm45 pin, set via the vm45 control register (vm45c). in this case, be sure to set p176 and pm176 to 0. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 17 mode register (pm17) pm17 can be read/written in 8- or 1-bit units. after reset: 7fh r/w address: fffff058h 76543210 pm17 0 pm176 pm175 pm174 pm173 pm172 pm171 pm170 pm17n control of i/o mode (n = 0 to 6) 0 output mode 1 input mode
chapter 5 port functions user ? s manual u15109ej3v0ud 190 (3) block diagram (port 17) figure 5-20. block diagram of p170 to p175 wr pm wr port rd selector output latch (p17n) pm17n pm17 internal bus p170 p171 p172 p173 p174 p175 remarks 1. pm17: port 17 mode register rd: port 17 read signal wr: port 17 write signal 2. n = 0 to 5
chapter 5 port functions user ? s manual u15109ej3v0ud 191 figure 5-21. block diagram of p176 wr pm wr port rd selector output latch (p176) pm176 pm17 internal bus alternate function p176/vm45 remark pm17: port 17 mode register rd: port 17 read signal wr: port 17 write signal
chapter 5 port functions user ? s manual u15109ej3v0ud 192 5.3 setting when port pin is used for alternate function when a port pin is used for an alternate function, set the port n mode register (pm0 to pm6, pm9 to pm12, pm14, pm15, and pm17) and output latch as shown in table 5-16 below. table 5-16. setting when port pin is used for alternate function (1/6) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) p00 nmi input pm00 = 1 setting not needed for p00 ? p01 intp0 input pm01 = 1 setting not needed for p01 ? p02 intp1 input pm02 = 1 setting not needed for p02 ? p03 intp2 input pm03 = 1 setting not needed for p03 ? p04 intp3 input pm04 = 1 setting not needed for p04 ? intp4 input p05 adtrg input pm05 = 1 setting not needed for p05 ? p06 intp5 input pm06 = 1 setting not needed for p06 ? p07 intp6 input pm07 = 1 setting not needed for p07 ? si0 input pm10 = 1 setting not needed for p10 ? p10 sda0 i/o pm10 = 0 p10 = 0 pf10 = 1 p11 so0 output pm11 = 0 p11 = 0 ? input pm12 = 1 setting not needed for p12 sck0 output ? p12 scl0 i/o pm12 = 0 p12 = 0 pf12 = 1 si4 input p13 rxd0 input pm13 = 1 setting not needed for p13 ? so4 output p14 txd0 output pm14 = 0 p14 = 0 ? input pm15 = 1 setting not needed for p15 sck4 output pm15 = 0 p15 = 0 p15 asck0 input pm15 = 1 setting not needed for p15 ? ti5 input pm17 = 1 setting not needed for p17 p17 to5 output pm17 = 0 p17 = 0 ?
chapter 5 port functions user ? s manual u15109ej3v0ud 193 table 5-16. setting when port pin is used for alternate function (2/6) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) si2 input pm20 = 1 setting not needed for p20 ? p20 sda1 i/o pm20 = 0 p20 = 0 pf20 = 1 p21 so2 output pm21 = 0 p21 = 0 ? input pm22 = 1 setting not needed for p22 sck2 output ? p22 scl1 i/o pm22 = 0 p22 = 0 pf22 = 1 p23 ti90 input pm23 = 1 setting not needed for p23 ? p24 ti91 input pm24 = 1 setting not needed for p24 ? p25 to9 output pm25 = 0 p25 = 0 ? p26 ierx0 note 1 input pm26 = 1 setting not needed for p26 ? p27 ietx0 note 1 output pm27 = 0 p27 = 0 ? ti6 input pm30 = 1 setting not needed for p30 p30 to6 output pm30 = 0 p30 = 0 ? p31 ti80 input pm31 = 1 setting not needed for p31 ? p32 ti81 input pm32 = 1 setting not needed for p32 ? p33 to8 output pm33 = 0 p33 = 0 ? ti71 input pm34 = 1 setting not needed for p34 ? p34 a13 note 2 output pm34 = 0 p34 = 0 refer to 3.4.6 (2) (mam) intp7 input pm35 = 1 setting not needed for p35 ? p35 a14 note 2 output pm35 = 0 p35 = 0 refer to 3.4.6 (2) (mam) intp8 input pm36 = 1 setting not needed for p36 ? p36 a15 note 2 output pm36 = 0 p36 = 0 refer to 3.4.6 (2) (mam) p37 intp9 input pm37 = 1 setting not needed for p37 ? notes 1. only for the v850/sc2 2. only for the v850/sc1 and v850/sc2
chapter 5 port functions user ? s manual u15109ej3v0ud 194 table 5-16. setting when port pin is used for alternate function (3/6) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) p40 to p47 ad0 to ad7 i/o setting not needed for pm40 to pm47 setting not needed for p40 to p47 refer to 3.4.6 (1) (mm) p50 to p57 ad8 to ad15 i/o setting not needed for pm50 to pm57 setting not needed for p50 to p57 refer to 3.4.6 (1) (mm) p60 to p65 a16 to a21 output setting not needed for pm60 to pm65 setting not needed for p60 to p65 refer to 3.4.6 (1) (mm) p70 to p77 ani0 to ani7 input none setting not needed for p70 to p77 ? p80 to p83 ani8 to ani11 input none setting not needed for p80 to p83 ? lben output p90 wrl note output setting not needed for pm90 setting not needed for p90 refer to 3.4.6 (1) (mm) p91 uben output setting not needed for pm91 setting not needed for p91 refer to 3.4.6 (1) (mm) r/w output p92 wrh note output setting not needed for pm92 setting not needed for p92 refer to 3.4.6 (1) (mm) dstb output p93 rd note output setting not needed for pm93 p93 = 1 refer to 3.4.6 (1) (mm) p94 astb output setting not needed for pm94 p94 = 1 refer to 3.4.6 (1) (mm) p95 hldak output setting not needed for pm95 setting not needed for p95 refer to 3.4.6 (1) (mm) p96 hldrq input setting not needed for pm96 setting not needed for p96 refer to 3.4.6 (1) (mm) kr0 input pm 100 = 1 setting not needed for p100 to7 output ? p100 a5 note output pm100 = 0 p100 = 0 refer to 3.4.6 (2) (mam) kr1 input ti70 input pm101 = 1 setting not needed for p101 ? p101 a6 note output pm101 = 0 p101 = 0 refer to 3.4.6 (2) (mam) kr2 input ti00 input pm102 = 1 setting not needed for p102 ? p102 a7 note output pm102 = 0 p102 = 0 refer to 3.4.6 (2) (mam) note only for the v850/sc1 and v850/sc2
chapter 5 port functions user ? s manual u15109ej3v0ud 195 table 5-16. setting when port pin is used for alternate function (4/6) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) kr3 input pm 103 = 1 setting not needed for p103 ti01 input ? p103 a8 note 1 output pm103 = 0 p 103 = 0 refer to 3.4.6 (2) (mam) kr4 input pm 104 = 1 setting not needed for p104 to0 output ? p104 a9 note 1 output pm104 = 0 p104 = 0 refer to 3.4.6 (2) (mam) kr5 input ti10 input pm105 = 1 setting not needed for p105 ? p105 a10 note 1 output pm105 = 0 p105 = 0 refer to 3.4.6 (2) (mam) kr6 input ti11 input pm106 = 1 setting not needed for p106 ? p106 a11 note 1 output pm106 = 0 p106 = 0 refer to 3.4.6 (2) (mam) kr7 input pm 107 = 1 setting not needed for p107 to1 output ? p107 a12 note 1 output pm107 = 0 p107 = 0 refer to 3.4.6 (2) (mam) wait input pm110 = 1 setting not needed for p110 wac = 1 (pac) p110 a1 note 1 output pm110 = 0 p110 = 0 refer to 3.4.6 (2) (mam) p111 a2 note 1 output pm111 = 0 p111 = 0 refer to 3.4.6 (2) (mam) p112 a3 note 1 output pm112 = 0 p112 = 0 refer to 3.4.6 (2) (mam) p113 a4 note 1 output pm113 = 0 p113 = 0 refer to 3.4.6 (2) (mam) p114 cantx1 note 2 output pm114 = 0 p 114 = 0 pac 114 = 1 (pac) p115 canrx1 note 2 input pm 115 = 1 p 115 = 0 pac 115 = 1 (pac) notes 1. only for the v850/sc1 and v850/sc2 2. only for the v850/sc3
chapter 5 port functions user ? s manual u15109ej3v0ud 196 table 5-16. setting when port pin is used for alternate function (5/6) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) p116 cantx2 note output pm116 = 0 p 116 = 0 pac 116 = 1 (pac) p117 canrx2 note input pm 117 = 1 p 117 = 0 pac 117 = 1 (pac) input pm 120 = 1 p120 sck5 output pm120 = 0 p120 = 0 pac 120 = 1 (pac2) p121 si5 input pm 121 = 1 p 121 = 0 pac 121 = 1 (pac2) p122 so5 output pm122 = 0 p 122 = 0 pac 122 = 1 (pac2) input pm 123 = 1 p123 sck6 output pm123 = 0 p123 = 0 pac 123 = 1 (pac2) p124 si6 input pm 124 = 1 p 124 = 0 pac 124 = 1 (pac2) p125 so6 output pm125 = 0 p 125 = 0 pac 125 = 1 (pac2) p126 to10 output pm126 = 0 p 126 = 0 ? p127 to11 output pm127 = 0 p 127 = 0 ? si3 input p140 rxd1 input pm140 = 1 setting not needed for p140 ? so3 output p141 txd1 output pm141 = 0 p 141 = 0 ? input pm 142 = 1 setting not needed for p142 sck3 output pm142 = 0 p 142 = 0 p142 asck1 input pm 142 = 1 setting not needed for p142 ? p143 rxd2 input pm 143 = 1 setting not needed for p143 ? p144 txd2 output pm144 = 0 p 144 = 0 ? p145 asck2 input pm 145 = 1 setting not needed for p145 ? p146 ti100 input pm 146 = 1 setting not needed for p146 ? p147 ti101 input pm 147 = 1 setting not needed for p147 ? p150 rxd3 input pm 150 = 1 setting not needed for p150 ? p151 txd3 output pm151 = 0 p 151 = 0 ? note only for the pd703089y and 70f3089y
chapter 5 port functions user ? s manual u15109ej3v0ud 197 table 5-16. setting when port pin is used for alternate function (6/6) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) p152 asck3 input pm 152 = 1 setting not needed for p152 ? p153 ti110 input pm 153 = 1 setting not needed for p153 ? p154 ti111 input pm 154 = 1 setting not needed for p154 ? p155 to12 output pm155 = 0 p 155 = 0 ? p156 ti120 input pm 156 = 1 setting not needed for p156 ? p157 ti121 input pm 157 = 1 setting not needed for p157 ? p176 vm45 output pm176 = 0 p 176 = 0 refer to 14.3 (2) (vm45c) caution when changing the output level of ports 0 and 3 by setting the port function output mode of ports 0 and 3, the interrupt request flag will be set because ports 0 and 3 also have alternate functions as external interrupt request inputs. therefore, be sure to set the corresponding interrupt mask flag to 1 before using ports 0 and 3 as output pins. remark pmnx bit of pmn register and pnx bit of pn register n: 0 (x = 0 to 7) n: 1 (x = 0 to 7) n: 2 (x = 0 to 7) n: 3 (x = 0 to 7) n: 4 (x = 0 to 7) n: 5 (x = 0 to 7) n: 6 (x = 0 to 5) n: 7 (x = 0 to 7) n: 8 (x = 0 to 3) n: 9 (x = 0 to 6) n: 10 (x = 0 to 7) n: 11 (x = 0 to 7) n: 12 (x = 0 to 7) n: 14 (x = 0 to 7) n: 15 (x = 0 to 7) n: 17 (x = 0 to 6)
chapter 5 port functions user?s manual u15109ej3v0ud 198 5.4 operation of port function the operation of a port differs depending on whether the port is in the input or output mode, as described below. 5.4.1 writing data to i/o port (1) in output mode a value can be written to the output latch by using a transfer instruction. the contents of the output latch are output from the pin. once data has been written to the output latch, it is retained until new data is written to the output latch. (2) in input mode a value can be written to the output latch by using a transfer instruction. because the output buffer is off, however, the status of the pin does not change. once data has been written to the output latch, it is retained until new data is written to the output latch. caution a bit manipulation instruction (clr1, set1, not1) manipulates 1 bit but accesses a port in 8- bit units. if this instruction is executed to manipulate a port with a mixture of input and output bits, the contents of the output latch of a pin set in the input mode, in addition to the bit to be manipulated, are overwritten to the current input pin status and become undefined. 5.4.2 reading data from i/o port (1) in output mode the contents of the output latch can be read by using a transfer instruction. the contents of the output latch do not change. (2) in input mode the status of the pin can be read by using a transfer instruction. the contents of the output latch do not change.
user?s manual u15109ej3v0ud 199 chapter 6 bus control function the v850/sc1, v850/sc2, and v850/sc3 are provided with an external bus interface function by which external memories, such as rom and ram, and i/o can be connected. 6.1 features ? address bus (separate output possible only for the v850/sc1 and v850/sc2) ? 16-bit data bus ? able to be connected to external devices via pins with alternate-functions as ports ? wait function ? programmable wait function: up to 3 wait states can be inserted every 2 blocks ? external wait control through wait input pin ? idle state insertion function ? bus mastership arbitration function ? bus hold function
chapter 6 bus control function user?s manual u15109ej3v0ud 200 6.2 bus control pins and control register 6.2.1 bus control pins the following pins are used for interfacing to external devices. table 6-1. bus control pins external bus interface function corresponding port (pins) address/data bus (ad0 to ad7) port 4 (p40 to p47) address/data bus (ad8 to ad15) port 5 (p50 to p57) address bus (a1 to a4) note port 11 (p110 to p113) address bus (a5 to a12) note port 10 (p100 to p107) address bus (a13 to a15) note port 3 (p34 to p36) address bus (a16 to a21) port 6 (p60 to p65) read/write control (lben, uben, r/w, dstb, wrl note , wrh note , rd note ) port 9 (p90 to p93) address strobe (astb) port 9 (p94) bus hold control (hldrq, hldak) port 9 (p95, p96) external wait control (wait) port 11 (p110) note only for the v850/sc1 and v850/sc2. the bus interface function of each pin is enabled by setting the memory expansion mode register (mm) or memory address output mode register (mam) for the v850/sc1 and v850/sc2, and the memory expansion mode register (mm) for the v850/sc3. for details of external bus interface operating mode specification, refer to 3.4.6 (1) memory expansion mode register (mm) , (2) memory address output mode register (mam) . caution for debugging when using the separate bus of the v850/sc1 and v850/sc2, refer to the user?s manual of the relevant in-circuit emulator.
chapter 6 bus control function user?s manual u15109ej3v0ud 201 6.2.2 control register (1) system control register (syc) (v850/sc1, v850/sc2) this register switches control signals for the bus interface. the system control register can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff064h symbol7654321<0> syc0000000bic bic bus interface control 0 dstb, r/w, lben, uben note signals output 1 rd, wrl, wrh, uben note signals output note the uben signal is output regardless of the bic bit setting in the external expansion mode (set by the memory expansion mode register (mm)). caution in the v850/sc1 and v850/sc2, when using port 9 as an i/o port, set the bic bit to 0. note that the bic bit is 0 after system reset. 6.3 bus access 6.3.1 number of access clocks the number of basic clocks necessary for accessing each resource is as follows. table 6-2. number of access clocks peripheral i/o (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) peripheral i/o (16 bits) external memory (16 bits) instruction fetch 1 3 disabled 3 + n operand data access 3 1 3 3 + n remarks 1. unit: clock/access 2. n: number of wait insertions
chapter 6 bus control function user?s manual u15109ej3v0ud 202 6.3.2 bus width the cpu carries out peripheral i/o access and external memory access in 8-bit, 16-bit, or 32-bit units. the following shows the operation for each access. (1) byte access (8 bits) byte access is divided into two types: access to even addresses and access to odd addresses. figure 6-1. byte access (8 bits) 0 7 0 7 8 15 byte data external data bus (a) access to even addresses 0 7 0 7 8 15 byte data external data bus (b) access to odd addresses (2) halfword access (16 bits) in halfword access to external memory, data is handled as is because the data bus is fixed to 16 bits. figure 6-2. halfword access (16 bits) 00 15 15 halfword data external data bus (3) word access (32 bits) in word access to external memory, the lower halfword is accessed first and then the higher halfword is accessed. figure 6-3. word access (32 bits) 0 15 0 15 16 31 word data external data bus first 0 15 0 15 16 31 word data external data bus second
chapter 6 bus control function user ? s manual u15109ej3v0ud 203 6.4 memory block function the 16 mb memory space is divided into memory blocks of 1 mb units. the programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. figure 6-4. memory block block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 on-chip peripheral i/o area internal ram area external memory area ffffffh f00000h efffffh e00000h dfffffh d00000h cfffffh c00000h bfffffh b00000h afffffh a00000h 9fffffh 900000h 8fffffh 800000h 7fffffh 700000h 6fffffh 600000h 5fffffh 500000h 4fffffh 400000h 3fffffh 300000h 2fffffh 200000h 1fffffh 100000h 0fffffh 000000h internal rom area
chapter 6 bus control function user ? s manual u15109ej3v0ud 204 6.5 wait function 6.5.1 programmable wait function to facilitate interfacing with low-speed memories and i/o devices, up to 3 data wait states can be inserted in a bus cycle that starts every two memory blocks. the number of wait states can be programmed by using the data wait control register (dwc). immediately after the system has been reset, three data wait insertion states are automatically programmed for all memory blocks. (1) data wait control register (dwc) this register can be read/written in 16-bit units. after reset: ffffh r/w address: fffff060h symbol1514131211109876543210 dwc dw71 dw70 dw61 dw60 dw51 dw50 dw41 dw40 dw31 dw30 dw21 dw20 dw11 dw10 dw01 dw00 dwn1 dwn0 number of wait states to be inserted 000 011 102 113 n blocks into which wait states are inserted 0 blocks 0/1 1 blocks 2/3 2 blocks 4/5 3 blocks 6/7 4 blocks 8/9 5 blocks 10/11 6 blocks 12/13 7 blocks 14/15 block 0 is reserved for the internal rom area. it is not subject to programmable wait control, regardless of the setting of dwc, and is always accessed without wait states. the internal ram area of block 15 is not subject to programmable wait control and is always accessed without wait states. the on-chip peripheral i/o area of this block is also not subject to programmable wait control; wait control is dependent upon the execution of each peripheral function.
chapter 6 bus control function user ? s manual u15109ej3v0ud 205 6.5.2 external wait function when an extremely slow device, i/o, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by sampling the external wait pin (wait) to synchronize with the external device. the external wait signal is data wait only, and does not affect the access times of the internal rom, internal ram, and on-chip peripheral i/o areas, similar to the programmable wait. the external wait signal can be input asynchronously to clkout and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle. if the setup/hold time at sampling timing is not satisfied, the wait state may or may not be inserted in the next state. caution because the a1 pin and wait pin are alternate-function pins in the v850/sc1 and v850/sc2, the wait pin based wait function cannot be used when using a separate bus (programmable wait can be used, however). similarly, a separate bus cannot be used when the wait pin based wait function is being used. 6.5.3 relationship between programmable wait and external wait a wait cycle is inserted as a result of an or operation between the wait cycle specified by the set value of a programmable wait and the wait cycle controlled by the wait pin. in other words, the number of wait cycles is determined by whichever has more cycles. figure 6-5. wait control wait control programmable wait wait by wait pin for example, if the number of programmable waits and the timing of the wait pin input signal are as illustrated below, three wait states will be inserted in the bus cycle. figure 6-6. example of inserting wait states clkout t1 t2 tw tw tw t3 wait pin wait by wait pin programmable wait wait control remark { : valid sampling timing
chapter 6 bus control function user ? s manual u15109ej3v0ud 206 6.6 idle state insertion function to facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory read accesses every two blocks, one idle state (ti) can be inserted into the current bus cycle after the t3 state. the bus cycle following continuous bus cycles starts after one idle state. specifying insertion of the idle state is programmable by using the bus cycle control register (bcc). immediately after the system has been reset, idle state insertion is automatically programmed for all memory blocks. (1) bus cycle control register (bcc) this register can be read/written in 16-bit units. after reset: aaaah r/w address: fffff062h symbol1514131211109876543210 bcc bc710bc610bc510bc410bc310bc210bc110bc010 bcn1 idle state insert specification 0 not inserted 1 inserted n blocks into which idle state is inserted 0 blocks 0/1 1 blocks 2/3 2 blocks 4/5 3 blocks 6/7 4 blocks 8/9 5 blocks 10/11 6 blocks 12/13 7 blocks 14/15 block 0 is reserved for the internal rom area; therefore no idle state can be specified. the internal ram area and on-chip peripheral i/o area of block 15 are not subject to insertion of an idle state. be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to 0. if these bits are set to 1, the operation is not guaranteed.
chapter 6 bus control function user ? s manual u15109ej3v0ud 207 6.7 bus hold function 6.7.1 outline of function when the mm3 bit of the memory expansion mode register (mm) is set (1), the hldrq and hldak pin functions of p95 and p96 become valid. when the hldrq pin becomes active (low) indicating that another bus master is requesting acquisition of the bus, the external address/data bus and strobe pins go into a high-impedance state note , and the bus is released (bus hold status). when the hldrq pin becomes inactive (high) indicating that the request for the bus is cleared, these pins are driven again. during the bus hold period, the internal operation continues until the next external memory access. the bus hold status can be recognized by the hldak pin becoming active (low). this feature can be used to design a system where two or more bus masters exist, such as when a multi- processor configuration is used and when a dma controller is connected. bus hold requests are not acknowledged between the first and the second word access, nor between a read access and a write access in the read modify write access of a bit manipulation instruction. note when using a separate bus in the v850/sc1 and v850/sc2, pins a1 to a15 are in a held state.
chapter 6 bus control function user?s manual u15109ej3v0ud 208 6.7.2 bus hold procedure the procedure of the bus hold function is illustrated below. figure 6-7. bus hold procedure 6.7.3 operation in power save mode in the idle or stop mode, the system clock is stopped. consequently, the bus hold status is not set even if the hldrq pin becomes active. in the halt mode, the hldak pin immediately becomes active when the hldrq pin becomes active, and the bus hold status is set. when the hldrq pin becomes inactive, the hldak pin becomes inactive. as a result, the bus hold status is cleared, and the halt mode is set again. hldrq hldak < 1 >< 2 >< 3 >< 4 >< 5 >< 7 >< 8 >< 9 > < 6 > <1> hldrq = 0 acknowledged <2> all bus cycle start requests pending <3> end of current bus cycle <4> bus idle status <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> releases pending bus cycle start requests <9> start of bus cycle normal status bus hold status normal status
chapter 6 bus control function user ? s manual u15109ej3v0ud 209 6.8 bus timing the v850/sc1, v850/sc2, and v850/sc3 can execute read/write control for an external device using the following two modes. ? mode using dstb, r/w, lben, uben, and astb signals ? mode using rd, wrl, wrh, and astb signals set these modes by using the bic bit of the system control register (syc) (see 6.2.2 (1) system control register (syc) (v850/sc1, v850/sc2) ). figure 6-8. memory read (1/4) (a) 0 waits t1 t2 t3 clkout (output) a16 to a21 note (output) ad0 to ad15 (i/o) address data address astb (output) r/w (output) dstb, rd note (output) uben, lben (output) wait (input) wrh note , wrl note (output) h a1 to a15 (output) address note only for the v850/sc1 and v850/sc2 remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken lines indicate the high-impedance state.
chapter 6 bus control function user ? s manual u15109ej3v0ud 210 figure 6-8. memory read (2/4) (b) 1 wait t1 t2 tw clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) address address astb (output) r/w (output) dstb, rd note (output) uben, lben (output) wait (input) wrh note , wrl note (output) t3 data h a1 to a15 note (output) address note only for the v850/sc1 and v850/sc2 remarks 1. { indicates the sampling timing when the number of programmable waits is set to 1. 2. the broken lines indicate the high-impedance state.
chapter 6 bus control function user ? s manual u15109ej3v0ud 211 figure 6-8. memory read (3/4) (c) 0 waits, idle state t1 t2 t3 clkout (output) a1 to a15 note (output) ad0 to ad15 (i/o) address address astb (output) r/w (output) dstb, rd note (output) uben, lben (output) wait (input) wrh note , wrl note (output) h ti data a16 to a21 (output) address note only for the v850/sc1 and v850/sc2 remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken lines indicate the high-impedance state.
chapter 6 bus control function user ? s manual u15109ej3v0ud 212 figure 6-8. memory read (4/4) (d) 1 wait, idle state t1 t2 tw address address t3 data ti h address clkout (output) a1 to a15 note (output) ad0 to ad15 (i/o) astb (output) r/w (output) dstb, rd note (output) uben, lben (output) wait (input) wrh note , wrl note (output) a16 to a21 (output) note only for the v850/sc1 and v850/sc2 remarks 1. { indicates the sampling timing when the number of programmable waits is set to 1. 2. the broken lines indicate the high-impedance state.
chapter 6 bus control function user ? s manual u15109ej3v0ud 213 figure 6-9. memory write (1/2) (a) 0 waits t1 t2 t3 address data note 2 address h address clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) astb (output) r/w (output) dstb (output) uben, lben (output) wait (input) rd note 1 (output) wrh note 1 , wrl note 1 (output) a1 to a15 note 1 (output) notes 1. only for the v850/sc1 and v850/sc2 2. ad0 to ad7 output invalid data when odd-address byte data is accessed. ad8 to ad15 output invalid data when even-address byte data is accessed. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken lines indicate the high-impedance state.
chapter 6 bus control function user ? s manual u15109ej3v0ud 214 figure 6-9. memory write (2/2) (b) 1 wait t1 t2 tw clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) address astb (output) r/w (output) dstb (output) uben, lben (output) wait (input) rd note 1 (output) wrh note 1 , wrl note 1 (output) t3 data note 2 address h a1 to a15 note 1 (output) address notes 1. only for the v850/sc1 and v850/sc2 2. ad0 to ad7 output invalid data when odd-address byte data is accessed. ad8 to ad15 output invalid data when even-address byte data is accessed. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 1. 2. the broken lines indicate the high-impedance state.
chapter 6 bus control function user ? s manual u15109ej3v0ud 215 figure 6-10. bus hold timing clkout (output) r/w (output) dstb note 2 , rd note 2 , wrh note 2 , wrl note 2 (output) uben, lben (output) wait (input) hldrq (input) t2 t1 t3 th th th th ti t1 hldak (output) a16 to a21 (output) a1 to a15 note 2 (output) ad0 to ad15 (i/o) address address address data address astb (output) undefined address address note 1 note 3 notes 1. if the hldrq signal is inactive (high level) at this sampling timing, the bus hold state is not entered. 2. only for the v850/sc1 and v850/sc2 3. if the bus hold status is entered after a write cycle, a high level may be output momentarily from the r/w pin immediately before the hldak signal changes from high level to low level. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken lines indicate the high-impedance state.
chapter 6 bus control function user ? s manual u15109ej3v0ud 216 6.9 bus priority there are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch (continuous). the bus hold cycle is given the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (continuous) in that order. the instruction fetch cycle may be inserted in between the read access and write access in read-modify-write access. no instruction fetch cycle and bus hold are inserted between the lower halfword access and higher halfword access of word access operations. table 6-3. bus priority external bus cycle priority bus hold 1 operand data access 2 instruction fetch (branch) 3 instruction fetch (continuous) 4 6.10 memory boundary operation condition 6.10.1 program space (1) do not execute a branch to the on-chip peripheral i/o area or a continuous fetch from the internal ram area to peripheral i/o area. if a branch or instruction fetch is executed, the nop instruction code is continuously fetched and fetching from external memory is not performed. (2) a prefetch operation extending over the on-chip peripheral i/o area (invalid fetch) does not take place if a branch instruction exists at the upper-limit address of the internal ram area. 6.10.2 data space only the address aligned at the halfword boundary (when the least significant bit of the address is ? 0 ? )/word boundary (when the lowest 2 bits of the address are ? 0 ? ) is accessed by halfword (16 bits)/word (32 bits) access, respectively. therefore, access that extends over the memory or memory block boundary does not take place. for details, refer to the v850 series architecture user ? s manual .
user?s manual u15109ej3v0ud 217 chapter 7 interrupt/exception processing function 7.1 outline the v850/sc1, v850/sc2, and v850/sc3 are provided with a dedicated interrupt controller (intc) for interrupt servicing and realize a high-powered interrupt function that can service interrupt requests from a total of 49 to 56 sources. an interrupt is an event that occurs independently of program execution, and an exception is an event that whose occurrence is dependent on program execution. the v850/sc1, v850/sc2, and v850/sc3 can process interrupt requests from the on-chip peripheral hardware and external sources. moreover, exception processing can be started (exception trap) by the trap instruction (software exception) or by generation of an exception event (fetching of an illegal op code). 7.1.1 features ? interrupts ? non-maskable: 2 sources ? maskable: (number of maskable interrupt sources differs depending on product) (v850/sc1) pd703068y, 70f3089y: 49 sources (v850/sc2) pd703069y, 70f3089y: 51 sources (v850/sc3) pd703088y: 53 sources pd703089y, 70f3089y: 56 sources ? 8 levels of programmable priorities ? mask specification for interrupt requests according to priority ? masks can be individually specified for maskable interrupt requests. ? noise elimination, edge detection, and valid edge of external interrupt request signal can be specified. ? exceptions ? software exceptions: 32 sources ? exception trap: 1 source (illegal op code exception) the interrupt/exception sources are listed in table 7-1.
chapter 7 interrupt/exception proc essing f unction user?s manual u15109ej3v0ud 218 table 7-1. interrupt source list (1/3) type classifi- cation default priority name trigger interrupt source exception code handler address restored pc interrupt control register reset interrupt ? reset reset input ? 0000h 00000000h undefined ? interrupt ? nmi nmi pin input ? 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt wdtovf non-maskable wdt 0020h 00000020h nextpc ? exception ? trap0n note 1 trap instruction ? 004nh note 1 00000040h nextpc ? software exception exception ? trap1n note 1 trap instruction ? 005nh note 1 00000050h nextpc ? exception trap exception ? ilgop illegal op code ? 0060h 00000060h nextpc ? 0 intwdtm wdtovf maskable wdt 0080h 00000080h nextpc wdtic 1 intp0 intp0 pin pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin pin 00f0h 000000f0h nextpc pic6 8 intcsi5 csi5 transmit end sio5 0100h 00000100h nextpc csic5 9 intad a/d conversion end a/d 0110h 00000110h nextpc adic 10 intdma0 dma0 transfer end dma0 0120h 00000120h nextpc dmaic0 11 intdma1 dma1 transfer end dma1 0130h 00000130h nextpc dmaic1 12 intdma2 dma2 transfer end dma2 0140h 00000140h nextpc dmaic2 13 inttm00 tm0 and cr00 match/ ti01 pin valid edge tm0 0150h 00000150h nextpc tmic00 14 inttm01 tm0 and cr01 match/ ti00 pin valid edge tm0 0160h 00000160h nextpc tmic01 15 inttm10 tm1 and cr10 match/ ti11 pin valid edge tm1 0170h 00000170h nextpc tmic10 16 inttm11 tm1 and cr11 match/ ti10 pin valid edge tm1 0180h 00000180h nextpc tmic11 17 inttm70 tm7 and cr70 match/ ti71 pin valid edge tm7 0190h 00000190h nextpc tmic70 18 inttm71 tm7 and cr71 match/ ti70 pin valid edge tm7 01a0h 000001a0h nextpc tmic71 19 intcsi6 csi6 transmission/ reception completion csi6 01b0h 000001b0h nextpc csic6 20 inttm5/ intp8 note 2 tm5 compare match/ ovf/intp8 pin tm5/pin 01c0h 000001c0h nextpc tmic5 21 intwtn watch timer ovf wtn 01d0h 000001d0h nextpc wtnic 22 intwtni watch timer prescaler wtn 01e0h 000001e0h nextpc wtniic maskable interrupt 23 intiic0/ intcsi0 i 2 c0 interrupt/ csi0 transmit end i 2 c0/ sio0 01f0h 000001f0h nextpc csic0 notes 1. n: 0 to fh 2. when using intp8 or intp9, stop tm5 and tm6 (tcem0 bit of tmcm0 register = 0) and do not use them (m = 5, 6). when using tm5 or tm6, do not specify the valid edge for intp8 and intp9 (egp1n bit of egp1 register and egn1n bit of egn1 register = 0) and do not use them as external interrupts (they can be used as ports) (n = 6, 7).
chapter 7 interrupt/exception proc essing f unction user?s manual u15109ej3v0ud 219 table 7-1. interrupt source list (2/3) type classifi- cation default priority name trigger interrupt source exception code handler address restored pc interrupt control register 24 inttm6/ intp9 note 1 tm6 compare match/ ovf/intp9 pin tm6/pin 0200h 00000200h nextpc tmic6 25 intsr0/ intcsi4 uart receive end/ csi4 transmit end uart0/ sio4 0210h 00000210h nextpc csic4 26 intst0 uart0 transmit end uart0 0220h 00000220h nextpc stic0 27 intkr key return interrupt kr 0230h 00000230h nextpc kric 28 intce1 note 2 / intie1 note 3 fcan1 serial error/ iebus transfer end fcan1/ iebus 0240h 00000240h nextpc canic1/ iebic1 29 intcr1 note 2 / intie2 note 3 fcan1 reception/ iebus communication end fcan1/ iebus 0250h 00000250h nextpc canic2/ iebic2 30 intct1 note 2 fcan1 transmission fcan1 0260h 00000260h nextpc canic3 31 intcme note 2 fcan memory access error fcan1/ 2 0270h 00000270h nextpc canic7 32 inttm80 tm8 and cr80 match/ ti81 pin valid edge tm8 0280h 00000280h nextpc tmic80 33 inttm81 tm81 and cr81 match/ ti80 pin valid edge tm8 0290h 00000290h nextpc tmic81 34 inttm90 tm9 and cr90 match/ ti91 pin valid edge tm9 02a0h 000002a0h nextpc tmic90 35 inttm91 tm9 and cr91 match/ ti90 pin valid edge tm9 02b0h 000002b0h nextpc tmic91 36 intsr1/ intcsi3 uart1 receive end/ csi3 transmit end uart1/ csi3 02c0h 000002c0h nextpc csic3 37 intst1 uart1 transmit end uart1 02d0h 000002d0h nextpc stic1 38 intdma3 dma3 transfer end dma3 02e0h 000002e0h nextpc dmaic3 39 intdma4 dma4 transfer end dma4 02f0h 000002f0h nextpc dmaic4 40 intdma5 dma5 transfer end dma5 0300h 00000300h nextpc dmaic5 41 intce2 note 4 fcan2 serial error fcan2 0310h 00000310h nextpc canic4 42 intcr2 note 4 fcan2 reception fcan2 0320h 00000320h nextpc canic5 43 intct2 note 4 fcan2 transmission fcan2 0330h 00000330h nextpc canic6 44 intp7 intp7 pin pin 0340h 00000340h nextpc pic7 45 intsr2 uart2 receive end uart2 0350h 00000350h nextpc sric2 46 intst2 uart2 transmit end uart2 0360h 00000360h nextpc stic2 47 intsr3 uart3 receive end uart3 0370h 00000370h nextpc sric3 48 intst3 uart3 transmit end uart3 0380h 00000380h nextpc stic3 maskable interrupt 49 inttm100 tm10 and cr100 match/ ti101 pin valid edge tm10 0390h 00000390h nextpc tmic100 notes 1. when using intp8 or intp9, stop tm5 and tm6 (tcem0 bit of tmcm0 register = 0) and do not use them (m = 5, 6). when using tm5 or tm6, do not specify the valid edge for intp8 and intp9 (egp1n bit of egp1 register and egn1n bit of egn1 register = 0) and do not use them as external interrupts (they can be used as ports) (n = 6, 7). 2. only for the v850/sc3 3. only for the v850/sc2 4. only for the pd703089y and 70f3089y
chapter 7 interrupt/exception proc essing f unction user?s manual u15109ej3v0ud 220 table 7-1. interrupt source list (3/3) type classifi- cation default priority name trigger interrupt source exception code handler address restored pc interrupt control register 50 inttm101 tm10 and cr101 match/ ti100 pin valid edge tm10 03a0h 000003a0h nextpc tmic101 51 inttm110 tm11 and cr110 match/ ti111 pin valid edge tm11 03b0h 000003b0h nextpc tmic110 52 inttm111 tm11 and cr111 match/ ti110 pin valid edge tm11 03c0h 000003c0h nextpc tmic111 53 inttm120 tm12 and cr120 match/ ti121 pin valid edge tm12 03d0h 000003d0h nextpc tmic120 54 inttm121 tm12 and cr121 match/ ti120 pin valid edge tm12 03e0h 000003e0h nextpc tmic121 maskable interrupt 55 intiic1/ intiic2 i 2 c interrupt/ csi2 transmit end i 2 c1/ sio2 03f0h 000003f0h nextpc csic2 remarks 1. default priority: priority when two or more maskable interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, the value of the pc saved when an interrupt is granted during divh (division) instruction execution is the value of the pc of the current instruction (divh). 2. the execution address of the illegal instruction when an illegal op code exception occurs is calculated with (restored pc ? 4). 3. the restored pc of an interrupt/exception other than reset is the value of (the pc when an event occurred) + 1. 4. non-maskable and maskable interrupts (intwdt and intwdtm) are set by the wdtm4 bit of the watchdog timer mode register (wdtm).
chapter 7 interrupt/exception proc essing f unction user?s manual u15109ej3v0ud 221 7.2 non-maskable interrupts non-maskable interrupts are acknowledged unconditionally, even when interrupts are disabled (di state). an nmi is not subject to priority control and takes precedence over all other interrupts. the following two non-maskable interrupt requests are available in the v850/sc1, v850/sc2, and v850/sc3. ? nmi pin input (nmi) ? non-maskable watchdog timer interrupt request (intwdt) when the valid edge specified by the rising edge specification register 0 (egp0) and falling edge specification register 0 (egn0) is detected at the nmi pin, an interrupt occurs. intwdt functions as the non-maskable interrupt (intwdt) only when the wdtm4 bit of the watchdog timer mode register (wdtm) is set to 1. while the service routine of a non-maskable interrupt is being executed (psw.np = 1), the acknowledgement of another non-maskable interrupt request is held pending. the pending nmi is acknowledged when psw.np is cleared to 0 after the original service routine of the non-maskable interrupt under execution has been terminated (by the reti instruction). note that if two or more nmi requests are input during the execution of the service routine for an nmi, only are nmi will be acknowledged after psw.np is cleared to 0. caution do not clear psw.np to 0 using the ldsr instruction during non-maskable interrupt servicing. if psw. np is cleared to 0, subsequent interrupts cannot be acknowledged correctly.
chapter 7 interrupt/exception proc essing f unction user?s manual u15109ej3v0ud 222 7.2.1 operation if a non-maskable interrupt is generated, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the restored pc to fepc. (2) saves the current psw to fepsw. (3) writes the exception code (0010h, 0020h) to the higher halfword (fecc) of ecr. (4) sets the np and id bits of the psw and clears the ep bit. (5) loads the handler address (00000010h, 00000020h) of the non-maskable interrupt routine to the pc, and transfers control. figure 7-1. non-maskable interrupt servicing nmi input non-maskable interrupt request interrupt servicing interrupt request pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc restored pc psw exception code 1 0 1 handler address 00000010h (nmi) 00000020h (intwdt) handler address: intc acknowledged cpu processing psw. np 1 0
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 223 figure 7-2. acknowledging non-maskable interrupt requests (a) if a new nmi request is generated while an nmi service routine is being executed: main routine nmi request nmi request (psw. np = 1) nmi request held pending regardless of the np bit of psw pending nmi request processed (b) if a new nmi request is generated twice while an nmi service routine is being executed: main routine nmi request nmi request held pending because nmi service program is being processed held pending because nmi service program is being processed nmi request only one nmi request is acknowledged even though two or more nmi requests are generated
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 224 7.2.2 restore execution is restored from non-maskable interrupt servicing by the reti instruction. operation of reti instruction when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. (1) restores the values of the pc and psw from fepc and fepsw, respectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. (2) transfers control back to the address of the restored pc and psw. how the reti instruction is processed is shown below. figure 7-3. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and psw.np bit are changed by the ldsr instruction during non- maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 225 7.2.3 np flag the np flag is a status flag that indicates that non-maskable interrupt (nmi) servicing is under execution. this flag is set when an nmi interrupt request has been acknowledged, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged. figure 7-4. np flag (np) after reset: 00000020h symbol 31 876543210 psw 0 np ep id sat cy ov s z np nmi servicing state 0 no nmi interrupt servicing 1 nmi interrupt currently being serviced 7.2.4 noise eliminator of nmi pin nmi pin noise is eliminated by a noise eliminator using analog delay. therefore, a signal input to the nmi pin is not detected as an edge, unless it maintains its input level for a certain period. the edge is detected only after a certain period has elapsed. the nmi pin is used for canceling the software stop mode. in the software stop mode, noise elimination using the system clock does not occur because the internal system clock is stopped.
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 226 7.2.5 edge detection function of nmi pin the nmi pin valid edge can be selected from the following four types: falling edge, rising edge, both edges, neither rising nor falling edge detected. rising edge specification register 0 (egp0) and falling edge specification register 0 (egn0) specify the valid edge of non-maskable interrupts (nmi). these two registers can be read/written in 1-bit or 8-bit units. after reset, the valid edge of the nmi pin is set to the ? neither rising nor falling edge detected ? state. therefore, the nmi pin functions as a normal port and an interrupt request cannot be acknowledged, unless a valid edge is specified by using the egp0 and egn0 registers. when using p00 as an output port, set the nmi valid edge to ? neither rising nor falling edge detected ? . (1) format of rising edge specification register 0 (egp0) after reset: 00h r/w address: fffff0c0h symbol <7> <6> <5> <4> <3> <2> <1> <0> egp0 egp07 egp06 egp05 egp04 egp03 egp02 egp01 egp00 egp0n rising edge validity control 0 no interrupt request signal occurs at the rising edge 1 interrupt request signal occurs at the rising edge n = 0: nmi pin control n = 1 to 7: intp0 to intp6 pins control (2) format of falling edge specification register 0 (egn0) after reset: 00h r/w address: fffff0c2h symbol <7> <6> <5> <4> <3> <2> <1> <0> egn0 egn07 egn06 egn05 egn04 egn03 egn02 egn01 egn00 egn0n falling edge validity control 0 no interrupt request signal occurs at the falling edge 1 interrupt request signal occurs at the falling edge n = 0: nmi pin control n = 1 to 7: intp0 to intp6 pins control
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 227 7.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. the v850/sc1, v850/sc2, and v850/sc3 have 49 to 56 maskable interrupt sources (refer to 7.1.1 features ). if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers, allowing programmable priority control. when an interrupt request has been acknowledged, the acknowledgement of other maskable interrupts is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt servicing routine, the interrupt enabled (ei) status is set, which enables interrupts having a higher priority to immediately interrupt the service routine currently in progress. note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. to use multiple interrupts, it is necessary to save eipc and eipsw to memory or a register before executing the ei instruction, and restore eipc and eipsw to the original values by executing the di instruction before the reti instruction. when the wdtm4 bit of the watchdog timer mode register (wdtm) is set to 0, the watchdog timer overflow interrupt functions as a maskable interrupt (intwdtm). 7.3.1 operation if a maskable interrupt occurs, the cpu performs the following processing, and transfers control to a handler routine: (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower halfword of ecr (eicc). (4) sets the id bit of the psw and clears the ep bit. (5) loads the corresponding handler address to the pc, and transfers control. the int input masked by intc and the int input that occurs while another interrupt is being serviced (when psw.np = 1 or psw.id = 1) are held pending internally. when the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 by using the reti and ldsr instructions, the pending int is input to start a new maskable interrupt servicing. how maskable interrupts are serviced is shown below.
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 228 figure 7-5. maskable interrupt servicing maskable interrupt request interrupt servicing eipc eipsw ecr. eicc psw. ep psw. id pc intc acknowledged cpu processing mask? yes no psw. id = 0 priority higher than that of interrupt currently being serviced? interrupt request pending psw. np psw. id interrupt request pending no no no no 1 0 1 0 int input yes yes yes yes priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? interrupt enable mode? restored pc psw exception code 0 1 handler address
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 229 7.3.2 restore to restore execution from the maskable interrupt servicing, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following steps, and transfers control to the address of the restored pc. (1) restores the values of the pc and psw from eipc and eipsw because the ep bit of the psw is 0 and the np bit of the psw is 0. (2) transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 7-6. reti instruction processing reti instruction restores original processing pc psw eipc eipsw psw. ep 1 0 1 0 pc psw fepc fepsw psw. np caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 230 7.3.3 priorities of maskable interrupts the v850/sc1, v850/sc2, and v850/sc3 provide a multiple interrupt service in which an interrupt can be acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels specified by the interrupt priority level specification bit (xxprn). when two or more interrupts having the same priority level specified by xxprn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, refer to table 7-1. programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is acknowledged, the id flag of the psw is automatically set (1). therefore, when multiple interrupts are to be used, clear (0) the id flag beforehand (for example, by placing the ei instruction into the interrupt service program) to set the interrupt enable mode. remark xx: identifying name of each peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 )
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 231 figure 7-7. example of interrupt nesting process (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b interrupt request b (level 2) servicing of c interrupt request c (level 3) interrupt request d (level 2) servicing of d servicing of e ei interrupt request e (level 2) interrupt request f (level 3) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. caution the values of eipc and eipsw must be saved before executing multiple interrupts. remarks 1. a to u in the figure are the names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests.
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 232 figure 7-7. example of interrupt nesting process (2/2) main routine ei interrupt request i (level 2) servicing of i processing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after processing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. notes 1. lower default priority 2. higher default priority
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 233 figure 7-8. example of servicing interrupt requests simultaneously generated main routine ei interrupt request a (level 2) interrupt request b (level 1) note 1 interrupt request c (level 1) note 2 servicing of interrupt request b servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority. notes 1. higher default priority 2. lower default priority remarks 1. a to c are the names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. 7.3.4 interrupt control register (xxicn) an interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. the interrupt control register can be read/written in 8- or 1-bit units. caution if the following three conditions conflict, interrupt servicing is executed twice. however, this does not occur when dma is not used. ? execution of a bit manipulation instruction corresponding to the interrupt request flag (xxifn) ? an interrupt via hardware of the same interrupt control register (xxicn) as the interrupt request flag (xxifn) is generated ? dma is started during execution of a bit manipulation instruction corresponding to the interrupt request flag (xxifn) two workarounds using software are shown below. ? insert a di instruction before the software-based bit manipulation instruction and an ei instruction after it, so that jumping to an interrupt immediately after the bit manipulation instruction execution does not occur. ? when an interrupt request is acknowledged, since the hardware becomes interrupt disabled (di state), clear the interrupt request flag (xxifn) before executing the ei instruction in each interrupt servicing routine.
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 234 after reset: 47h r/w address: fffff100h to fffff172h symbol<7><6>543210 xxicn xxifn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 xxifn interrupt request flag note 0 interrupt request not generated 1 interrupt request generated xxmkn interrupt mask flag 0 enables interrupt servicing 1 disables interrupt servicing (pending) xxprn2 xxprn1 xxprn0 interrupt priority specification bit 0 0 0 specifies level 0 (highest) 0 0 1 specifies level 1 0 1 0 specifies level 2 0 1 1 specifies level 3 1 0 0 specifies level 4 1 0 1 specifies level 5 1 1 0 specifies level 6 1 1 1 specifies level 7 (lowest) note automatically reset by hardware when interrupt request is acknowledged. remark xx: identifying name of each peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 )
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 235 the addresses and bits of the interrupt control registers are as follows. table 7-2. interrupt control registers (xxicn) (1/2) bit address register <7><6>543 2 1 0 fffff100h wdtic wdtif wdtmk 000wdtpr2wdtpr1wdtpr0 fffff102h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff104h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff106h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff108h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff10ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff10ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff10eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff110h csic5 csif5 csmk5 000cspr52cspr51cspr50 fffff112h adic adif admk 000adpr2adpr1adpr0 fffff114h dmaic0 dmaif0 dmamk0 000dmapr02dmapr01dmapr00 fffff116h dmaic1 dmaif1 dmamk1 000dmapr12dmapr11dmapr10 fffff118h dmaic2 dmaif2 dmamk2 000dmapr22dmapr21dmapr20 fffff11ah tmic00 tmif00 tmmk00 000tmpr002tmpr001tmpr000 fffff11ch tmic01 tmif01 tmmk01 000tmpr012tmpr011tmpr010 fffff11eh tmic10 tmif10 tmmk10 000tmpr102tmpr101tmpr100 fffff120h tmic11 tmif11 tmmk11 000tmpr112tmpr111tmpr110 fffff122h tmic70 tmif70 tmmk70 000tmpr702tmpr701tmpr700 fffff124h tmic71 tmif71 tmmk71 000tmpr712tmpr711tmpr710 fffff126h csic6 csif6 csmk6 000cspr62cspr61cspr60 fffff128h tmic5 tmif5 tmmk5 000tmpr52tmpr51tmpr50 fffff12ah wtnic wtnif wtnmk 000wtnpr2wtnpr1wtnpr0 fffff12ch wtniic wtniif wtnimk 000wtnipr2wtnipr1wtnipr0 fffff12eh csic0 csif0 csmk0 000cspr02cspr01cspr00 fffff130h tmic6 tmif6 tmmk6 000tmpr62tmpr61tmpr60 fffff132h csic4 csif4 csmk4 000cspr42cspr41cspr40 fffff134h stic0 stif0 stmk0 000stpr02stpr01stpr00 fffff136h kric krif krmk 000krpr2krpr1krpr0 canic1 note 1 canif1canmk1000canpr12canpr11canpr10 fffff138h iebic1 note 2 iebif1iebmk1000i ebpr12 iebpr11 iebpr10 canic2 note 1 canif2canmk2000canpr22canpr21canpr20 fffff13ah iebic2 note 2 iebif2iebmk2000i ebpr22 iebpr21 iebpr20 fffff13ch canic3 note 1 canif3canmk3000canpr32canpr31canpr30 fffff13eh canic7 note 1 canif7canmk7000canpr72canpr71canpr70 fffff140h tmic80 tmif80 tmmk80 000tmpr802tmpr801tmpr800 fffff142h tmic81 tmif81 tmmk81 000tmpr812tmpr811tmpr810 fffff144h tmic90 tmif90 tmmk90 000tmpr902tmpr901tmpr900 fffff146h tmic91 tmif91 tmmk91 000tmpr912tmpr911tmpr910 fffff148h csic3 csif3 csmk3 000cspr32cspr31cspr30 fffff14ah stic1 stif1 stmk1 000stpr12stpr11stpr10 notes 1. only for the v850/sc3 2. only for the v850/sc2
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 236 table 7-2. interrupt control registers (xxicn) (2/2) bit address register <7><6>543 2 1 0 fffff14ch dmaic3 dmaif3 dmamk3 000dmapr32dmapr31dmapr30 fffff14eh dmaic4 dmaif4 dmamk4 000dmapr42dmapr41dmapr40 fffff150h dmaic5 dmaif5 dmamk5 000dmapr52dmapr51dmapr50 fffff152h canic4 note canif4canmk4000canpr42canpr41canpr40 fffff154h canic5 note canif5canmk5000canpr52canpr51canpr50 fffff156h canic6 note canif6canmk6000canpr62canpr61canpr60 fffff158h pic7 pif7 pmk7 0 0 0 ppr72 ppr71 ppr70 fffff15ah sric2 srif2 srmk2 000srpr22srpr21srpr20 fffff15ch stic2 stif2 stmk2 000stpr22stpr21stpr20 fffff15eh sric3 srif3 srmk3 000srpr32srpr31srpr30 fffff160h stic3 stif3 stmk3 000stpr32stpr31stpr30 fffff162h tmic100 tmif100 tmmk100 000tmpr 1002 tmpr1001 tmpr1000 fffff164h tmic101 tmif101 tmmk101 000tmpr 1012 tmpr1011 tmpr1010 fffff168h tmic110 tmif110 tmmk110 000tmpr 1102 tmpr1101 tmpr1100 fffff16ah tmic111 tmif111 tmmk111 000tmpr 1112 tmpr1111 tmpr1110 fffff16ch tmic120 tmif120 tmmk120 000tmpr 1202 tmpr1201 tmpr1200 fffff16eh tmic121 tmif121 tmmk121 000tmpr 1212 tmpr1211 tmpr1210 fffff172h csic2 csif2 csmk2 000cspr22cspr21cspr20 note only for the pd703089y and 70f3089y
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 237 7.3.5 in-service priority register (ispr) this register holds the priority level of the maskable interrupt currently requesting acknowledgement. when the interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set (1) and remains set while the interrupt is being serviced. when the reti instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically reset (0) by hardware. however, it is not reset (0) when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only, in 8- or 1-bit units. after reset: 00h r address: fffff166h symbol <7> <6> <5> <4> <3> <2> <1> <0> ispr ispr7 ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 isprn indicates priority of interrupt currently requesting acknowledgement 0 interrupt request with priority n not acknowledged 1 interrupt request with priority n acknowledged remark n: 0 to 7 (priority level) 7.3.6 id flag the interrupt disable flag (id) controls the enabling and disabling of maskable interrupt requests, and is assigned to the psw. figure 7-9. id flag after reset: 00000020h symbol 31 876543210 psw 0 np ep id sat cy ov s z id specifies maskable interrupt servicing note 0 maskable interrupt acknowledgement enabled 1 maskable interrupt acknowledgement disabled (pending) note interrupt disable flag (id) function id is set (1) by the di instruction and reset (0) by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. non-maskable interrupts and exceptions are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set (1) by hardware. an interrupt request generated during the acknowledgement disabled period (id = 1) can be acknowledged when the xxifn bit of xxicn is set (1), and the id flag is reset (0). remark xx: identifying name of each peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 )
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 238 7.3.7 watchdog timer mode register (wdtm) this register can be read/written in 8- or 1-bit units (for details, refer to chapter 10 watchdog timer ). after reset: 00h r/w address: fffff384h symbol<7>6543210 wdtm run 0 0 wdtm4 wdtm3 0 0 0 run watchdog timer operation control 0 count operation stopped 1 count started after clearing wdtm4 timer mode selection/interrupt control by wdt 0 interval timer mode 1 wdt mode wdtm3 internal reset signal generation selection 0 when overflow occurs, the internal reset signal is not generated 1 when overflow occurs, the internal reset signal is generated caution if the run, wdtm4, or wdtm3 bit is set to 1, that bit can only be cleared by reset input. 7.3.8 noise elimination (1) elimination of noise from intp0 to intp3 and intp7 to intp9 pins an on-chip noise eliminator is provided that uses analog delay to eliminate noise. consequently, if a signal having a constant level is input for longer than a specified time, it is detected as a valid edge. edge detection occurs only after the specified amount of time has elapsed. (2) elimination of noise from intp4 and intp5 pins a digital noise eliminator is provided on chip. if the input level of the intp pin is detected by the sampling clock (f xx ) and the same level is not detected three successive times, the input pulse is eliminated as noise. note the following: ? if the input pulse width is 2 or 3 clocks, whether it will be detected as a valid edge or eliminated as noise is undetermined. to securely detect a valid edge, the same level input of 3 clocks or more is required. ? when a noise is generated in synchronization with a sampling clock, this may not be recognized as a noise. in this case, eliminate the noise by adding a filter to the input pin.
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 239 (3) elimination of noise from intp6 pin a digital noise eliminator is provided on chip. the sampling clock for digital sampling can be selected from among f xx , f xx /64, f xx /128, f xx /256, f xx /512, f xx /1024, and f xt . sampling is performed 3 times. the noise elimination control register (ncc) selects the clock to be used. remote control signals can be received effectively with this function. f xt can be used for the noise elimination clock. in this case, the intp6 external interrupt function is enabled in the idle/stop mode. this register can be read/written in 8- or 1-bit units. caution after the sampling clock has been changed, it takes 3 sampling clocks to initialize the noise eliminator. for that reason, if an intp6 valid edge is input within these 3 clocks, an interrupt request may occur. therefore, observe the following points when using the interrupt and dma functions. ? ? ? ? when using the interrupt function, after 3 sampling clocks have elapsed, enable interrupts after the interrupt request flag (bit 7 of pic6) has been cleared. ? ? ? ? when using the dma function, after 3 sampling clocks have elapsed, enable dma by setting bit 0 of dchcn. (a) noise elimination control register (ncc) after reset: 00h r/w address: fffff3d4h 7 6543210 ncc 00 000 ncs2 ncs1 ncs0 reliably eliminated noise width note ncs2 ncs1 ncs0 sampling clock f xx = 20 mhz f xx = 18.87 mhz f xx = 16 mhz 000 f xx 100.0 ns 105.0 ns 125.0 ns 001 f xx /64 6.4 s6.7 s8.0 s 010 f xx /128 12.8 s 13.5 s 16.0 s 011 f xx /256 25.6 s 27.1 s 32.0 s 100 f xx /512 51.2 s 54.2 s 64.0 s 101 f xx /1024 102.4 s 108.5 s 128.0 s 110 setting prohibited 111 f xt 61 s note since sampling is performed three times, the reliably eliminated noise width is 2 sampling clock.
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 240 7.3.9 edge detection function valid edges of the intp0 to intp9 pins can be selected for each pin from the following four types. ? rising edge ? falling edge ? both rising and falling edges ? neither rising nor falling edge detected the validity of the rising edge is controlled by rising edge specification register n (egpn), and the validity of the falling edge is controlled by falling edge specification register n (egnn) (n = 0, 1). these can be read/written in 8- or 1-bit units. refer to 7.2.5 (1) format of rising edge specification register 0 (egp0) and 7.2.5 (2) format of falling edge specification register 0 (egn0) for details of egp0 and egn0 and (1) format of rising edge specification register 1 (egp1) and (2) format of falling edge specification register 1 (egn1) for details of egp1 and egn1. after reset, the valid edges of the intp0 to intp9 pins are set to the ? neither rising nor falling edge detected ? state. therefore, the nmi pin functions as a normal port and interrupt requests cannot be acknowledged, unless a valid edge is specified by using the egp0 and egn0 registers. when using p01 to p07 or p35 to p37 as output ports, set the valid edges of intp0 to intp6 or intp7 to intp9 to ? neither rising nor falling edge detected ? or mask interrupt requests. (1) format of rising edge specification register 1 (egp1) after reset: 00h r/w address: fffff0c4h symbol <7> <6> <5> 4 3 2 1 0 egp1 egp17 egp16 egp15 0 0 0 0 0 egp1n rising edge validity control 0 no interrupt request signal occurs at the rising edge 1 interrupt request signal occurs at the rising edge n = 5 to 7: control of intp7 to intp9 pins (2) format of falling edge specification register 1 (egn1) after reset: 00h r/w address: fffff0c6h symbol <7> <6> <5> 4 3 2 1 0 egn1 egn17 egn16 egn15 0 0 0 0 0 egn1n falling edge validity control 0 no interrupt request signal occurs at the falling edge 1 interrupt request signal occurs at the falling edge n = 5 to 7: control of intp7 to intp9 pins
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 241 7.4 software exceptions a software exception is generated when the cpu executes the trap instruction, and can be always acknowledged. ? trap instruction format: trap vector (where vector is 0 to 1fh) for details of the instruction function, refer to the v850 series architecture user?s manual. 7.4.1 operation if a software exception occurs, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). (4) sets the ep and id bits of the psw. (5) loads the handler address (00000040h or 00000050h) of the software exception routine in the pc, and transfers control. how a software exception is processed is shown below. figure 7-10. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing handler address: 00000040h (vector = 0nh) 00000050h (vector = 1nh)
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 242 7.4.2 restore to restore or return execution from a software exception service routine, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. (1) restores the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. (2) transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 7-11. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 243 7.4.3 ep flag the ep flag in the psw is a status flag used to indicate that exception processing is in progress. it is set when an exception occurs. figure 7-12. ep flag (ep) after reset: 00000020h symbol 31 876543210 psw 0 np ep id sat cy ov s z ep exception processing 0 exception processing is not in progress 1 exception processing is in progress
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 244 7.5 exception trap the exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. in the v850/sc1, v850/sc2, and v850/sc3, an illegal op code exception (ilgop: ilegal opcode trap) is considered as an exception trap. ? illegal op code exception: occurs if the sub op code field of an instruction to be executed next is not a valid op code. 7.5.1 illegal op code definition an illegal op code is defined to be a 32-bit word with bits 5 to 10 = 111111b and bits 23 to 26 = 0011b to 1111b. figure 7-13. illegal op code 15 16 17 23 22 x 21 x 20 xxxxx x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 12 13 1 1 1 1 0 to 1 0 1 x: don ? t care 7.5.2 operation if an exception trap occurs, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code (0060h) to the lower 16 bits (eicc) of ecr. (4) sets the ep and id bits of the psw. (5) loads the handler address (00000060h) for the exception trap routine to the pc, and transfers control. how the exception trap is processed is shown below. figure 7-14. exception trap processing exception trap (ilgop) occurs eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 00000060h cpu processing exception processing
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 245 7.5.3 restore to restore or return execution from the exception trap, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. (1) restores the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. (2) transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 7-15. reti instruction processing reti instruction jump to pc pc psw eipc eipsw psw. ep 1 0 1 0 pc psw fepc fepsw psw. np caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during exception trap processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 246 7.6 priority control 7.6.1 priorities of interrupts and exceptions table 7-3. priorities of interrupts and exceptions reset nmi int trap ilgop reset * * * * nmi int trap ilgop reset: reset nmi: non-maskable interrupt int: maskable interrupt trap: software exception ilgop: illegal op code exception *: item on the left ignores the item above. : item on the left is ignored by the item above. : item above is higher than the item on the left in priority. : item on the left is higher than the item above in priority.
chapter 7 interrupt/exception proc essing f unction user?s manual u15109ej3v0ud 247 7.6.2 multiple interrupt servicing multiple interrupt servicing is a function that allows the nesting of interrupts. if a higher priority interrupt is generated and acknowledged, it will be allowed to stop an interrupt service routine currently in progress. execution of the original routine will resume once the higher priority interrupt routine is completed. if an interrupt with a lower or equal priority is generated and a service routine is currently in progress, the later interrupt will be held pending. multiple interrupt servicing control is performed when interrupts are enabled (id = 0). even in an interrupt servicing routine, multiple interrupt control must be performed while interrupts are enabled (id = 0). if a maskable interrupt or exception is generated in a maskable interrupt or exception service program, eipc and eipsw must be saved. the following example shows the procedure of interrupt nesting. (1) to acknowledge maskable interrupts in service program service program of maskable interrupt or exception (2) to generate exception in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (enables interrupt acknowledgement) ... ... ? di instruction (disables interrupt acknowledgement) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (enables interrupt acknowledgement) ... ? trap instruction ? illegal op code ... ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction acknowledges interrupts such as intp input. acknowledges exceptions such as trap instruction. acknowledges exceptions such as illegal op code.
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 248 priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request in multiple interrupt servicing control. to set a priority level, write values to the xxprn0 to xxprn2 bits of the interrupt request control register (xxicn) corresponding to each maskable interrupt request. at reset, interrupt requests are masked by the xxmkn bit, and the priority level is set to 7 by the xxprn0 to xxprn2 bits. remark xx: identifying name of each peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 ) priorities of maskable interrupts (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been suspended as a result of multiple interrupt servicing is resumed after the interrupt servicing of the higher priority has been completed and the reti instruction has been executed. a pending interrupt request is acknowledged after the current interrupt servicing has been completed and the reti instruction has been executed. caution in a non-maskable interrupt servicing routine (in the time until the reti instruction is executed), maskable interrupts are not acknowledged and held pending.
chapter 7 interrupt/exception proc essing f unction user?s manual u15109ej3v0ud 249 7.7 response time the following table describes the interrupt response time (from interrupt request generation to start of interrupt servicing). figure 7-16. pipeline operation at interrupt request acknowledgement int1 to int4: interrupt acknowledge processing if x : invalid instruction fetch id x : invalid instruction decode interrupt response time ( system clock) internal interrupt external interrupt conditions minimum 11 13 maximum 18 20 time to eliminate noise (2 system clocks) is also necessary for external interrupts, except when: ? in idle/stop mode ? external bus is accessed ? two or more interrupt request non-sample instructions are executed in succession ? access to interrupt control register system clock if id ifx idx ifx ex mem int1 int2 int3 if id ex mem wb int4 wb interrupt request instruction 1 instruction 2 instruction 3 interrupt acknowledge operation instruction (start instruction of interrupt servicing routine) 7 to 14 system clocks 4 system clocks
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 250 7.8 periods in which interrupts are not acknowledged interrupts are acknowledged while an instruction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction. interrupt request non-sample instruction ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (vs. psw) 7.8.1 interrupt request valid timing following ei instruction when an interrupt request is generated (if flag = 1) in the status in which interrupts have been disabled by the di instruction and interrupts are not masked (mk flag = 0), 7 system clocks are required until the interrupt request is acknowledged following execution of the ei instruction (interrupt enable). if the di instruction (interrupt disable) is executed during the 7 system clocks, the interrupt request is not acknowledged by the cpu. therefore, instructions equivalent to 7 system clocks must be inserted as the number of instruction execution clocks after executing the ei instruction (interrupt enable). however, securing 7 system clocks is disabled under the following conditions because an interrupt request is not acknowledged even if 7 system clocks are secured. ? idle/stop mode ? interrupt request non-sampling instruction (instruction to manipulate psd.id bit) ? access to interrupt request control register (xxicn) the following shows an example of program processing.
chapter 7 interrupt/exception proc essing f unction user?s manual u15109ej3v0ud 251 [program processing example] di : ;(mk flag = 0) :; interrupt request generated (if flag = 1) ei ;ei instruction executed nop ;1 system clock nop ;1 system clock nop ;1 system clock note nop ;1 system clock jr lp1 ;3 system clocks (branched to lp1 routine) : lp1 ;lp1 routine di ;after ei instruction executed, executed at the 8th clock by nop x 4 and jr instructions note do not execute the di instruction (psw.id = 1) during this period. remarks 1. in this example, the di instruction is executed at the 8th clock after ei instruction execution, so an interrupt request is acknowledged by the cpu and the interrupt is serviced. 2. this timing does not imply that the interrupt servicing routine instruction is executed at the 8th clock after ei instruction. the interrupt servicing routine instruction is executed 4 system clocks after interrupt request acknowledgement by the cpu. 3. this example indicates the case where an interrupt request is generated (if flag = 1) before the ei instruction is executed. in the case where an interrupt request is generated (if flag = 1) after the ei instruction is executed, the interrupt request is also not acknowledged by the cpu if interrupts are disabled (psw.id = 1) within 7 system clocks after the if flag is set (1).
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 252 figure 7-17. pipeline flow and interrupt request generation timing if id if id if id if id if id if id if id if id if id ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ei nop nop nop nop nop nop nop di if id if id if id if id if id if id if id if id ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ex mem wb ei nop nop nop nop nop nop di (a) when di instruction is executed at 8th system clock after ei instruction execution (interrupt request is acknowledged) (b) when di instruction is executed at 7th system clock after ei instruction execution (interrupt request is not acknowledged) ei signal intrq signal ei signal intrq signal intrq signal generated intrq signal not generated 7.9 bit manipulation instruction of interrupt control register on dma transfer when using the dma function, execute the di instruction before performing bit manipulation of the interrupt control register (xxicn) in the ei status and execute the ei instruction after performing manipulation. alternately, clear (0) the xxif bit at the start of the interrupt servicing routine. when not using the dma function, these manipulations are not required. remark xx: identifying name of each peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 )
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 253 7.10 key interrupt function a key interrupt can be generated by inputting a falling edge to key input pins (kr0 to kr7) by setting the key return mode register (krm). the key return mode register (krm) includes 5 bits. the krm0 bit controls the kr0 to kr3 signals in 4-bit units and the krm4 to krm7 bits control corresponding signals from kr4 to kr7 (arbitrary setting from 4 to 8 bits is possible). this register can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff3d0h <7> <6> <5> <4> 3 2 1 <0> krm krm7 krm6 krm5 krm4 0 0 0 krm0 krmn key return mode control 0 does not detect key return signal 1 detects key return signal caution if the key return mode register (krm) is changed, an interrupt request flag may be set. to avoid setting this flag, change the krm register after disabling interrupts, and then enable interrupts after clearing the interrupt request flag. table 7-4. description of key return detection pin flag pin description krm0 controls kr0 to kr3 signals in 4-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units
chapter 7 interrupt/exception proc essing f unction user ? s manual u15109ej3v0ud 254 figure 7-18. block diagram of key return intkr key return mode register (krm) krm7 krm6 krm5 krm4 000 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0
user?s manual u15109ej3v0ud 255 chapter 8 timer/counter function 8.1 16-bit timer (tm0, tm1, tm7 to tm12) 8.1.1 outline ? 16-bit capture/compare registers: 2 (crn0, crn1) ? independent capture/trigger inputs: 2 (tin0, tin1) ? support of output of capture/match interrupt request signals (inttmn0, inttmn1) ? event input (shared with tin0) via digital noise eliminator and support of edge specifications ? timer output operated by match detection: 1 each (ton) when using the p104/to0, p107/to1, and p100/to7 pins as to0, to1, and to7 (timer output), set the value of port 10 (p10) to 0 (port mode output) and the port 10 mode register (pm10) to 0. when using the p33/to8 pins as to8 (timer output), set the value of port 3 (p3) to 0 (port mode output) and the port 3 mode register (pm3) to 0. when using the p25/to9 pins as to9 (timer output), set the value of port 2 (p2) to 0 (port mode output) and the port 2 mode register (pm2) to 0. when using the p126/to10 and p127/to11 pins as to10 and to11 (timer output), set the value of port 12 (p12) to 0 (port mode output) and the port 12 mode register (pm12) to 0. when using the p155/to12 pins as to12 (timer output), set the value of port 15 (p15) to 0 (port mode output) and the port 15 mode register (pm15) to 0. the ored value of the output of the port and the timer is output. remark n = 0, 1, 7 to 12 8.1.2 function tm0, tm1, and tm7 to tm12 have the following functions: ? interval timer ? ppg output ? pulse width measurement ? external event counter ? square-wave output ? one-shot pulse output the following shows the block diagram.
chapter 8 timer/counter function 256 user ? s manual u15109ej3v0ud figure 8-1. block diagram of tm0, tm1, and tm7 to tm12 internal bus internal bus tin1 noise eliminator count clock note tin0 toen tocn1 lvrn lvsn tocn4 ospen osptn ovfn tmcn1 tmcn2 prescaler mode register n0 (prmn0) prmn1 prmn0 tmcn3 crcn0 crcn1 crcn2 capture/compare control register n (crcn) 16-bit capture/compare register n0 (crn0) output controller 16-bit timer register (tmn) 16-bit capture/compare register n1 (crn1) crcn2 match match clear 16-bit timer mode control register n (tmcn) ton inttmn1 inttmn0 3 timer output control register n (tocn) f xx /2 selector selector selector selector prmn2 prescaler mode register n1 (prmn1) noise eliminator noise eliminator note the count clock is set by the prmn0 and prmn1 registers. remark n = 0, 1, 7 to 12 (1) interval timer generates an interrupt at preset time intervals. (2) ppg output can output a square wave with a frequency and output-pulse width that can be set arbitrarily. (3) pulse width measurement can measure the pulse width of a signal input from an external source. (4) external event counter can measure the number of pulses of a signal input from an external source. (5) square-wave output can output a square-wave of any frequency. (6) one-shot pulse output can output a one-shot pulse with any output pulse width.
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 257 8.1.3 configuration timers 0, 1, and 7 to 12 include the following hardware. table 8-1. configuration of timers 0, 1, and 7 to 12 item configuration timer registers 16 bits 8 (tm0, tm1, tm7 to tm12) registers capture/compare registers: 16 bits 6 (crn0, crn1) timer outputs 8 (to0, to1, to7 to to12) control registers 16-bit timer mode control register n (tmcn) capture/compare control register n (crcn) 16-bit timer output control register n (tocn) prescaler mode registers n0, n1 (prmn0, prmn1) remark n = 0, 1, 7 to 12 (1) 16-bit timer registers 0, 1, 7 to 12 (tm0, tm1, tm7 to tm12) tmn is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of the input clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases (n = 0, 1, 7 to 12): <1> at reset input <2> if tmcn3 and tmcn2 are cleared <3> if the valid edge of tin0 is input in the clear & start mode entered by inputting the valid edge of tin0 <4> if tmn and crn0 match in the clear & start mode entered on a match between tmn and crn0 <5> if osptn is set or if the valid edge of tin0 is input in the one-shot pulse output mode
chapter 8 timer/counter function 258 user ? s manual u15109ej3v0ud (2) capture/compare register n0 (cr00, cr10, cr70 to cr120) crn0 is a 16-bit register that functions as both a capture register and a compare register. whether this register functions as a capture or compare register is specified by using bit 0 (crcn0) of the crcn register (n = 0, 1, 7 to 12). (a) when using crn0 as compare register the value set to crn0 is continually compared with the count value of the tmn register. when the values of the two match, an interrupt request (inttmn0) is generated. when tmn is used as an interval timer, crn0 can also be used as the register that holds the interval time (n = 0, 1, 7 to 12). (b) when using crn0 as capture register the valid edge of the tin0 or tin1 pin can be selected as a capture trigger. the valid edge for tin0 or tin1 is set by using the prmn0 register. when the valid edge for the tin0 pin is specified as the capture trigger, refer to table 8-2 . when the valid edge for the tin1 pin is specified as the capture trigger, refer to table 8-3 (n = 0, 1, 7 to 12). table 8-2. valid edge of tin0 pin and capture trigger of crn0 esn01 esn00 valid edge of tin0 pin crn0 capture trigger 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges no capture operation remark n = 0, 1, 7 to 12 table 8-3. valid edge of tin1 pin and capture trigger of crn0 esn11 esn10 valid edge of tin1 pin crn0 capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges remark n = 0, 1, 7 to 12 crn0 is set using a 16-bit memory manipulation instruction. when used as a compare register, crn0 can be read/written, but when used as a capture register, crn0 can only be read. reset input sets crn0 to 0000h. caution in the clear & start mode entered on a match between tmn and crn0, set crn0 to a value other than 0000h. in the free-running mode or the tin0 valid edge clear mode, however, an interrupt request (inttmn0) is generated after an overflow (ffffh) when crn0 is set to 0000h.
chapter 8 timer/counter function user?s manual u15109ej3v0ud 259 (3) capture/compare register n1 (cr01, cr11, cr71 to cr121) this is a 16-bit register that can be used as both a capture register and a compare register. whether it is used as a capture register or compare register is specified by bit 2 (crcn2) of the crcn register (n = 0, 1, 7 to 12). (a) when using crn1 as compare register the value set to crn1 is continually compared with the count value of tmn. when the values of the two match, an interrupt request (inttmn1) is generated (n = 0, 1, 7 to 12). (b) when using crn1 as capture register the valid edge of the tin1 pin can be selected as a capture trigger. the valid edge of tin1 is specified by using the prmn0 register. when the capture trigger is specified as the valid edge of tin0, the relationship between the tin0 valid edge and the crn1 capture trigger is as follows. table 8-4. valid edge of tin0 pin and capture trigger of crn1 esn01 esn00 tin0 pin valid edge crn1 capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges remark n = 0, 1, 7 to 12 crn1 is set using a 16-bit memory manipulation instruction. when used as a compare register, crn1 can be read/written, but when used as a capture register, crn1 can only be read. reset input sets these registers to 0000h. caution in the clear & start mode entered on a match between tmn and crn1, set crn1 to a value other than 0000h. in the free-running mode or the tin0 valid edge clear mode, however, an interrupt request (inttmn1) is generated after an overflow (ffffh) when crn1 is set to 0000h.
chapter 8 timer/counter function 260 user ? s manual u15109ej3v0ud 8.1.4 timer 0, 1, 7 to 12 control registers timers 0, 1, and 7 to 12 are controlled by the following registers. ? 16-bit timer mode control register n (tmcn) ? capture/compare control register n (crcn) ? 16-bit timer output control register n (tocn) ? prescaler mode registers n0, n1 (prmn0, prmn1) remark n = 0, 1, 7 to 12 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) tmcn specifies the operation mode of the 16-bit timer; and the clear mode, output timing, and overflow detection of 16-bit timer register n. tmcn is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears tmc0, tmc1, and tmc7 to tmc12 to 00h. caution 16-bit timer register n starts operating when bits tmcn2 and tmcn3 are set to values other than 0, 0 (operation stop mode). to stop the operation, set bits tmcn2 and tmcn3 to 0, 0.
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 261 after reset: 00h r/w address: tmc0: fffff208h tmc1: fffff218h tmc7: fffff3a8h tmc8: fffff398h tmc9: fffff3b8h tmc10: fffff0d8h tmc11: fffff0e8h tmc12: fffff0f8h 7654321<0> tmcn 0 0 0 0 tmcn3 tmcn2 tmcn1 ovfn (n = 0, 1, 7 to 12) tmcn3 tmcn2 tmcn1 selects operation mode and clear mode selects ton output timing generation of interrupt 000 001 operation stops (tmn is cleared to 0) not affected does not generate 0 1 0 match between tmn and crn0 or match between tmn and crn1 011 free-running mode match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 1 0 0 match between tmn and crn0 or match between tmn and crn1 101 clears and starts at valid edge of tin0 match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 1 1 0 match between tmn and crn0 or match between tmn and crn1 111 clears and starts on match between tmn and crn0 match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 generates on match between tmn and crn0 and match between tmn and crn1 ovfn detection of overflow of 16-bit timer register n 0 does not overflow 1overflows cautions 1. when a bit other than the ovfn flag is written, be sure to stop the timer operation. 2. the valid edge of the tin0 pin is set using prescaler mode register n0 (prmn0). 3. when a mode in which the timer is cleared and started on a match between tmn and crn0 is selected, the ovfn flag is set to 1 when the count value of tmn changes from ffffh to 0000h with crn0 set to ffffh. 4. always set bits 7 to 4 to 0. remark ton: output pin of timer n tin0: input pin of timer n tmn: 16-bit timer register n crn0: compare register n0 crn1: compare register n1
chapter 8 timer/counter function 262 user ? s manual u15109ej3v0ud (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) crcn controls the operation of capture/compare register n (crn0 and crn1). crcn is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears crc0, crc1, and crc7 to crc12 to 00h. after reset: 00h r/w address: crc0: fffff20ah crc1: fffff21ah crc7: fffff3aah crc8: fffff39ah crc9: fffff3bah crc10: fffff0dah crc11: fffff0eah crc12: fffff0fah 76543210 crcn 0 0 0 0 0 crcn2 crcn1 crcn0 (n = 0, 1, 7 to 12) crcn2 selects operation mode of crn1 0 operates as compare register 1 operates as capture register crcn1 selects capture trigger of crn0 0 captured at valid edge of tin1 1 captured in reverse phase of valid edge of tin0 crcn0 selects operation mode of crn0 0 operates as compare register 1 operates as capture register cautions 1. before setting crcn, be sure to stop the timer operation. 2. when the mode in which the timer is cleared and started on a match between tmn and crn0 is selected by 16-bit timer mode control register n (tmcn), do not specify crn0 as a capture register. 3. when both the rising edge and falling edge are specified for the tin0 valid edge, the capture operation does not work. 4. for the capture trigger, a pulse longer than twice the count clock selected by prescaler mode registers 0n, 1n (prm0n, prm1n) is required for the signals from tin0 and t2n1 to perform the capture operation correctly. 5. always set bits 7 to 3 to 0. (3) 16-bit timer output control registers 0, 1, 7 to 12 (toc0, toc1, toc7 to toc12) tocn controls the operation of the timer n output controller by setting or resetting the r-s flip-flop (lv0), enabling or disabling reverse output, enabling or disabling output of timer n, enabling or disabling one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software. tocn is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears toc0, toc1, and toc7 to toc12 to 00h.
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 263 after reset: 00h r/w address: toc0: fffff20ch toc1: fffff21ch toc7: fffff3ach toc8: fffff39ch toc9: fffff3bch toc10: fffff0dch toc11: fffff0ech toc12: fffff0fch 7 <6> <5> 4 <3> <2> 1 <0> tocn 0 osptn ospen tocn4 lvsn lvrn tocn1 toen (n = 0, 1, 7 to 12) osptn controls output trigger of one-shot pulse by software 0 no one-shot pulse trigger 1 uses one-shot pulse trigger ospen controls one-shot pulse output operation 0 successive pulse output 1 one-shot pulse output tocn4 controls timer output f/f on match between crn1 and tmn 0 disables reverse timer output f/f 1 enables reverse timer output f/f lvsn lvrn sets status of timer output f/f of timer n 0 0 not affected 0 1 resets timer output f/f (0) 1 0 sets timer output f/f (1) 1 1 setting prohibited tocn1 controls timer output f/f on match between crn0 and tmn or valid edge of tin0 0 disables reverse timer output f/f 1 enables reverse timer output f/f toen controls output of timer n 0 disables output (output is fixed to 0 level) 1 enables output note the one-shot pulse output operates only in the free-running mode and in the clear & start mode entered upon the tin0 valid edge. cautions 1. before setting tocn, be sure to stop the timer operation. 2. lvsn and lvrn are 0 when read after data has been set to them. 3. osptn is 0 when read because it is automatically cleared after data has been set. 4. do not set osptn (1) for other than one-shot pulse output.
chapter 8 timer/counter function 264 user ? s manual u15109ej3v0ud (4) prescaler mode registers 00, 01 (prm00, prm01) prm0n selects the count clock of the 16-bit timer (tm0) and the valid edges of the ti00 and ti01 inputs. prm00 and prm01 are set by an 8-bit memory manipulation instruction. reset input clears prm00 and prm01 to 00h. after reset: 00h r/w address: fffff20eh 76543210 prm010000000prm02 after reset: 00h r/w address: fffff206h 76543210 prm00 es011 es010 es001 es000 0 0 prm01 prm00 es011 es010 selects valid edge of ti01 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es001 es000 selects valid edge of ti00 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges count clock selection f prm02 prm01 prm00 count clock 20 mhz 18.87 mhz 16 mhz 000f /2 100 ns 0.5 ns 125 ns 001f /16 800 ns 848 s1 s 0 1 0 intwtni ??? 0 1 1 ti00 valid edge ??? 100f /4 200 ns 212 ns 250 ns 101f /64 3.2 s3.4 s4 s 110f /256 12.8 s 13.6 s 16 s 1 1 1 setting prohibited ??? note a pulse longer than twice the internal clock (f /2) is required for an external clock.
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 265 cautions 1. when selecting the valid edge of ti00 as the count clock, do not specify the valid edge of ti00 to clear and start the timer and as a capture trigger. 2. before setting data to prm00 and prm01, always stop the timer operation. 3. if the 16-bit timer (tm0) operation is enabled by specifying the rising edge or both edges as the valid edge of the ti00 pin while the ti00 or ti01 pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. care is therefore needed when pulling up the ti00 or ti01 pin. however, the rising edge is not detected when operation is enabled after it has been stopped.
chapter 8 timer/counter function 266 user ? s manual u15109ej3v0ud (5) prescaler mode registers 10, 11, 70, 71 (prm10, prm11, prm70, prm71) prm1n selects the count clock of the 16-bit timer (tm1, tm7) and the valid edge of the tin0 and tin1 inputs. prmn0 and prmn1 are set by an 8-bit memory manipulation instruction (n = 1, 7). reset input clears prmn0 and prmn1 to 00h. after reset: 00h r/w address: fffff21eh, fffff3aeh 76543210 prmn10000000prmn2 (n = 1, 7) after reset: 00h r/w address: fffff216h, fffff3a6h 76543210 prmn0 esn11 esn10 esn01 esn00 0 0 prmn1 prmn0 (n = 1, 7) esn11 esn10 selects valid edge of tin1 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges esn01 esn00 selects valid edge of tin0 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges count clock selection f prmn2 prmn1 prmn0 count clock 20 mhz 18.87 mhz 16 mhz 000f /2 100 ns 105 ns 125 ns 001f /4 200 ns 212 ns 250 ns 010f /16 800 ns 848 ns 1 s 0 1 1 tin0 valid edge ??? 100f /32 1.6 s1.7 s2 s 101f /128 6.4 s6.8 s8 s 110f /256 12.8 s 13.6 s 16 s 1 1 1 setting prohibited ??? note a pulse longer than twice the internal clock (f /2) is required for an external clock.
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 267 cautions 1. when selecting the valid edge of tin0 as the count clock, do not specify the valid edge of tin0 to clear and start the timer and as a capture trigger. 2. before setting data to prmn0 and prmn1, always stop the timer operation. 3. if the 16-bit timer (tm1, tm7) operation is enabled by specifying the rising edge or both edges as the valid edge of the tin0 or tin1 pin while the tin0 or tin1 pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. care is therefore needed when pulling up the tin0 or tin1 pin. however, the rising edge is not detected when operation is enabled after it has been stopped (n = 1, 7).
chapter 8 timer/counter function 268 user ? s manual u15109ej3v0ud (6) prescaler mode registers 80, 81, 100, 101, 120, 121 (prm80, prm81, prm100, prm101, prm120, prm121) prm1n selects the count clock of the 16-bit timer (tm8, tm10, tm12) and the valid edge of the tin0 and tin1 inputs. prmn0 and prmn1 are set by an 8-bit memory manipulation instruction (n = 8, 10, 12). reset input clears prmn0 and prmn1 to 00h. after reset: 00h r/w address: fffff39eh, fffff0deh, fffff0feh 76543210 prmn10000000prmn2 (n = 8, 10, 12) after reset: 00h r/w address: fffff396h, fffff0d6h, fffff0f6h 76543210 prmn0 esn11 esn10 esn01 esn00 0 0 prmn1 prmn0 (n = 8, 10, 12) esn11 esn10 selects valid edge of tin1 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges esn01 esn00 selects valid edge of tin0 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges count clock selection f prmn2 prmn1 prmn0 count clock 20 mhz 18.87 mhz 16 mhz 000f /2 100 ns 105 ns 125 ns 001f /4 400 ns 424 ns 250 ns 010f /16 800 ns 848 ns 1 s 0 1 1 tin0 valid edge ??? 100f /32 1.6 s1.7 s2 s 101f /128 6.4 s6.8 s8 s 110f /256 12.8 s 13.6 s 16 s 1 1 1 setting prohibited ??? note a pulse longer than twice the internal clock (f /2) is required for an external clock.
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 269 cautions 1. when selecting the valid edge of tin0 as the count clock, do not specify the valid edge of tin0 to clear and start the timer and as a capture trigger. 2. before setting data to prmn0 and prmn1, always stop the timer operation. 3. if the 16-bit timer (tm8, tm10, tm12) operation is enabled by specifying the rising edge or both edges for the valid edge of the tin0 or tin1 pin while the tin0 or tin1 pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. be careful when pulling up the tin0 or tin1 pin. however, the rising edge is not detected when operation is enabled after it has been stopped (n = 8, 10, 12).
chapter 8 timer/counter function 270 user ? s manual u15109ej3v0ud (7) prescaler mode registers 90, 91, 110, 111 (prm90, prm91, prm110, prm111) prm1n selects the count clock of the 16-bit timer (tm9, tm11) and the valid edge of the tin0 and tin1 inputs. prmn0 and prmn1 are set by an 8-bit memory manipulation instruction (n = 9, 11). reset input clears prmn0 and prmn1 to 00h. after reset: 00h r/w address: fffff3beh, fffff0eeh 76543210 prmn10000000prmn2 (n = 9, 11) after reset: 00h r/w address: fffff3b6h, fffff0e6h 76543210 prmn0 esn11 esn10 esn01 esn00 0 0 prmn1 prmn0 (n = 9, 11) esn11 esn10 selects valid edge of tin1 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges esn01 esn00 selects valid edge of tin0 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges count clock selection f prmn2 prmn1 prmn0 count clock 20 mhz 18.87 mhz 16 mhz 000f /4 200 ns 212 ns 250 ns 001f /8 400 ns 424 ns 500 ns 010f /32 1.6 s1.7 s2 s 0 1 1 tin0 valid edge ??? 100f /64 3.2 s3.4 s4 s 101f /128 6.4 s6.8 s8 s 110f /512 25.6 s 27.1 s 32 s 1 1 1 setting prohibited ??? note a pulse longer than twice the internal clock (f /2) is required for an external clock.
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 271 cautions 1. when selecting the valid edge of tin0 as the count clock, do not specify the valid edge of tin0 to clear and start the timer and as a capture trigger. 2. before setting data to prmn0 and prmn1, always stop the timer operation. 3. if the 16-bit timer (tm9, tm11) operation is enabled by specifying the rising edge or both edges for the valid edge of the tin0 or tin1 pin while the tin0 or tin1 pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. be careful when pulling up the tin0 or tin1 pin. however, the rising edge is not detected when operation is enabled after it has been stopped (n = 9, 11).
chapter 8 timer/counter function 272 user ? s manual u15109ej3v0ud 8.2 16-bit timer (tm0, tm1, tm7 to tm12) operation 8.2.1 operation as interval timer tmn operates as an interval timer when 16-bit timer mode control register n (tmcn) and capture/compare control register n (crcn) are set as shown in figure 8-2 (n = 0, 1). in this case, tmn repeatedly generates an interrupt at the time interval specified by the count value preset to 16- bit capture/compare register n0 (crn0). when the count value of tmn matches the set value of crn0, the value of tmn is cleared to 0, and the timer continues counting. at the same time, an interrupt request signal (inttmn0) is generated. the count clock of the 16-bit timer/event counter can be selected by bits 0 and 1 (prmn0 and prmn1) of prescaler mode register n0 (prmn0) and by bits 0 (prmn2) of prescaler mode register n1 (prmn1). remark n = 0, 1, 7 to 12 figure 8-2. control register settings when tmn operates as interval timer (a) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) tmcn3 tmcn2 tmcn1 ovfn tmcn0000110/10 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 0 crn0 as compare register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the interval timer function. for details, refer to 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) and (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) .
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 273 figure 8-3. configuration of interval timer

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t remarks 1. interval time = (n + 1) t: n = 0001h to ffffh 2. n = 0, 1, 7 to 12
chapter 8 timer/counter function 274 user ? s manual u15109ej3v0ud 8.2.2 ppg output operation tmn can be used for ppg (programmable pulse generator) output by setting 16-bit timer mode control register n (tmcn) and capture/compare control register n (crcn) as shown in figure 8-5. the ppg output function outputs a square-wave from the ton pin with a cycle specified by the count value preset to 16-bit capture/compare register n0 (crn0) and a pulse width specified by the count value preset to 16-bit capture/compare register n1 (crn1). remark n = 0, 1, 7 to 12 figure 8-5. control register settings in ppg output operation (a) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) tmcn3 tmcn2 tmcn1 ovfn tmcn00001100 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0 0 crn0 as compare register crn1 as compare register (c) 16-bit timer output control registers 0, 1, 7 to 12 (toc0, toc1, toc7 to toc12) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00010/10/111 enables ton output. inverts output on match between tmn and crn0. specifies initial value of ton output f/f. inverts output on match between tmn and crn1. disables one-shot pulse output. cautions 1. make sure that crn0 and crn1 are set to 0000h < crn1 < crn0 ffffh. 2. ppg output sets the pulse cycle to (crn0 setup value + 1). the duty ratio is (crn1 setup value + 1)/(crn0 setup value + 1). remark n = 0, 1, 7 to 12 : don ? t care
chapter 8 timer/counter function user?s manual u15109ej3v0ud 275 figure 8-6. configuration of ppg output f xx /2 tin0 ton 16-bit capture/compare register n1 (crn1) 16-bit capture/compare register n0 (crn0) count clock note selector noise eliminator 16-bit timer register n (tmn) clear circuit output controller note the count clock is set by the prmn0 and prmn1 registers. remarks 1. ? ? indicates a signal that can be directly connected to ports. 2. n = 0, 1, 7 to 12 figure 8-7. ppg output operation timing t 0000h 0000h 0001h 0001h m-1 ton n m m n-1 n count clock tmn count value value loaded to crn0 value loaded to crn1 clear count starts pulse width: m t 1 cycle: n t remarks 1. 0000h < m < n ffffh 2. n = 0, 1, 7 to 12
chapter 8 timer/counter function 276 user ? s manual u15109ej3v0ud 8.2.3 pulse width measurement 16-bit timer register n (tmn) can be used to measure the pulse widths of the signals input to the tin0 and tin1 pins. measurement can be carried out with tmn used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the tin0 pin. (1) pulse width measurement with free-running counter and one capture register if the edge specified by prescaler mode register n0 (prmn0) is input to the tin0 pin when 16-bit timer register n (tmn) is used as a free-running counter (refer to figure 8-8 ), the value of tmn is loaded to 16-bit capture/compare register n1 (crn1), and an external interrupt request signal (inttmn1) is set. the edge is specified using bits 6 and 7 (esn10 and esn11) of prescaler mode register n0 (prmn0). the rising, falling, or both rising and falling edges can be selected. the valid edge is detected through sampling at a count clock cycle selected by prescaler mode registers n0 and n1 (prmn0, prmn1), and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. figure 8-8. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) tmcn3 tmcn2 tmcn1 ovfn tmcn0000010/10 free-running mode (b) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 1 0/1 0 crn0 as compare register crn1 as capture register remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) and (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) . 2. n = 0, 1, 7 to 12
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 277 figure 8-9. configuration for pulse width measurement with free-running counter

!"# note the count clock is set by the prmn0 and prmn1 registers. remarks 1. ?? indicates a signal that can be directly connected to ports. 2. n = 0, 1, 7 to 12 figure 8-10. timing of pulse width measurement with free-running counter and one capture register (with both edges specified) "
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chapter 8 timer/counter function 278 user ? s manual u15109ej3v0ud (2) measurement of two pulse widths with free-running counter the pulse widths of the two signals respectively input to the tin0 and tin1 pins can be measured when 16-bit timer register n (tmn) is used as a free-running counter (refer to figure 8-11 ). when the edge specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0) is input to the tin0 pin, the value of tmn is loaded to 16-bit capture/compare register n1 (crn1) and an external interrupt request signal (inttmn1) is set. when the edge specified by bits 6 and 7 (esn10 and esn11) of prmn0 is input to the tin1 pin, the value of tmn is loaded to 16-bit capture/compare register n0 (crn0), and an external interrupt request signal (inttmn0) is set. the edges of the tin0 and tin1 pins are specified by bits 4 and 5 (esn00 and esn01) and bits 6 and 7 (esn10 and esn11) of prmn0, respectively. the rising, falling, or both rising and falling edges can be specified. the valid edge is detected through sampling at a count clock cycle selected by prescaler mode registers n0 and n1 (prmn0, prmn1), and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. remark n = 0, 1, 7 to 12 figure 8-11. control register settings for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) tmcn3 tmcn2 tmcn1 ovfn tmcn0000010/10 free-running mode (b) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 1 0 1 crn0 as capture register captures valid edge of tin1 pin to crn0. crn1 as capture register remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) and (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) . 2. n = 0, 1, 7 to 12
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 279 ? capture operation (free-running mode) the following figure illustrates the operation of the capture register when the capture trigger is input. figure 8-12. crn1 capture operation with rising edge specified , ? ? % ? +
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chapter 8 timer/counter function 280 user ? s manual u15109ej3v0ud (3) pulse width measurement with free-running counter and two capture registers when 16-bit timer register n (tmn) is used as a free-running counter (refer to figure 8-14 ), the pulse width of the signal input to the tin0 pin can be measured. when the edge specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0) is input to the tin0 pin, the value of tmn is loaded to 16-bit capture/compare register n1 (crn1), and an external interrupt request signal (inttmn1) is set. the value of tmn is also loaded to 16-bit capture/compare register n0 (crn0) when an edge that is the reverse of the one that triggers capturing to crn1 is input. the edge of the tin0 pin is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n (prmn0). the rising or falling edge can be specified. the valid edge of tin0 is detected through sampling at a count clock cycle selected by prescaler mode registers n0 and n1 (prmn0, prmn1), and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. caution if the valid edge of the tin0 pin is specified to be both the rising and falling edges, capture/compare register n0 (crn0) cannot perform a capture operation. remark n = 0, 1, 7 to 12 figure 8-14. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) tmcn3 tmcn2 tmcn1 ovfn tmcn0000010/10 free-running mode (b) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 1 1 1 crn0 as capture register captures to crn0 at edge reverse to valid edge of tin0 pin. crn1 as capture register remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) and (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) . 2. n = 0, 1, 7 to 12
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 281 figure 8-15. timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) * ? * ' ? *,*% *+ ? *% !"# ' ' * * &
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) d0 + 1 d1 + 1 ' ####' *% d2 + 1 *+ * * *% *+ remark n = 0, 1, 7 to 12 (4) pulse width measurement by restarting when the valid edge of the tin0 pin is detected, the pulse width of the signal input to the tin0 pin can be measured by clearing 16-bit timer register n (tmn) once and then resuming counting after loading the count value of tmn to 16-bit capture/compare register n1 (crn1) (see figure 8-17 ). the edge is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). the rising or falling edge can be specified. the valid edge is detected through sampling at a count clock cycle selected by prescaler mode registers n0 and n1 (prmn0, prmn1) and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. caution if the valid edge of the tin0 pin is specified to be both the rising and falling edges, capture/compare register n0 (crn0) cannot perform a capture operation. remark n = 0, 1, 7 to 12
chapter 8 timer/counter function 282 user ? s manual u15109ej3v0ud figure 8-16. control register settings for pulse width measurement by restarting (a) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) tmcn3 tmcn2 tmcn1 ovfn tmcn0000100/10 clears and starts at valid edge of tin0 pin. (b) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 1 1 1 crn0 as capture register captures to crn0 at edge reverse to valid edge of tin0. crn1 as capture register remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) and (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) . 2. n = 0, 1, 7 to 12 figure 8-17. timing of pulse width measurement by restarting (with rising edge specified) t (d1+1) t (d2+1) t d0 d0 d2 d1 d1 d2 0001h 0000h 0001h 0000h 0001h 0000h inttmn1 value loaded to crn1 value loaded to crn0 tin0 pin input tmn count value count clock remark n = 0, 1, 7 to 12
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 283 8.2.4 operation as external event counter tmn can be used as an external event counter that counts the number of clock pulses input to the tin0 pin from an external source by using 16-bit timer register n (tmn). each time the valid edge specified by prescaler mode register n0 (prmn0) is input, tmn is incremented. when the count value of tmn matches the value of 16-bit capture/compare register n0 (crn0), tmn is cleared to 0, and an interrupt request signal (inttmn0) is generated. the edge is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). the rising, falling, or both rising and falling edges can be specified. the valid edge is detected through sampling at a count clock cycle of f /2, and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. remark n = 0, 1, 7 to 12 figure 8-18. control register settings in external event counter mode (a) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) tmcn3 tmcn2 tmcn1 ovfn tmcn0000110/10 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 0 crn0 as compare register remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the external event counter function. for details, refer to 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) and (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) . 2. n = 0, 1, 7 to 12
chapter 8 timer/counter function 284 user ? s manual u15109ej3v0ud figure 8-19. configuration of external event counter

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chapter 8 timer/counter function user ? s manual u15109ej3v0ud 285 8.2.5 operation as square-wave output tmn can be used to output a square-wave with any frequency at an interval specified by the count value preset to 16-bit capture/compare register n0 (crn0). by setting bits 0 (toen) and 1 (tocn1) of 16-bit timer output control register n (tocn) to 1, the output status of the ton pin is inverted at an interval specified by the count value preset to crn1. in this way, a square wave with any frequency can be output. remark n = 0, 1, 7 to 12 figure 8-21. control register settings in square-wave output mode (a) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) tmcn3 tmcn2 tmcn1 ovfn tmcn00001100 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 1 crn0 as compare register (c) 16-bit timer output control registers 0, 1, 7 to 12 (toc0, toc1, toc7 to toc12) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00000/10/111 enables ton output. inverts output on match between tmn and crn0. specifies initial value of ton output f/f. does not invert output on match between tmn and crn1. disables one-shot pulse output.
chapter 8 timer/counter function 286 user ? s manual u15109ej3v0ud remarks 1. 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the square-wave output function. for details, refer to 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) and (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) . 2. n = 0, 1, 7 to 12 figure 8-22. timing of square-wave output operation &
%' ' ' ? ? ! %' ' ' ' remark n = 0, 1, 7 to 12 8.2.6 operation as one-shot pulse output tmn can output a one-shot pulse in synchronization with a software trigger and an external trigger (tin0 pin input). (1) one-shot pulse output via software trigger a one-shot pulse can be output from the ton pin by setting 16-bit timer mode control register n (tmcn), capture/compare control register n (crcn), and 16-bit timer output control register n (tocn) as shown in figure 8-23, and by setting bit 6 (osptn) of tocn by software. by setting osptn to 1, the 16-bit timer/event counter is cleared and started, and its output is asserted active at the count value (n) preset to 16-bit capture/compare register n1 (crn1). after that, the output is deasserted inactive at the count value (m) preset to 16-bit capture/compare register n0 (crn0) . even after the one-shot pulse has been output, tmn continues its operation. to stop tmn, tmcn must be reset to 00h. note this is an example when n < m. when n > m, the output becomes active at the crn0 value and inactive at the crn1 value. caution do not set osptn to 1 while the one-shot pulse is being output. to output the one-shot pulse again, wait until the current one-shot pulse output ends. remark n = 0, 1, 7 to 12
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 287 figure 8-23. control register settings for one-shot pulse output via software trigger (a) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) tmcn3 tmcn2 tmcn1 ovfn tmcn00000100 free-running mode (b) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0 0/1 0 crn0 as compare register crn1 as compare register (c) 16-bit timer output control registers 0, 1, 7 to 12 (toc0, toc1, toc7 to toc12) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00110/10/111 enables ton output. inverts output on match between tmn and crn0. specifies initial value of ton output f/f. inverts output on match between tmn and crn1. sets one-shot pulse output mode. set to 1 for output. caution do not set crn0 and crn1 to 0000h. remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the square-wave output function. for details, refer to 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) and (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) . 2. n = 0, 1, 7 to 12
chapter 8 timer/counter function 288 user ? s manual u15109ej3v0ud figure 8-24. timing of one-shot pulse output operation via software trigger &
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' caution 16-bit timer register n starts operating as soon as tmcn2 and tmcn3 are set to values other than 0, 0 (operation stop mode). remark n = 0, 1, 7 to 12 n < m (2) one-shot pulse output via external trigger a one-shot pulse can be output from the ton pin by setting 16-bit timer mode control register n (tmcn), capture/compare control register n (crcn), and 16-bit timer output control register n (tocn) as shown in figure 8-25, and by using the valid edge of the tin0 pin as an external trigger. the valid edge of the tin0 pin is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). the rising, falling, or both rising and falling edges can be specified. when the valid edge of the tin0 pin is detected, the 16-bit timer/event counter is cleared and started, and the output is asserted active at the count value (n) preset to 16-bit capture/compare register n1 (crn1). after that, the output is deasserted inactive at the count value (m) preset to 16-bit capture/compare register n0 (crn0) . note this is an example when n < m. when n > m, the output becomes active at the crn0 value and inactive at the crn1 value. caution if the external trigger occurs while a one-shot pulse is being output, the 16-bit timer/counter clears & starts and the one-shot pulse is output again. remark n = 0, 1, 7 to 12
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 289 figure 8-25. control register settings for one-shot pulse output via external trigger (a) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) tmcn3 tmcn2 tmcn1 ovfn tmcn00001000 clears and starts at valid edge of tin0 pin. (b) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0 0/1 0 crn0 as compare register crn1 as compare register (c) 16-bit timer output control registers 0, 1, 7 to 12 (toc0, toc1, toc7 to toc12) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00110/10/111 enables ton output. inverts output on match between tmn and crn0. specifies initial value of ton output f/f. inverts output on match between tmn and crn1. sets one-shot pulse output mode. caution do not set crn0 and crn1 to 0000h. remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the square-wave output function. for details, refer to 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) and (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) . 2. n = 0, 1, 7 to 12
chapter 8 timer/counter function 290 user ? s manual u15109ej3v0ud figure 8-26. timing of one-shot pulse output operation via external trigger (with rising edge specified) &
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1' ' ? % caution 16-bit timer register n starts operating as soon as tmcn2 and tmcn3 are set to values other than 0, 0 (operation stop mode). remark n = 0, 1, 7 to 12 n > m
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 291 8.2.7 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because 16-bit timer register n (tmn) is started asynchronously to the count pulse. figure 8-27. start timing of 16-bit timer register n
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remark n = 0, 1, 7 to 12 (2) 16-bit capture/compare register setting (in the clear & start mode entered on match between tmn and crn0) set 16-bit capture/compare registers n0 and n1 (crn0, crn1) to a value other than 0000h (a 1-pulse count operation is disabled when these registers are used as event counters). (3) setting compare register during timer count operation if the value to which the current value of 16-bit capture/compare register n0 (crn0) has been changed is less than the value of 16-bit timer register n (tmn), tmn continues counting, overflows, and starts counting again from 0. if the new value of crn0 (m) is less than the old value (n), the timer must be reset and restarted after the value of crn0 has been changed. figure 8-28. timing after changing compare register during timer count operation &
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chapter 8 timer/counter function 292 user ? s manual u15109ej3v0ud (4) data hold timing of capture register if the valid edge is input to the tin0 pin while 16-bit capture/compare register n1 (crn1) is being read, crn1 performs the capture operation, but this capture value is not guaranteed. however, the interrupt request signal (inttmn1) is set as a result of detection of the valid edge. figure 8-29. data hold timing of capture register &

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remark n = 0, 1, 7 to 12 (5) setting valid edge before setting the valid edge of the tin0 pin, stop the timer operation by resetting bits 2 and 3 (tmcn2 and tmcn3) of 16-bit timer mode control register n to 0, 0. set the valid edge by using bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). remark n = 0, 1, 7 to 12 (6) re-triggering one-shot pulse (a) one-shot pulse output via software when a one-shot pulse is being output, do not set osptn to 1. do not output the one-shot pulse again until the current one-shot pulse output ends. (b) one-shot pulse output via external trigger if the external trigger occurs while a one-shot pulse is being output, the 16-bit timer/event counter clears and starts and the one-shot pulse is output again. (c) on-shot pulse output function when using a software trigger for one-shot pulse output of timers 0, 1, and 7 to 12, do not change the level of the tin0 pin or its alternate-function pin. the reason for this is that the timer is inadvertently cleared and started at the level of the tin0 pin pr its alternate-function pin and pulses are output at an unintended timing because the external trigger is valid. remark n = 0, 1, 7 to 12
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 293 (7) operation of ovfn flag (a) ovfn flag set the ovfn flag is set to 1 in the following case in addition to when tmn register overflows: selection of mode in which tm0 is cleared and started on a match between tmn and crn0. crn0 is set to ffffh. when tmn is cleared from ffffh to 0000h on a match with crn0. figure 8-30. operation timing of ovfn flag
' ####' !"# ###3' ####' ' remark n = 0, 1, 7 to 12 (b) clear ovfn flag even if the ovfn flag is cleared before the next count clock is counted (before tmn becomes 0001h) after tmn has overflowed, the ovfn flag is set again and the clear becomes invalid. remark n = 0, 1, 7 to 12 (8) conflict operation (a) if the read period and capture trigger input conflict when 16-bit capture/compare registers n0 and n1 (crn0, crn1) are used as capture registers, if the read period and capture trigger input conflict, the capture trigger has priority. the read data of crn0 and crn1 is undefined. (b) if the match timings of the write period and tmn conflict when 16-bit capture/compare registers n0 and n1 (crn0, crn1) are used as capture registers, because match detection cannot be performed correctly if the match timings of the write period and 16-bit timer register n (tmn) conflict, do not write to crn0 and crn1 close to the match timing. remark n = 0, 1, 7 to 12
chapter 8 timer/counter function 294 user ? s manual u15109ej3v0ud (9) timer operation (a) crn1 capture even if 16-bit timer register n (tmn) is read, a capture to 16-bit capture/compare register n1 (crn1) is not performed. (b) acknowledgement of tin0 and tin1 pins when the timer is stopped, input signals to the tin0 and tin1 pins are not acknowledged, regardless of the cpu operation. (c) one-shot pulse output the one-shot pulse output operates correctly only in free-running mode or in clear & start mode entered upon the valid edge of the tin0 pin. the one-shot pulse cannot be output in the clear & start mode entered on a match of tmn and crn0 because an overflow does not occur. remark n = 0, 1, 7 to 12 (10) capture operation (a) if the valid edge of tin0 is specified for the count clock when the valid edge of tin0 is specified for the count clock, the capture register with tin0 specified as a trigger will not operate correctly. (b) if both rising and falling edges are selected as valid edge of tin0 if both rising and falling edges are selected as the valid edge of tin0, a capture operation is not performed. (c) to capture the signals correctly from tin0 and tin1 the capture trigger needs a pulse longer than twice the count clock selected by prescaler mode registers n0 and n1 (prmn0, prmn1) in order to correctly capture the signals from tin1 and tin0. (d) interrupt request input although a capture operation is performed at the falling edge of the count clock, interrupt request inputs (inttmn0, inttmn1) are generated at the rising edge of the next count clock. remark n = 0, 1, 7 to 12 (11) compare operation (a) when rewriting crn0 and crn1 during timer operation when rewriting 16-bit timer capture/compare registers n0 and n1 (crn0, crn1), if the value is close to or larger than the timer value, the match interrupt request generation or clear operation may not be performed correctly. (b) when crn0 and crn1 are set to compare mode when crn0 and crn1 are set to compare mode, they do not perform a capture operation even if a capture trigger is input. remark n = 0, 1, 7 to 12
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 295 (12) edge detection (a) when the tin0 or tin1 pin is high level immediately after a system reset when the tin0 or tin1 pin is high level immediately after a system reset, if the valid edge of the tin0 or tin1 pin is specified as the rising edge or both rising and falling edges, and the operation of 16-bit timer/counter n (tmn) is then enabled, the rising edge will be detected immediately. care is therefore needed when the tin0 or tin1 pin is pulled up. however, when operation is enabled after being stopped, the rising or falling edge is not detected. (b) sampling clock for noise elimination the sampling clock for noise elimination differs depending on whether the tin0 valid edge is used as a count clock or a capture trigger. the former is sampled by f /2, and the latter is sampled by the count clock selected using prescaler mode registers n0 or n1 (prmn0, prmn1). detecting the valid edge can eliminate short pulse width noise because a capture operation is performed only after the valid edge is sampled and a valid level is detected twice. remark n = 0, 1, 7 to 12
chapter 8 timer/counter function 296 user ? s manual u15109ej3v0ud 8.3 16-bit timer (tm5, tm6) 8.3.1 functions tm5 and tm6 have the following functions. ? pwm output with 16-bit resolution ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square-wave output with 16-bit resolution figure 8-31. block diagram of tm5 and tm6

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chapter 8 timer/counter function user ? s manual u15109ej3v0ud 297 8.3.2 configuration timer n includes the following hardware. table 8-5. configuration of timers 5 and 6 item configuration timer registers 16-bit counters 5, 6 (tm5, tm6) registers 16-bit compare registers 5, 6 (cr5, cr6) timer outputs to5, to6 control registers timer clock select registers 50, 51, 60, and 61 (tcl50, tcl51, tcl60, and tcl61) 8-bit timer mode control registers 50 and 60 (tmc50, tmc60) (1) 16-bit counters 5, 6 (tm5, tm6) tmn is a 16-bit read-only register that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. when the count is read out during operation, the count clock input temporarily stops and the count is read at that time. in the following cases, the count becomes 0000h. (1) when reset is input. (2) when tcen is cleared. (3) when tmn and crn match in the clear & start mode that is entered when tmn and crn0 match. remark n = 5, 6 (2) 16-bit compare registers 5, 6 (cr5, cr6) the value set in crn is always compared to the count in 16-bit counter n (tmn). if the two values match, an interrupt request (inttmn) is generated (except in the pwm mode). remark n = 5, 6
chapter 8 timer/counter function 298 user ? s manual u15109ej3v0ud 8.3.3 timer n control registers timer n is controlled by the following registers. ? timer clock select registers n0, n1 (tcln0, tcln1) ? 16-bit timer mode control register n (tmcn) (1) timer clock select registers 50, 51, 60, 61 (tcl50, tcl51, tcl60, tcl61) these registers set the count clock of timer n. tcln0 and tcln1 are set by an 8-bit memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r/w address: fffff33eh 76543210 tcl510000000tc l503 after reset: 00h r/w address: fffff334h 76543210 tcl5000000tc l502 tcl501 tcl500 count clock selection f tcl503 tcl502 tcl501 tcl500 count clock 20 mhz 18.87 mhz 16 mhz 0 0 0 0 ti5 falling edge ??? 0 0 0 1 ti5 rising edge ??? 0010f /2 100 ns 105 ns 125 ns 0011f /4 200 ns 212 ns 250 ns 0100f /8 400 ns 424 ns 500 ns 0101f /16 800 ns 848 ns 1 s 0110f /64 3.2 s3.4 s4 s 0111f (subclock) 30.5 s 30.5 s 30.5 s 1 0 0 0 setting prohibited ??? 1 0 0 1 setting prohibited ??? 1010f /32 1.6 s1.7 s2 s 1011f /128 6.4 s6.8 s8 s 1 1 0 0 setting prohibited ??? 1 1 0 1 setting prohibited ??? 1 1 1 0 setting prohibited ??? 1 1 1 1 setting prohibited ??? cautions 1. to overwrite tcl50 and tcl51 with different data, temporarily stop the timer first. 2. always set bits 3 to 7 of tcl50 and bits 1 to 7 of tcl51 to 0.
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 299 after reset: 00h r/w address: fffff28eh 76543210 tcl610000000tc l603 after reset: 00h r/w address: fffff284h 76543210 tcl6000000tc l602 tcl601 tcl600 count clock selection f tcl603 tcl602 tcl601 tcl600 count clock 20 mhz 18.87 mhz 16 mhz 0 0 0 0 ti6 falling edge ??? 0 0 0 1 ti6 rising edge ??? 0010f /2 100 ns 105 ns 125 ns 0011f /4 200 ns 212 ns 250 ns 0100f /8 400 ns 424 ns 500 ns 0101f /16 800 ns 848 ns 1 s 0110f /64 3.2 s3.4 s4 s 0111f /256 12.8 s 13.6 s 16 s 1 0 0 0 setting prohibited ??? 1 0 0 1 setting prohibited ??? 1010f /32 1.6 s1.7 s2 s 1011f /128 6.4 s6.8 s8 s 1 1 0 0 setting prohibited ??? 1 1 0 1 setting prohibited ??? 1 1 1 0 setting prohibited ??? 1 1 1 1 tm0 overflow signal ??? cautions 1. to overwrite tcl60 and tcl61 with different data, temporarily stop the timer first. 2. always set bits 3 to 7 of tcl60 and bits 1 to 7 of tcl61 to 0.
chapter 8 timer/counter function 300 user ? s manual u15109ej3v0ud (2) 16-bit timer mode control registers 50, 60 (tmc50, tmc60) the tmcn0 register makes the following five settings. (1) controls the counting by 16-bit counter n (tmn) (2) selects the operating mode of 16-bit counter n (tmn) (3) sets the state of the timer output flip-flop (4) controls the timer flip-flop or selects the active level in the pwm (free-running) mode (5) controls timer output tmcn0 is set by an 8-bit or 1-bit memory manipulation instruction. reset input sets these registers to 04h (although the state of the hardware is initialized to 04h, 00h is readout when reading). remark n = 5, 6
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 301 after reset: 04h r/w address: tmc50 fffff336h tmc60 fffff286h <7> 6 5 4 <3> <2> 1 <0> tmcn0 tcen0 tmcn06 0 0 lvsn0 lvrn0 tmcn01 toen0 (n = 5, 6) tcen0 tmn count operation control 0 counting is disabled after the counter is cleared to 0 (prescaler disabled) 1 start count operation tmcn06 tmn operating mode selection 0 clear & start mode entered when tmn and crn match 1 pwm (free-running) mode lvsn0 lvrn0 setting state of timer output flip-flop 0 0 not change 0 1 reset timer output flip-flop (0) 1 0 set timer output flip-flop (1) 1 1 setting prohibited other than pwm (free-running) mode (tmcn06 = 0) pwm (free-running) mode (tmcn06 = 1) tmcn01 controls timer f/f selects active level 0 disable inversion operation active high 1 enable inversion operation active low toen0 timer output control 0 disable output (port mode) 1 enable output cautions 1. when using the timer output pin (ton), set the port value to 0 (port mode output). an ored value (logical or) of the timer output values is output. 2. since ton and tin are the same alternate-function pin, only one function can be used. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tcen0 = 0. 2. if lvsn0 and lvrn0 are read after setting data, 0 is read.
chapter 8 timer/counter function 302 user ? s manual u15109ej3v0ud 8.4 16-bit timer (tm5, tm6) operation 8.4.1 operation as an interval timer tmn operates as an interval timer that repeatedly generates interrupts at the time interval specified by the count value preset to 16-bit compare register n (crn). when the count value of 16-bit counter n (tmn) matches the set value of crn, the value of tmn is cleared to 0, and the timer continues counting. at the same time, an interrupt request signal (inttmn) is generated. the tmn count clock can be selected by bits 0 to 2 (tcln0 to tcln2) of timer clock select register n0 (tcln0) and by bit 0 (tcln3) of timer clock select register n1 (tcln1) (n = 5, 6). setting method (1) set each register. ? tcln0, tcln1: selects the count clock. ? crn: compare value ? tmcn0: selects the clear and start mode entered when tmn and crn match. (tmcn0 = 0000xxx0b, = don ? t care) (2) when tcen0 = 1 is set, counting starts. (3) when the values of tmn and crn match, inttmn is generated (tmn is cleared to 0000h). (4) inttmn is then repeatedly generated at the same interval. when counting stops, set tcen0 = 0. figure 8-32. timing of interval timer operation (1/2) basic operation &
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chapter 8 timer/counter function user ? s manual u15109ej3v0ud 303 figure 8-32. timing of interval timer operation (2/2) when crn = 0000h 3 ! 0000h 0000h 0000h 0000h 0000h
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chapter 8 timer/counter function 304 user?s manual u15109ej3v0ud 8.4.2 operation as external event counter the external event counter counts the number of external clock pulses that are input to tin. each time the valid edge specified by timer clock select registers n0 and n1 (tcln0, tcln1) is input, tmn is incremented. the edge setting can be selected to be either a rising or falling edge. if the total value of tmn and the value of 16-bit compare register n (crn) match, tmn is cleared to 0 and an interrupt request signal (inttmn) is generated. inttmn is generated each time the tmn value matches the crn value. remark n = 5, 6 figure 8-33. timing of external event counter operation (with rising edge specified) tin tmn count value 0005h 0004h 0003h 0002h 0001h 0000h n ? 1 n crn inttmn n 0000h 0001h 0002h 0003h remark n = 5, 6
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 305 8.4.3 operation as square-wave output a square-wave with any frequency is output at the interval preset to 16-bit compare register n (crn). by setting bit 0 (toen0) of 16-bit timer mode control register n0 (tmcn0) to 1, the output status of ton is inverted at an interval specified by the count value preset to crn. in this way, a square wave of any frequency (duty ratio = 50%) can be output. setting method (1) set the registers. ? set the port latch and port mode register to 0 ? tcln0, tcln1: selects the count clock ? crn: compare value ? tmcn0: clear and start mode entered when tmn and crn match lvsn0 lvrn0 setting state of timer output flip-flop 1 0 high level output 0 1 low level output inversion of timer output flip-flop enabled timer output enabled toen0 = 1 (2) when tcen0 = 1 is set, the counter starts operating. (3) if the values of tmn and crn match, the timer output flip-flop inverts. also, inttmn is generated and tmn is cleared to 0000h. (4) the timer output flip-flop is then inverted at the same interval and a square wave is output from ton. remark n = 5, 6 figure 8-34. square-wave output operation timing 0000h 0000h 0001h 0002h n ? 1 n 0001h 0002h n n ? 1 n 0000h count clock crn ton tmn count value count start note the initial value of ton output can be set with bits 3 and 2 (lvsn0, lvrn0) of the tmcn0 register. remark n = 5, 6
chapter 8 timer/counter function 306 user ? s manual u15109ej3v0ud 8.4.4 operation as 16-bit pwm output by setting bit 6 (tmcn6) of 16-bit timer mode control register n0 (tmcn0) to 1, the timer operates as a pwm output. pulses with the duty ratio determined by the value set to 16-bit compare register n (crn) are output from ton. set the width of the active level of the pwm pulse to crn. the active level can be selected by bit 1 (tmcn01) of tmcn0. the count clock can be selected by bits 0 to 2 (tcln0 to tcln2) of timer clock select register n0 (tcln0) and by bit 0 (tcln3) of timer clock select register n1 (tcln1). the pwm output can be enabled and disabled by bit 0 (toen0) of tmcn0. caution crn can be rewritten only once in one period while in the pwm mode. remark n = 5, 6 (1) basic operation of pwm output setting method (1) set the port latch and port mode register n to 0. (2) set the active level width to 16-bit compare register n (crn). (3) select the count clock using timer clock select register n0, n1 (tcln0, tcln1). (4) set the active level to bit 1 (tmcn01) of tmcn0. (5) if bit 7 (tcen0) of tmcn0 is set to 1, counting starts. to stop counting, set tcen0 to 0. pwm output operation (1) when counting starts, pwm output (output from ton) outputs the inactive level until an overflow occurs. (2) when an overflow occurs, the active level specified in step (1) in the setting method is output. the active level is output until crn and the count value of 16-bit counter n (tmn) match. (3) pwm output after the crn and count values match is at the inactive level until an overflow occurs again. (4) steps (2) and (3) repeat until counting stops. (5) if counting is stopped by tcen0 = 0, pwm output goes to the inactive level. remark n = 5, 6
chapter 8 timer/counter function user ? s manual u15109ej3v0ud 307 (a) basic operation of pwm output figure 8-35. timing of pwm output basic operation (active level = h) ' 3 ! 7&

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chapter 8 timer/counter function 308 user ? s manual u15109ej3v0ud 8.4.5 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because 16-bit counter n (tmn) is started asynchronously to the count pulse. figure 8-36. start timing of timer n ' ' %' +' /'
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remark n = 5, 6 (2) tmn readout during timer operation since reading out tmn during operation occurs while the selected clock is temporarily stopped, be sure to select a high- or low-level waveform that is longer than the selected clock (n = 5, 6).
user?s manual u15109ej3v0ud 309 chapter 9 watch timer function 9.1 function the watch timer has the following functions. ? watch timer ? interval timer the watch timer and interval timer functions can be used at the same time. figure 9-1. block diagram of watch timer f xx f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 4 intwtn intwtni wtnm0 wtnm1 wtnm2 wtnm3 wtnm4 wtnm5 wtnm6 wtnm7 wtncs0 wtncs1 wtncs2 f w clear clear internal bus watch timer mode control register (wtnm) watch timer high-speed clock select register (wtnhc) watch timer clock select register (wtncs) 5-bit counter selector selector selector selector 11-bit prescaler remark f xx : main clock frequency f xt : subclock frequency f w : watch timer clock frequency
chapter 9 watch timer function user ? s manual u15109ej3v0ud 310 (1) watch timer the watch timer generates an interrupt request (intwtn) at time intervals of 0.5 or 0.25 second by using the main clock or subclock. (2) interval timer the watch timer generates an interrupt request (intwtni) at time intervals specified in advance. table 9-1. interval time of interval timer interval time f w = 32.768 khz 2 4 1/f w 488 s 2 5 1/f w 977 s 2 6 1/f w 1.95 ms 2 7 1/f w 3.91 ms 2 8 1/f w 7.81 ms 2 9 1/f w 15.6 ms 2 10 1/f w 31.2 ms 2 11 1/f w 62.4 ms remark f w : watch timer clock frequency 9.2 configuration the watch timer includes the following hardware. table 9-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 11 bits 1 control registers watch timer mode control register (wtnm) watch timer high-speed clock select register (wtnhc) watch timer clock select register (wtncs)
chapter 9 watch timer function user ? s manual u15109ej3v0ud 311 9.3 watch timer control register the watch timer mode control register (wtnm), watch timer high-speed clock select register (wtnhc), and watch timer clock select register (wtncs) control the watch timer. the watch timer should be operated after setting the count clock and interval time. (1) watch timer mode control register (wtnm) this register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the interrupt time of the watch timer. wtnm is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears wtnm to 00h. after reset: 00h r/w address: fffff360h 765432<1><0> wtnm wtnm7 wtnm6 wtnm5 wtnm4 wtnm3 wtnm2 wtnm1 wtnm0 wtnm6 wtnm5 wtnm4 selects interval time of prescaler 0002 4 /f w (488 s) 0012 5 /f w (977 s) 0102 6 /f w (1.95 ms) 0112 7 /f w (3.91 ms) 1002 8 /f w (7.81 ms) 1012 9 /f w (15.6 ms) 1102 10 /f w (31.2 ms) 1112 11 /f w (62.4 ms) wtnm3 wtnm2 selects interrupt time of watch timer 002 14 /f w (0.5 s) 012 13 /f w (0.25 s) 102 5 /f w (977 s) 112 4 /f w (488 s) wtm1 controls operation of 5-bit counter 0 clears after operation stops 1starts wtnm0 enables operation of watch timer 0 stops operation (clears both prescaler and 5-bit counter) 1 enables operation remarks 1. f w : watch timer clock frequency 2. values in parentheses apply when f w = 32.768 khz. 3. for the settings of wtnm7, refer to 9.3 (3) watch timer clock select register (wtncs) .
chapter 9 watch timer function 312 user ? s manual u15109ej3v0ud (2) watch timer high-speed clock select register (wtnhc) this register selects the count clock of the watch timer. the count clock is determined using wtnm7 bit of wtnm register in combination with wtncs1 and wtncs0 bits of the watch timer clock select register (wtncs). wtnhc is set using an 8-bit memory manipulation instruction. reset input clears wtnhc to 00h. after reset: 00h r/w address: fffff366h 76543210 wtnhc0000000wtncs2 remark for the settings of wtncs2, refer to 9.3 (3) watch timer clock select register (wtncs) . (3) watch timer clock select register (wtncs) this register selects the count clock of the watch timer. wtncs is set using an 8-bit memory manipulation instruction. reset input clears wtncs to 00h. caution do not change the contents of the wtnm, wtnhc, and wtncs registers (interval time, interrupt time for watch timer, count clock) during a watch timer operation. after reset: 00h r/w address: fffff364h 76543210 wtncs 0 0 0 0 0 0 wtncs1 wtncs0 wtncs2 wtncs1 wtncs0 wtnm7 selection of count clock main clock frequency 0000f xx /2 7 4.194 mhz 0001f xt (subclock) ? 0010f xx /3 2 6 6.291 mhz 0011f xx /2 8 8.388 mhz 0100setting prohibited ? 0101setting prohibited ? 0110f xx /3 2 7 12.582 mhz 0111f xx /2 9 16.777 mhz 1010f xx /3 2 2 6 18.874 mhz other than above setting prohibited ? remark wtnm7 is bit 7 of the wtnm register. wtncs2 is bit 0 of the wtnhc register.
chapter 9 watch timer function user ? s manual u15109ej3v0ud 313 9.4 operation 9.4.1 operation as watch timer the watch timer operates with time intervals of 0.5 second with the subclock (32.768 khz). the watch timer generates an interrupt request at fixed time intervals. the count operation of the watch timer is started when bits 0 (wtnm0) and 1 (wtnm1) of the watch timer mode control register (wtnm) are set to 1. when these bits are cleared to 0, the 11-bit prescaler and 5-bit counter are cleared, and the watch timer stops the count operation. setting the wtnm1 bit to 0 can clear the 5-bit counter of the watch timer. an error of up to 15.6 ms may occur at this time. setting the wtnm0 bit to 0 can clear the interval timer. however, an error up to 0.5 s may occur after a watch timer overflow (intwtn) because the 5-bit counter is also cleared.
chapter 9 watch timer function 314 user ? s manual u15109ej3v0ud 9.4.2 operation as interval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value. the interval time can be selected by bits 4 to 6 (wtnm4 to wtnm6) of the watch timer mode control register (wtnm). table 9-3. interval time of interval timer wtnm6 wtnm5 wtnm4 interval time f w = 32.768 khz 000 2 4 1/f w 488 s 001 2 5 1/f w 977 s 010 2 6 1/f w 1.95 ms 011 2 7 1/f w 3.91 ms 100 2 8 1/f w 7.81 ms 101 2 9 1/f w 15.6 ms 110 2 10 1/f w 31.2 ms 111 2 11 1/f w 62.4 ms remark f w : watch timer clock frequency figure 9-2. operation timing of watch timer/interval timer start 5-bit counter overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) count clock f w or f w /2 9 watch timer interrupt intwtn interval timer interrupt intwtni nt nt remark f w : watch timer clock frequency ( ): f w = 32.768 khz n: number of interval timer operations
chapter 9 watch timer function user ? s manual u15109ej3v0ud 315 9.4.3 cautions it takes some time to generate the first watch timer interrupt request (intwtn) after operation is enabled (wtnm1 and wtnm0 bits of wtnm register = 1). figure 9-3. watch timer interrupt request (intwtn) generation (interrupt period = 0.5 s) it takes 0.515625 s to generate the first intwtn (2 9 1/32.768 = 0.015625 s longer). intwtn is then generated every 0.5 s. 0.5 s 0.5 s 0.515625 s wtnm0, wtnm1 intwtn
user?s manual u15109ej3v0ud 316 chapter 10 watchdog timer function 10.1 functions the watchdog timer has the following functions. ? watchdog timer ? interval timer ? selecting the oscillation stabilization time caution use the watchdog timer mode register (wdtm) to select the watchdog timer mode or the interval timer mode. figure 10-1. block diagram of watchdog timer internal bus osts0 osts1 osts2 osts wdtm4 wdtm3 run wdtm wdcs wdcs0 wdcs1 wdcs2 3 internal reset signal intwdt note 1 intwdtm note 2 3 output controller output controller prescaler selector f xx /2 24 f xx /2 12 f xx /2 22 f xx /2 21 f xx /2 20 f xx /2 19 f xx /2 18 f xx /2 17 f xx /2 16 run clear selector osc notes 1. in watchdog timer mode 2. in interval timer mode remark f xx : main clock frequency
chapter 10 watchdog timer function user ? s manual u15109ej3v0ud 317 (1) watchdog timer mode this mode detects an inadvertent program loop. when a loop is detected, a non-maskable interrupt can be generated. table 10-1. loop detection time of watchdog timer loop detection time clock f xx = 20 mhz f xx = 18.87 mhz f xx = 16 mhz 2 16 /f xx 3.3 ms 3.5 ms 4.1 ms 2 17 /f xx 6.6 ms 6.9 ms 8.2 ms 2 18 /f xx 13.1 ms 13.9 ms 16.4 ms 2 19 /f xx 26.2 ms 27.8 ms 32.8 ms 2 20 /f xx 52.4 ms 55.6 ms 65.5 ms 2 21 /f xx 104.9 ms 111.1 ms 131.1 ms 2 22 /f xx 209.7 ms 222.3 ms 262.1 ms 2 24 /f xx 838.9 ms 889.1 ms 1.05 s (2) interval timer mode interrupts are generated at a preset time interval. table 10-2. interval time of interval timer interval time clock f xx = 20 mhz f xx = 18.87 mhz f xx = 16 mhz 2 16 /f xx 3.3 ms 3.5 ms 4.1 ms 2 17 /f xx 6.6 ms 6.9 ms 8.2 ms 2 18 /f xx 13.1 ms 13.9 ms 16.4 ms 2 19 /f xx 26.2 ms 27.8 ms 32.8 ms 2 20 /f xx 52.4 ms 55.6 ms 65.5 ms 2 21 /f xx 104.9 ms 111.1 ms 131.1 ms 2 22 /f xx 209.7 ms 222.3 ms 262.1 ms 2 24 /f xx 838.9 ms 889.1 ms 1.05 s
chapter 10 watchdog timer function 318 user ? s manual u15109ej3v0ud 10.2 configuration the watchdog timer includes the following hardware. table 10-3. watchdog timer configuration item configuration control registers oscillation stabilization time select register (osts) watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) 10.3 watchdog timer control registers the watchdog timer is controlled by the following registers. ? oscillation stabilization time select register (osts) ? watchdog timer clock select register (wdcs) ? watchdog timer mode register (wdtm) (1) oscillation stabilization time select register (osts) this register selects the oscillation stabilization time after a reset is applied or the stop mode is released until the oscillation is stable. osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 01h. after reset: 01h r/w address: fffff380h 76543210 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection f xx osts2 osts1 osts0 clock 20 mhz 18.87 mhz 16 mhz 0002 16 /f xx 3.3 ms 3.5 ms 4.1 ms 0012 18 /f xx (after reset) 13.1 ms 13.9 ms 16.4 ms 0102 19 /f xx 26.2 ms 27.8 ms 32.8 ms 0112 20 /f xx 52.4 ms 55.6 ms 65.5 ms 1002 21 /f xx 104.9 ms 111.1 ms 131.1 ms other than above setting prohibited
chapter 10 watchdog timer function user ? s manual u15109ej3v0ud 319 (2) watchdog timer clock select register (wdcs) this register selects the overflow times of the watchdog timer and the interval timer. wdcs is set by an 8-bit memory manipulation instruction. reset input sets wdcs to 00h. after reset: 00h r/w address: fffff382h 76543210 wdcs00000wdcs2wdcs1wdcs0 watchdog timer/interval timer overflow time f xx wdcs2 wdcs1 wdcs0 clock 20 mhz 18.87 mhz 16 mhz 0002 16 /f xx 3.3 ms 3.5 ms 4.1 ms 0012 17 /f xx 6.6 ms 6.9 ms 8.2 ms 0102 18 /f xx 13.1 ms 13.9 ms 16.4 ms 0112 19 /f xx 26.2 ms 27.8 ms 32.8 ms 1002 20 /f xx 52.4 ms 55.6 ms 65.5 ms 1012 21 /f xx 104.9 ms 111.1 ms 131.1 ms 1102 22 /f xx 209.7 ms 222.3 ms 262.1 ms 1112 24 /f xx 838.9 ms 889.1 ms 1.05 s caution always set bits 7 to 3 to 0.
chapter 10 watchdog timer function 320 user ? s manual u15109ej3v0ud (3) watchdog timer mode register (wdtm) this register sets the operating mode of the watchdog timer, enables and disables counting, and generates internal reset signals. wdtm is set by an 8-bit or 1-bit memory manipulation instruction. reset input sets wdtm to 00h. after reset: 00h r/w address: fffff384h <7>6543210 wdtm run 0 0 wdtm4 wdtm3 0 0 0 run operating mode selection for the watchdog timer note 1 0 disable count 1 clear count and start counting wdtm4 operating mode selection for the watchdog timer note 2 0 interval timer mode (if an overflow occurs, the maskable interrupt intwdtm is generated.) 1 watchdog timer mode 1 (if an overflow occurs, the non-maskable interrupt intwdt is generated.) wdtm3 internal reset signal generation selection note 2 0 internal reset signal not generated when overflow 1 internal reset signal generated when overflow notes 1. once run is set (1), the register cannot be cleared (0) by software. therefore, when the count starts, the count cannot be stopped except by reset input. 2. once wdtm3 and wdtm4 are set (1), the registers cannot be cleared (0) by software. caution if run is set (1) and the watchdog timer is cleared, the actual overflow time may be up to 2 12 /f xx seconds shorter than the set time.
chapter 10 watchdog timer function user ? s manual u15109ej3v0ud 321 10.4 operation 10.4.1 operation as watchdog timer set bit 4 (wdtm4) of the watchdog timer mode register (wdtm) to 1 to operate as a watchdog timer to detect inadvertent program looping. setting bit 7 (run) of wdtm to 1 starts the count. after counting starts, if run is set to 1 again within the set time interval for loop detection, the watchdog timer is cleared and counting starts again. if run is not set to 1 and the loop detection time has elapsed, a non-maskable interrupt (intwdt) is generated (no reset functions). the watchdog timer stops running in the idle and stop modes. consequently, set run to 1 and clear the watchdog timer before entering the idle or stop mode. do not set the watchdog timer when using the halt mode since the watchdog timer continues to operate in the halt mode. cautions 1. the actual loop detection time may be up to 2 12 /f xx seconds shorter than the set time. 2. when the subclock is selected for the cpu clock, the watchdog timer stops counting (pauses). table 10-4. loop detection time of watchdog timer loop detection time clock f xx = 20 mhz f xx = 18.87 mhz f xx = 16 mhz 2 16 /f xx 3.3 ms 3.5 ms 4.1 ms 2 17 /f xx 6.6 ms 6.9 ms 8.2 ms 2 18 /f xx 13.1 ms 13.9 ms 16.4 ms 2 19 /f xx 26.2 ms 27.8 ms 32.8 ms 2 20 /f xx 52.4 ms 55.6 ms 65.5 ms 2 21 /f xx 104.9 ms 111.1 ms 131.1 ms 2 22 /f xx 209.7 ms 222.3 ms 262.1 ms 2 24 /f xx 838.9 ms 889.1 ms 1.05 s
chapter 10 watchdog timer function 322 user ? s manual u15109ej3v0ud 10.4.2 operation as interval timer set bit 4 (wdtm4) of the watchdog timer mode register (wdtm) to 0 to operate the watchdog timer as an interval timer that repeatedly generates interrupts with a preset count value as the interval. when operating as an interval timer, the interrupt mask flag (wdtmk) of the wdtic register and the priority setting flags (wdtpr0 to wdtpr2) become valid, and a maskable interrupt (intwdtm) can be generated. the default priority of intwdtm has the highest priority setting of the maskable interrupts. the interval timer continues operating in the halt mode and stops in the idle and stop modes. therefore, before entering the idle/stop mode set the run bit of the wdtm register to 1 to clear the interval timer, and then set to the idle or stop mode. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (selecting the watchdog timer mode), the interval timer mode is not entered as long as reset is not input. 2. the interval time immediately after being set by wdtm may be up to 2 12 /f xx seconds shorter than the set time. 3. when the subclock is selected for the cpu clock, the watchdog timer stops counting (pauses). table 10-5. interval time of interval timer interval time clock f xx = 20 mhz f xx = 18.87 mhz f xx = 16 mhz 2 16 /f xx 3.3 ms 3.5 ms 4.1 ms 2 17 /f xx 6.6 ms 6.9 ms 8.2 ms 2 18 /f xx 13.1 ms 13.9 ms 16.4 ms 2 19 /f xx 26.2 ms 27.8 ms 32.8 ms 2 20 /f xx 52.4 ms 55.6 ms 65.5 ms 2 21 /f xx 104.9 ms 111.1 ms 131.1 ms 2 22 /f xx 209.7 ms 222.3 ms 262.1 ms 2 24 /f xx 838.9 ms 889.1 ms 1.05 s
chapter 10 watchdog timer function user ? s manual u15109ej3v0ud 323 10.5 standby function control register (1) oscillation stabilization time select register (osts) the wait time from when the stop mode is cancelled until the oscillation stabilizes is controlled by the oscillation stabilization time select register (osts). osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 01h. after reset: 01h r/w address: fffff380h 76543210 osts00000osts2osts1osts0 oscillation stabilization time selection f xx osts2 osts1 osts0 clock 20 mhz 18.87 mhz 16 mhz 0002 16 /f xx 3.3 ms 3.5 ms 4.1 ms 0012 18 /f xx (after reset) 13.1 ms 13.9 ms 16.4 ms 0102 19 /f xx 26.2 ms 27.8 ms 32.8 ms 0112 20 /f xx 52.4 ms 55.6 ms 65.5 ms 1002 21 /f xx 104.9 ms 111.1 ms 131.1 ms other than above setting prohibited caution the wait time at the cancellation of the stop mode does not include the time (?a? in the figure below) until clock oscillation starts after stop mode is cancelled by reset input or interrupt generation. v ss stop mode cancellation a voltage waveform at x1 pin
user?s manual u15109ej3v0ud 324 chapter 11 serial interface function 11.1 overview the v850/sc1, v850/sc2, and v850/sc3 incorporate the following serial interfaces. ? channel 0: 3-wire serial i/o (csi0)/i 2 c0 note ? channel 2: 3-wire serial i/o (csi2)/i 2 c1 note ? channel 3: 3-wire serial i/o (csi3)/asynchronous serial interface (uart1) ? channel 4: 3-wire serial i/o (csi4)/asynchronous serial interface (uart0) ? channel 5: 3-wire serial i/o (csi5) ? channel 6: 3-wire serial i/o (csi6) ? channel 7: asynchronous serial interface (uart2) ? channel 8: asynchronous serial interface (uart3) note i 2 c0 and i 2 c1 support multimasters. either 3-wire serial i/o or i 2 c can be used as a serial interface. 11.2 3-wire serial i/o (csi0, csi2, csi3): 8 bits csin (n = 0, 2, 3) has the following two modes. (1) operation stopped mode this mode is used when serial transfers are not performed. (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sckn), a serial output line (son), and a serial input line (sin). since data can be transmitted and received simultaneously in 3-wire serial i/o mode, the processing time for data transfer is reduced. the first bit in the 8-bit data in serial transfers is fixed as the msb. the sck0 and sck2 pins can be used to select normal output and n-ch open-drain output, respectively, by setting the port 1 function register and port 2 function register (pf1, pf2). 3-wire serial i/o mode is useful for connection to devices such as peripheral i/o that include a clocked serial interface, and display controllers.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 325 11.2.1 configuration csin includes the following hardware. table 11-1. configuration of csin item configuration registers serial i/o shift register n (sion) serial operation mode register n (csimn) control registers serial clock select register n (csisn) remark n = 0, 2, 3 figure 11-1. block diagram of 3-wire serial i/o (csi0, csi2, csi3) tmx output clock selection sckn son sin intcsin internal bus selector 8 serial clock controller serial clock counter serial i/o shift register n (sion) interrupt generator remarks 1. n = 0, 2, 3 2. tmx output is as shown below. when n = 0, 3: tm5 output when n = 2: tm6 output (1) serial i/o shift register n (sion) sion is an 8-bit register that performs parallel-serial conversion and serial transmission/reception (shift operations) in synchronization with the serial clock. sion is set by an 8-bit memory manipulation instruction. when bit 7 (csien) of serial operation mode register n (csimn) is set to 1, a serial operation can be started by writing data to or reading data from sion. when transmitting, data written to sion is output via the serial output (son). when receiving, data is read from the serial input (sin) and written to sion. reset input sets these registers to 00h. caution do not access sion except by the transfer start trigger during a transfer operation (read is disabled when moden = 0 and write is disabled when moden = 1). remark n = 0, 2, 3
chapter 11 serial interface function user ? s manual u15109ej3v0ud 326 11.2.2 csin control registers csin is controlled by the following registers. ? serial operation mode register n (csimn) ? serial clock select register n (csisn) (1) serial clock select register n (csisn) and serial operation mode register n (csimn) csisn is used to set the serial clock of serial interface channel n. csisn can be set by an 8-bit memory manipulation instruction (n = 0, 2, 3). reset input sets csisn to 00h. csimn is used to enable or disable the serial clock, operation modes, and specific operations of serial interface channel n. csimn can be set by an 8-bit or 1-bit memory manipulation instruction (n = 0, 2, 3). reset input sets csimn to 00h.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 327 after reset: 00h r/w address: csis0 fffff2a4h csis2 fffff2c4h csis3 fffff2d4h 76543210 csisn0000000scln2 (n = 0, 2, 3) after reset: 00h r/w address: csim0 fffff2a2h csim2 fffff2c2h csim3 fffff2d2h <7>6543210 csimn csien 0 0 0 0 moden scln1 scln0 (n = 0, 2, 3) sion operation enable/disable specification csien shift register operation serial counter port 0 operation disable clear port function note 1 1 operation enable count operation enable serial function + port function note 2 transfer operation mode flag moden operation mode transfer start trigger son output 0 transmit/receive mode sion write normal output 1 receive-only mode sion read port function scln2 scln1 scln0 clock selection 0 0 0 external clock input (sckn) 0 0 1 at n = 0, 3: tm5 output at n = 2: tm6 output 010f xx /8 011f xx /16 1 0 0 setting prohibited 1 0 1 setting prohibited 110f xx /32 111f xx /64 notes 1. the sin, son, and sckn pins are used as port function pins when csien = 0 (sion operation stopped state). 2. when csien = 1 (sion operation enabled state), the port function is available for the sin pin when only using the transmit function and son pin when only using the receive function. cautions 1. do not perform bit manipulation on scln1 and scln0. 2. always set bits 6 to 3 to csimn to 0. remark if the selected clock is specified as a timer output, the p17/t05/ti5 and p30/t06/ti6 pins do not need to be in timer output mode.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 328 11.2.3 operations csin has the following two operation modes. ? operation stopped mode ? 3-wire serial i/o mode (1) operation stopped mode in this mode, serial transfers are not performed, thus enabling a reduction in power consumption. in operation stopped mode, the sin, son, and sckn pins can be used as normal i/o port pins. (a) register settings operation stopped mode is set via the csien bit of serial operation mode register n (csimn). figure 11-2. csimn setting (operation stopped mode) after reset: 00h r/w address: csim0 fffff2a2h csim2 fffff2c2h csim3 fffff2d2h <7>6543210 csimn csien 0 0 0 0 moden scln1 scln0 (n = 0, 2, 3) sion operation enable/disable specification csien shift register operation serial counter port 0 operation disabled cleared port function
chapter 11 serial interface function user ? s manual u15109ej3v0ud 329 (2) 3-wire serial i/o mode 3-wire serial i/o mode is useful when connecting to devices such as peripheral i/o that include a clocked serial interface, and display controllers. this mode executes data transfers via three lines: a serial clock line (sckn), a serial output line (son), and a serial input line (sin). (a) register settings 3-wire serial i/o mode is set by serial operation mode register n (csimn). figure 11-3. csimn setting (3-wire serial i/o mode) after reset: 00h r/w address: csim0 fffff2a2h csim2 fffff2c2h csim3 fffff2d2h <7>6543210 csimn csien 0 0 0 0 moden scln1 scln0 (n = 0, 2, 3) sion operation enable/disable specification csien shift register operation serial counter port 1 operation enabled count operation enabled serial function + port function transfer operation mode flag moden operation mode transfer start trigger son output 0 transmit/receive mode write to sion normal output 1 receive-only mode read from sion port function scln2 scln1 scln0 clock selection 0 0 0 external clock input (sckn) 0 0 1 when n = 0, 3: tm5 output when n = 2: tm6 output 010f xx /8 011f xx /16 1 0 0 setting prohibited 1 0 1 setting prohibited 110f xx /32 111f xx /64 remarks 1. refer to 11.2.2 (1) serial clock select register n (csisn) and serial operation mode register n (csimn) for the scln2 bit. 2. if the selected clock is specified as a timer output, the p17/t05/ti5 and p30/t06/ti6 pins do not need to be in timer output mode.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 330 (b) communication operations in 3-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is sent or received in synchronization with the serial clock. serial i/o shift register n (sion) is shifted in synchronization with the falling edge of the serial clock. transmit data is held in the son latch and is output from the son pin. data that is received via the sin pin in synchronization with the rising edge of the serial clock is latched to sion. completion of an 8-bit transfer automatically stops operation of sion and sets the interrupt request flag (intcsin). figure 11-4. timing of 3-wire serial i/o mode si0 di7 di6 di5 di4 di3 di2 di1 di0 intcsin serial clock 1 so0 do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronization with the falling edge of the serial clock (c) transfer start a serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial i/o shift register n (sion). ? the sion operation control bit (csien) = 1 ? after an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. the transfer data is set to sion as follows. ? transmit/receive mode when csien = 1 and moden = 0, transfer starts when writing to sion. ? receive-only mode when csien = 1 and moden = 1, transfer starts when reading from sion. caution after data has been written to sion, transfer will not start even if the csien bit value is set to 1. completion of an 8-bit transfer automatically stops the serial transfer operation and sets the interrupt request flag (intcsin).
chapter 11 serial interface function user ? s manual u15109ej3v0ud 331 11.3 3-wire serial i/o (csi4): 8 to 16 bits variable csi4 has the following two operation modes. (1) operation stopped mode this mode is used when serial transfers are not performed. (2) 3-wire serial i/o mode (msb/lsb-first switchable) this mode transfers variable data of 8 to 16 bits via three lines: a serial clock line (sck4), a serial output line (so4), and a serial input line (si4). since data can be transmitted and received simultaneously in 3-wire serial i/o mode, the processing time for data transfer is reduced. the first bit of serial transfer data can be switched between msb and lsb. 3-wire serial i/o mode is useful for connection to devices such as peripheral i/o that include a clocked serial interface, and display controllers. 11.3.1 configuration csi4 includes the following hardware. table 11-2. configuration of csi4 item configuration registers variable-length serial io shift register 4 (sio4) control registers variable-length serial control register 4 (csim4) variable-length serial setting register 4 (csib4) baud rate generator source clock select register 4 (brgcn4) baud rate generator output clock select register 4 (brgck4)
chapter 11 serial interface function user ? s manual u15109ej3v0ud 332 figure 11-5. block diagram of 3-wire serial i/o (csi4) baud rate generator so4 si4 intcsi4 serial clock controller selector interrupt generator serial clock counter (8-/16-bit switchable) variable-length serial i/o shift register 4 (8 to 16 bits) sck4 direction controller internal bus (1) variable-length serial i/o shift register 4 (sio4) sio4 is a 16-bit variable register that performs parallel-serial conversion and transmission/reception (shift operations) in synchronization with the serial clock. sio4 is set by a 16-bit memory manipulation instruction. when bit 7 (csie4) of variable-length serial control register 4 (csim4) is set to 1, a serial operation can be started by writing data to or reading data from sio4. when transmitting, data written to sio4 is output via the serial output (so4). when receiving, data is read from the serial input (si4) and written to sio4. reset input sets sio4 to 0000h. caution do not access sio4 except by the transfer start trigger during a transfer operation (read is disabled when mode4 = 0 and write is disabled when mode4 = 1). after reset: 0000h r/w address: fffff2e0h 1514131211109876543210 sio4
chapter 11 serial interface function user ? s manual u15109ej3v0ud 333 if the transfer bit length is set to other than 16 bits, when setting data to the shift register, be sure to align data from the lowest bit, regardless of whether the first transfer bit is msb or lsb. any data can be set to the unused higher bits, but in this case the data received after a serial transfer operation becomes 0. figure 11-6. when transfer bit length other than 16 bits is set (a) when transfer bit length is 10 bits and msb first si4 so4 15 10 9 0 fixed to 0 (b) when transfer bit length is 12 bits and lsb first si4 so4 fixed to 0 15 12 11 0
chapter 11 serial interface function user ? s manual u15109ej3v0ud 334 11.3.2 csi4 control registers csi4 is controlled by the following registers. ? variable-length serial control register 4 (csim4) ? variable-length serial setting register 4 (csib4) ? baud rate generator source clock select register 4 (brgcn4) ? baud rate generator output clock select register 4 (brgck4) (1) variable-length serial control register 4 (csim4) this register is used to enable or disable the serial clock, operation modes, and specific operations of serial interface channel 4. csim4 can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets csim4 to 00h. after reset: 00h r/w address: fffff2e2h <7>6543210 csim4 csie4 0 0 0 0 mode4 0 scl4 sio4 operation enable/disable specification csie4 shift register operation serial counter port 0 operation disabled clear port function note 1 1 operation enabled count operation enabled serial function + port function note 2 transfer operation mode flag mode4 operation mode transfer start trigger so4 output 0 transmit/receive mode sio4 write normal output 1 receive-only mode sio4 read port function scl4 clock selection 0 external clock input (sck4) 1 brg (baud rate generator) notes 1. the si4, so4, and sck4 pins are used as port function pins when csie4 = 0 (sio4 operation disabled state). 2. when csie4 = 1 (sio4 operation enable state), the port function is available only for the si4 pin when only using the transmit function and to so4 pin when using the receive-only function.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 335 (2) variable-length serial setting register 4 (csib4) this register is used to set the operation format of serial interface channel 4. the bit length of a variable register is set by setting bits 3 to 0 (bsel3 to bsel0) of variable-length serial setting register 4. data is transferred msb first when bit 4 (dir) is 1, and is transferred lsb first when dir is 0. csib4 can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets csib4 to 00h. after reset: 00h r/w address: fffff2e4h 7 <6> <5> <4> 3 2 1 0 csib4 0 cmode dmode dir bsel3 bsel2 bsel1 bsel0 cmode dmode sck4 active level si4 interrupt timing so4 output timing 0 0 low level rising edge of sck4 falling edge of sck4 0 1 low level falling edge of sck4 rising edge of sck4 1 0 high level falling edge of sck4 rising edge of sck4 1 1 high level rising edge of sck4 falling edge of sck4 dir serial transfer direction 0 lsb first 1 msb first bsel3 bsel2 bsel1 bsel0 bit length of serial register 0 0 0 0 16 bits 10008 bits 10019 bits 1 0 1 0 10 bits 1 0 1 1 11 bits 1 1 0 0 12 bits 1 1 0 1 13 bits 1 1 1 0 14 bits 1 1 1 1 15 bits other than above setting prohibited
chapter 11 serial interface function user ? s manual u15109ej3v0ud 336 (3) baud rate generator source clock select register 4 (brgcn4) brgcn4 is set by an 8-bit memory manipulation instruction. reset input sets brgcn4 to 00h. after reset: 00h r/w address: fffff2e6h 76543210 brgcn400000brgn2brgn1brgn0 brgn2 brgn1 brgn0 source clock (f sck )n 000f xx 0 001f xx /2 1 010f xx /4 2 011f xx /8 3 100f xx /16 4 101f xx /32 5 110f xx /64 6 111f xx /128 7
chapter 11 serial interface function user ? s manual u15109ej3v0ud 337 (4) baud rate generator output clock select register 4 (brgck4) brgck4 is set by an 8-bit memory manipulation instruction. reset input sets brgck4 to 7fh. after reset: 7fh r/w address: fffff2e8h 76543210 brgck4 0 brgk6 brgk5 brgk4 brgk3 brgk2 brgk1 brgk0 brgk6 brgk5 brgk4 brgk3 brgk2 brgk1 brgk0 baud rate output clock k 0 0 0 0 0 0 0 setting prohibited 0 0000001f sck /2 1 0000010f sck /4 2 0103011f sck /6 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1111110f sck /252 126 1111111f sck /254 127 the baud rate transmit/receive clock that is generated is obtained by dividing the main clock. ? generation of baud rate transmit/receive clock using main clock the transmit/receive clock is obtained by dividing the main clock. the following equation is used to obtain the baud rate from the main clock. [baud rate] = [hz] f xx : main clock oscillation frequency n: value set by brgn2 to brgn0 (0 n 7) k: value set by brgk6 to brgk0 (1 k 127) caution do not use the baud rate transmit/receive clock of csi4 with a transfer rate higher than the cpu operation clock. if used with a transfer rate higher than the cpu operation clock, transfer cannot be performed correctly. f xx 2 n k 2
chapter 11 serial interface function user ? s manual u15109ej3v0ud 338 11.3.3 operations csi4 has the following two operation modes. ? operation stopped mode ? 3-wire serial i/o mode (1) operation stopped mode in this mode, serial transfers are not performed, thus enabling a reduction in power consumption. in operation stopped mode, the si4, so4, and sck4 pins can be used as normal i/o port pins. (a) register settings operation stopped mode is set via the csie4 bit of variable-length serial control register 4 (csim4). when csie4 = 0 (sio4 operation stop state), the pins connected to si4, so4, or sck4 function as port pins. figure 11-7. csim4 setting (operation stopped mode) after reset: 00h r/w address: fffff2e2h <7>6543210 csim4 csie4 0 0 0 0 mode4 0 scl4 sio4 operation enable/disable specification csie4 shift register operation serial counter port 0 operation disabled cleared port function
chapter 11 serial interface function user ? s manual u15109ej3v0ud 339 (2) 3-wire serial i/o mode 3-wire serial i/o mode is useful when connecting to devices such as peripheral i/o that include a clocked serial interface, and display controllers. this mode executes data transfers via three lines: a serial clock line (sck4), a serial output line (so4), and a serial input line (si4). (a) register settings 3-wire serial i/o mode is set by the variable-length serial control register 4 (csim4). figure 11-8. csim4 setting (3-wire serial i/o mode) after reset: 00h r/w address: fffff2e2h <7>6543210 csim4 csie4 0 0 0 0 mode4 0 scl4 sio4 operation enable/disable specification csie4 shift register operation serial counter port 1 operation enabled count operation enabled serial function + port function transfer operation mode flag mode4 operation mode transfer start trigger so4 output 0 transmit/receive mode write to sio4 normal output 1 receive-only mode read from sio4 port function scl4 clock selection 0 external clock input (sck4) 1 brg (baud rate generator)
chapter 11 serial interface function user ? s manual u15109ej3v0ud 340 the bit length of a variable-length register is set by setting bits 3 to 0 (bsel3 to bsel0) of csib4. data is transferred msb first when bit 4 (dir) is 1, and is transferred lsb first when dir is 0. figure 11-9. csib4 setting (3-wire serial i/o mode) after reset: 00h r/w address: fffff2e4h 7 <6> <5> <4> 3 2 1 0 csib4 0 cmode dmode dir bsel3 bsel2 bsel1 bsel0 cmode dmode sck4 active level si4 interrupt timing so4 output timing 0 0 low level rising edge of sck4 falling edge of sck4 0 1 low level falling edge of sck4 rising edge of sck4 1 0 high level falling edge of sck4 rising edge of sck4 1 1 high level rising edge of sck4 falling edge of sck4 dir serial transfer direction 0 lsb first 1 msb first bsel3 bsel2 bsel1 bsel0 bit length of serial register 0 0 0 0 16 bits 10008 bits 10019 bits 1 0 1 0 10 bits 1 0 1 1 11 bits 1 1 0 0 12 bits 1 1 0 1 13 bits 1 1 1 0 14 bits 1 1 1 1 15 bits other than above setting prohibited
chapter 11 serial interface function user ? s manual u15109ej3v0ud 341 (b) communication operations in 3-wire serial i/o mode, data is transmitted and received in 8 to 16-bit units, specified by setting bits 3 to 0 (bsel3 to bsel0) of variable-length serial setting register 4 (csib4). each bit of data is transmitted or received in synchronization with the serial clock. after transfer of all bits is completed, sio4 stops operation automatically and the interrupt request flag (intcsi4) is set. bits 6 and 5 (cmode and dmode) of variable-length serial setting register 4 (csib4) can be used to change the attribute of the serial clock (sck4) and the phases of serial data (si4 and so4). figure 11-10. timing of 3-wire serial i/o mode sck4 (cmode = 0) sio4 (write) so4 (dmode = 1) intcsi4 sck4 (cmode = 1) so4 (dmode = 0) remark the arrows show the si4 data fetch timing. when cmode = 0, the serial clock (sck4) stops at a high level during the operation stop, and outputs a low level during a data transfer operation. when cmode = 1, on the other hand, sck4 stops at a low level during the operation stop and outputs a high level during a data transfer operation. the phases of the so4 output timing and the s14 fetch timing can be shifted half a clock by setting dmode. however, the interrupt signal (intcsi4) is generated at the final edge of the serial clock (sck4), regardless of the setting of csib4.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 342 (c) transfer start a serial transfer becomes possible when the following two conditions have been satisfied. ? the sio4 operation control bit (csie4) = 1 ? after a serial transfer, the internal serial clock is stopped. serial transfer starts when the following operation is performed after the above two conditions have been satisfied. ? transmit and transmit/receive mode (mode4 = 0) transfer starts when writing to sio4. ? receive-only mode (mode4 = 1) transfer starts when reading from sio4. caution after data has been written to sio4, transfer will not start even if the csie4 bit value is set to 1. completion of the final-bit transfer automatically stops the serial transfer operation and sets the interrupt request flag (intcsi4). figure 11-11. timing of 3-wire serial i/o mode (when csib4 = 08h) sck4 (cmode = 0) si4 intcsi4 12345678 transfer end so4 (dmode = 0) lsb msb lsb msb remark csib4 = 08h (cmode = 0, dmode = 0, dir = 0, bsel3 to bsel0 = 1000)
chapter 11 serial interface function user?s manual u15109ej3v0ud 343 11.4 3-wire serial i/o (csi5, csi6): 8 or 16 bits 11.4.1 features ? high-speed transfer: maximum 4 mbps ? half-duplex communications ? master mode or slave mode can be selected ? transmit data length: 8 bits or 16 bits can be set ? transfer data direction can be switched between msb first and lsb first ? eight clock signals can be selected (7 master clocks and 1 slave clock) ? 3-wire type son: serial transmit data output sin: serial receive data input sckn: serial clock i/o ? interrupt sources: 1 type ? transmission/reception completion interrupt (intcsin) ? transmit/receive mode and receive-only mode can be specified ? two transmit buffers (sotbfn/sotbfln, sotbn/sotbln) and two receive buffers (sirbn/sirbln, sirben/sirbeln) are provided on chip ? single transfer mode and repeat transfer mode can be specified caution when using p120/sck5, p121/si5, and p122/so5 for csi5 transmission/reception and p123/sck6, p124/si6, and p125/so6 for csi6 transmission/reception, set the csi5 pin function (sck5, si5, so5) and csi6 pin function (sck6, si6, so6) using port alternate-function control register 2 (pac2) (refer to 5.2.11 (2) (b) port alternate-function register 2 (pac2) and 5.3 setting when port pin is used for alternate function). remark n = 5, 6
chapter 11 serial interface function user?s manual u15109ej3v0ud 344 11.4.2 configuration csin includes the following hardware (n = 5, 6). table 11-3. csin configuration item configuration registers serial i/o shift register n, ln (sion, sioln) control registers clocked serial interface mode register n (csimn) clocked serial interface clock select register n (csickn) clocked serial interface receive buffer register n, ln (sirbn, sirbln) clocked serial interface read-only receive buffer register n, ln (sirben, sirbeln) clocked serial interface transmit buffer register n , ln (sotbn, sotbln) clocked serial interface initial transmit buffer register (sotbfn, sotbfln) remark n = 5, 6 figure 11-12. block diagram of 3-wire serial i/o (csi5, csi6) selector transmission control so selection so latch transmit buffer register (sotbn/sotbln) receive buffer register (sirbn/sirbln) shift register (sion/sioln) initial transmit buffer register (sotbfn/sotbfln) interrupt controller clock start/stop control & clock phase control serial clock controller sckn intcsin son sin control signal transmit data control f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 sckn remark n = 5, 6 f xx : main clock frequency
chapter 11 serial interface function user ? s manual u15109ej3v0ud 345 transmission/reception of data is performed by the sion register (n = 0, 1). (1) serial i/o shift register n (sion) the sion register is a 16-bit shift register that converts parallel data into serial data, and is used for both transmission and reception. data is shifted in (reception) and shifted out (transmission) from the msb or lsb side. the actual transmit/receive operations are started up by accessing the buffer register. remark n = 5, 6 (2) serial i/o shift register ln (sioln) the sioln register is an 8-bit shift register that converts parallel data into serial data, and is used for both transmission and reception. data is shifted in (reception) and shifted out (transmission) from the msb or lsb side. the actual transmit/receive operations are started up by accessing the buffer register. remark n = 5, 6 (3) selector the selector selects the serial clock to be used. (4) serial clock controller the serial clock controller controls the serial clock supply to the shift register, as well as the clock output to the sckn pin when the internal clock is used. (5) serial clock counter the serial clock counter counts the serial clock output or input during transmission/reception, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (6) interrupt controller the interrupt controller controls the interrupt request timing.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 346 11.4.3 control registers csin is controlled by the following registers (n = 5, 6). ? clocked serial interface mode register n (csimn) ? clocked serial interface clock select register n (csickn) ? clocked serial interface receive buffer register n, ln (sirbn, sirbln) ? clocked serial interface read-only receive buffer register n, ln (sirben, sirbeln) ? clocked serial interface transmit buffer register n, ln (sotbn, sotbln) ? clocked serial interface initial transmit buffer register n, ln (sotbfn, sotbfln) (1) clocked serial interface mode registers 5, 6 (csim5, csim6) these registers control csin operations (n = 5, 6). csimn can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets these registers to 00h. caution the trmdn, ccln, dirn, csitn, and auton bits of the csimn register can be overwritten only when the csotn bit = 0. if these bits are overwritten at any other time, the operation cannot be guaranteed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 347 after reset: 00h r/w address: fffff240h, fffff260h 76543210 csimn csien trmdn ccln dirn csitn auton 0 csotn note (n = 5, 6) csien csin operation enable/disable specification 0 csin operation enabled 1 csin operation disabled the internal csin circuit can be reset asynchronously by setting the csien bit to 0. for the sckn and son pin output status when the csien bit = 0, refer to 11.6.5 output pins . trmdn transmission/reception mode specification 0 receive-only mode 1 transmit/receive mode when the trmdn bit = 0, receive-only transfer is performed and the son pin output is fixed to low level. data reception is started by reading the sirbn register. when the trmdn bit = 1, transmission/reception is started by writing data to the sotbn register. ccln data length specification 08 bits 1 16 bits dirn transfer direction mode (msb/lsb) specification 0 first bit of transfer data is msb 1 first bit of transfer data is lsb csitn delay of interrupt request signal control 0 no delay 1 delay mode (interrupt request signal is delayed 1/2 cycle). auton single transfer mode or repeat transfer mode specification 0 single transfer mode 1 repeat transfer mode csotn flag indicating transfer status 0 idle status 1 transfer execution status note bit 0 (csotn) can only be read. cautions 1. the delay mode (csitn bit = 1) is valid only in the master mode (cksn2 to cskn0 bits of the csickn register are not 111b). in the slave mode (cksn2 to cksn0 bits are 111b), do not set the delay mode. 2. the csotn bit is cleared (0) by writing 0 to the csien bit.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 348 (2) clocked serial interface clock select registers 5, 6 (csick5, csick6) the csickn register is an 8-bit register that controls the csin transfer operation (n = 5, 6). csickn can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets these registers to 00h. caution the csickn register can be overwritten only when the csie bit of the csimn register = 0. after reset: 00h r/w address: fffff242h, fffff262h 76543210 csickn 0 0 0 ckpn dapn cksn2 cksn1 cksn0 (n = 5, 6) ckpn dapn operation mode 00 do7 do6 do5 do4 do3 do2 do1 do0 di7 son (output) sckn (i/o) sin (input) di6 di5 di4 di3 di2 di1 di0 01 do7 do6 do5 do4 do3 do2 do1 do0 di7 son (output) sckn (i/o) sin (input) di6 di5 di4 di3 di2 di1 di0 10 do7 do6 do5 do4 do3 do2 do1 do0 di7 son (output) sckn (i/o) sin (input) di6 di5 di4 di3 di2 di1 di0 11 do7 do6 do5 do4 do3 do2 do1 do0 di7 son (output) sckn (i/o) sin (input) di6 di5 di4 di3 di2 di1 di0 cksn2 cksn1 cksn0 input clock selection mode 000f xx /4 master mode 001f xx /8 master mode 010f xx /16 master mode 011f xx /32 master mode 100f xx /64 master mode 101f xx /128 master mode 110f xx /256 master mode 1 1 1 external clock (sckn) slave mode remark f xx : main clock frequency
chapter 11 serial interface function user ? s manual u15109ej3v0ud 349 (3) clocked serial interface receive buffer registers 5, 6 (sirb5, sirb6) the sirbn register is a 16-bit buffer register that stores receive data. when the receive-only mode is set (trmdn bit of csimn register = 0), reception is started by reading data from the sirbn register (n = 5, 6). sirbn is set by a 16-bit memory manipulation instruction. reset input sets these registers to 0000h. in addition to reset input, these registers can also be initialized by clearing (0) the csien bit of the csimn register. after reset: 0000h r address: fffff244h, fffff264h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sirbn sirb n15 sirb n14 sirb n13 sirb n12 sirb n11 sirb n10 sirb n9 sirb n8 sirb n7 sirb n6 sirb n5 sirb n4 sirb n3 sirb n2 sirb n1 sirb n0 (n = 5, 6) cautions 1. read the sirbn register only when a data length of 16 bits has been set (ccln bit of csimn register = 1). 2. when the single transfer mode has been set (auton bit of csimn register = 0), perform a read operation only in the idle state (csotn bit of csimn register = 0). if the sirbn register is read during data transfer, the data cannot be guaranteed. (4) clocked serial interface receive buffer registers l5, l6 (sirbl5, sirbl6) the sirbln register is an 8-bit buffer register that stores receive data. when the receive-only mode is set (trmdn bit of csimn register = 0), reception is started by reading data from the sirbln register. sirbln is set by an 8-bit memory manipulation instruction (n = 5, 6). reset input sets these registers to 00h. in addition to reset input, these registers can also be initialized by clearing (0) the csien bit of the csimn register. the sirbln register is the same as the lower bytes of the sirbn register. after reset: 00h r address: fffff246h, fffff266h 76543210 sirbln sirbn7 sirbn6 sirbn5 sirbn4 sirbn3 sirbn2 sirbn1 sirbn0 (n = 5, 6) cautions 1. read the sirbln register only when a data length of 8 bits has been set (ccln bit of csimn register = 0). 2. when the single transfer mode is set (auton bit of csimn register = 0), perform a read operation only in the idle state (csotn bit of csimn register = 0). if the sirbln register is read during data transfer, the data cannot be guaranteed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 350 (5) clocked serial interface read-only receive buffer registers 5, 6 (sirbe5, sirbe6) the sirben register is a 16-bit buffer register that stores receive data. sirben is set by a 16-bit memory manipulation instruction (n = 5, 6). reset input sets these registers to 0000h. in addition to reset input, these registers can also be initialized by clearing (0) the csien bit of the csimn register. the sirben register is the same as the sirbn register. it is used to read the contents of the sirbn register. after reset: 0000h r address: fffff24ch, fffff26ch 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sirben sirbe n15 sirbe n14 sirbe n13 sirbe n12 sirbe n11 sirbe n10 sirbe n9 sirbe n8 sirbe n7 sirbe n6 sirbe n5 sirbe n4 sirbe n3 sirbe n2 sirbe n1 sirbe n0 (n = 5, 6) cautions 1. a receive operation is not started even if data is read from the sirben register. 2. the sirben register can be read only if a data length of 16 bits is set (ccln bit of csimn register = 1). (6) clocked serial interface read-only receive buffer registers l5, l6 (sirbel5, sirbel6) the sirbeln register is an 8-bit buffer register that stores receive data. sirbeln is set by an 8-bit or 1-bit memory manipulation instruction (n = 5, 6). reset input sets these registers to 00h. in addition to reset input, these registers can also be initialized by clearing (0) the csien bit of the csimn register. the sirbeln register is the same as the sirbln register. it is used to read the contents of the sirbln register. after reset: 00h r address: fffff24eh, fffff26eh 76543210 sirbeln sirben7 sirben6 sirben5 sirben4 sirben3 sirben2 sirben1 sirben0 (n = 5, 6) cautions 1. a receive operation is not started even if data is read from the sirbeln register. 2. the sirbeln register can be read only if a data length of 8 bits has been set (ccln bit of csimn register = 0).
chapter 11 serial interface function user ? s manual u15109ej3v0ud 351 (7) clocked serial interface transmit buffer registers 5, 6 (sotb5, sotb6) the sotbn register is a 16-bit buffer register that stores transmit data. when the transmit/receive mode is set (trmdn bit of csimn register = 1), transmission is started by writing data to the sotbn register (n = 5, 6). sotbn is set by a 16-bit memory manipulation instruction. reset input sets these registers to 0000h. after reset: 0000h r/w address: fffff248h, fffff268h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sotbn sotb n15 sotb n14 sotb n13 sotb n12 sotb n11 sotb n10 sotb n9 sotb n8 sotb n7 sotb n6 sotb n5 sotb n4 sotb n3 sotb n2 sotb n1 sotb n0 (n = 5, 6) cautions 1. access the sotbn register only when a data length of 16 bits is set (ccln bit of csimn register = 1). 2. when the single transfer mode is set (auton bit of csimn register = 0), perform access only in the idle state (csotn bit of csimn register = 0). if the sotbn register is accessed during data transfer, the data cannot be guaranteed. (8) clocked serial interface transmit buffer registers l5, l6 (sotbl5, sotbl6) the sotbln register is an 8-bit buffer register that stores transmit data. when the transmit/receive mode is set (trmdn bit of csimn register = 1), transmission is started by writing data to the sotbln register (n = 5, 6). sotbln is set by an 8-bit or 1-bit memory manipulation instruction. reset input sets these registers to 00h. the sotbln register is the same as the lower bytes of the sotbn register. after reset: 00h r/w address: fffff24ah, fffff26ah 76543210 sotbln sotbn7 sotbn6 sotbn5 sotbn4 sotbn3 sotbn2 sotbn1 sotbn0 (n = 5, 6) cautions 1. access the sotbln register only when a data length of 8 bits has been set (ccln bit of csimn register = 0). 2. when the single transfer mode is set (auton bit of csimn register = 0), perform access only in the idle state (csotn bit of csimn register = 0). if the sotbln register is accessed during data transfer, the data cannot be guaranteed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 352 (9) clocked serial interface initial transmit buffer registers 5, 6 (sotbf5, sotbf6) the sotbfn register is a 16-bit buffer register that stores the initial transmit data in the repeat transfer mode. transmission is not started even if data is written to the sotbfn register (n = 5, 6). sotbfn can be set by a 16-bit memory manipulation instruction. reset input sets these registers to 0000h. after reset: 0000h r/w address: fffff250h, fffff270h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sotbfn sotbf n15 sotbf n14 sotbf n13 sotbf n12 sotbf n11 sotbf n10 sotbf n9 sotbf n8 sotbf n7 sotbf n6 sotbf n5 sotbf n4 sotbf n3 sotbf n2 sotbf n1 sotbf n0 (n = 5, 6) caution access the sotbfn register only when a data length of 16 bits has been set (ccln bit of csimn register = 1), and only in the idle state (csotn bit of csimn register = 0). if the sotbfn register is accessed during data transfer, the data cannot be guaranteed. (10) clocked serial interface initial transmit buffer registers l5, l6 (sotbfl5, sotbfl6) the sotbfln register is an 8-bit buffer register that stores the initial transmit data in the repeat transfer mode. transmission is not started even if data is written to the sotbfln register (n = 5, 6). sotbfln is set by an 8-bit or 1-bit memory manipulation instruction. reset input sets these registers to 00h. the sotbfln register is the same as the lower bytes of the sotbfn register. after reset: 00h r/w address: fffff252h, fffff272h 76543210 sotbfln sotbfn7 sotbfn6 sotbfn5 sotbfn4 sotbfn3 sotbfn2 sotbfn1 sotbfn0 (n = 5, 6) caution access the sotbfln register only when a data length of 8 bits has been set (ccln bit of csimn register = 0), and only in the idle state (csotn bit of csimn register = 0). if the sotbfln register is accessed during data transfer, the data cannot be guaranteed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 353 (11) serial i/o shift registers 5, 6 (sio5, sio6) the sion register is a 16-bit shift register that converts parallel data into serial data. data is shifted in (received) or shifted out (transmitted) starting from msb or lsb. transfer is not started even if the sion register is read (n = 5, 6). sion is set by a 16-bit memory manipulation instruction. reset input sets these registers to 0000h. in addition to reset input, these registers can also be initialized by clearing (0) the csien bit of the csimn register. after reset: 0000h r address: fffff254h, fffff274h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sion sio n15 sio n14 sio n13 sio n12 sio n11 sio n10 sio n9 sio n8 sio n7 sio n6 sio n5 sio n4 sio n3 sio n2 sio n1 sio n0 (n = 5, 6) caution access the sion register only when a data length of 16 bits has been set (ccln bit of csimn register = 1), and only in the idle state (csotn bit of csimn register = 0). if the sion register is accessed during data transfer, the data cannot be guaranteed. (12) serial i/o shift registers l5, l6 (siol5, siol6) the sioln register is an 8-bit shift register that converts parallel data into serial data. data is shifted in (received) or shifted out (transmitted) starting from msb or lsb. transfer is not started even if the sioln register is read (n = 5, 6). sioln is set by an 8-bit or 1-bit memory manipulation instruction. reset input sets these registers to 00h. in addition to reset input, these registers can also be initialized by clearing (0) the csien bit of the csimn register. the sioln register is the same as the lower bytes of the sion register. after reset: 00h r address: fffff256h, fffff276h 76543210 sioln sion7 sion6 sion5 sion4 sion3 sion2 sion1 sion0 (n = 5, 6) caution access the sioln register only when a data length of 8 bits has been set (ccln bit of csimn register = 0), and only in the idle state (csotn bit of csimn register = 0). if the sioln register is accessed during data transfer, the data cannot be guaranteed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 354 11.4.4 operation csin is has the following two operation modes (n = 5, 6). ? single transfer mode ? repeat transfer mode (1) single transfer mode (a) usage in the receive-only mode (trmdn bit of csimn register = 0), transfer is started by reading note 1 the receive data buffer register (sirbn/sirbln) (n = 5, 6). in the transmit/receive mode (trmdn bit of csimn register = 1), transfer is started by writing note 2 to the transmit data buffer register (sotbn/sotbln). in the slave mode, operation must be enabled beforehand (csien bit of csimn register = 1). when transfer is started, the value of the csotn bit of the csimn register becomes 1 (transmission execution status). upon transfer completion, the transmission/reception completion interrupt (intcsin) is set (1), and the csotn bit is cleared (0). the next data transfer request is then waited for. notes 1. when a data length of 16 bits (ccln bit of csimn register = 1) has been set, read the sirbn register. when a data length of 8 bits (ccln bit of csimn register = 0) has been set, read the sirbln register. 2. when a data length of 16 bits (ccln bit of csimn register = 1) has been set, write to the sotbn register. when a data length of 8 bits (ccln bit of csimn register = 0) has been set, write to the sotbln register. caution when the csotn bit of the csimn register = 1, do not manipulate the csin register.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 355 figure 11-13. timing chart in single transfer mode (1/2) (a) in transmit/receive mode, data length: 8 bits, transfer direction: msb first, no interrupt delay, single transfer mode, operation mode: ckpn bit = 0, dapn bit = 0 01010101 10101010 (55h) (aah) aah aah abh 56h adh 5ah b5h 6ah d5h sckn (i/o) son (output) sin (input) reg_r/w sotbln register sioln register sirbln register csotn bit intcsin interrupt 55h (transmit data) write 55h to sotbln register remarks 1. n = 5, 6 2. reg_r/w: internal signal. this signal indicates that receive data buffer register (sirbn/sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 356 figure 11-13. timing chart in single transfer mode (2/2) (b) in transmit/receive mode, data length: 8 bits, transfer direction: msb first, no interrupt delay, single transfer mode, operation mode: ckpn bit = 0, dapn bit = 1 01010101 10101010 aah aah abh 56h adh 5ah b5h 6ah d5h sckn (i/o) son (output) sin (input) reg_r/w sotbln register sioln register sirbln register csotn bit intcsin interrupt (55h) (aah) 55h (transmit data) write 55h to sotbln register remarks 1. n = 5, 6 2. reg_r/w: internal signal. this signal indicates that receive data buffer register (sirbn/sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 357 (b) clock phase selection the following shows the timing when changing the conditions for clock phase selection (ckpn bit of csicn register) and data phase selection (dapn bit of csicn register) under the following conditions. ? data length = 8 bits (ccln bit of csimn register = 0) ? first bit of transfer data = msb (dirn bit of csimn register = 0) ? no interrupt request signal delay control (csitn bit of csimn register = 0) figure 11-14. timing chart according to clock phase selection (1/2) (a) when ckpn bit = 0, dapn bit = 0 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 (b) when ckpn bit = 1, dapn bit = 0 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 remarks 1. n = 5, 6 2. reg_r/w: internal signal. this signal indicates that receive data buffer register (sirbn/sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 358 figure 11-14. timing chart according to clock phase selection (2/2) (c) when ckpn bit = 0, dapn bit = 1 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 (d) when ckpn bit = 1, dapn bit = 1 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 remarks 1. n = 5, 6 2. reg_r/w: internal signal. this signal indicates that receive data buffer register (sirbn/sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 359 (c) transmission/reception completion interrupt request signals (intcsi5, intcsi6) intcsin is set (1) upon completion of data transmission/reception. caution the delay mode (csitn bit = 1) is valid only in the master mode (bits cksn2 to cksn0 of the csickn register are not 111b). the delay mode cannot be set when the slave mode is set (bits cksn2 to cksn0 = 111b). figure 11-15. timing chart of interrupt request signal output in delay mode (1/2) (a) when ckpn bit = 0, dapn bit = 0 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit delay remarks 1. n = 5, 6 2. reg_r/w: internal signal. this signal indicates that receive data buffer register (sirbn/sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 360 figure 11-15. timing chart of interrupt request signal output in delay mode (2/2) (b) when ckpn bit = 1, dapn bit = 1 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit delay remarks 1. n = 5, 6 2. reg_r/w: internal signal. this signal indicates that receive data buffer register (sirbn/sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 361 (2) repeat transfer mode (a) usage (receive-only) <1> set the repeat transfer mode (auton bit of csimn register = 1) and the receive-only mode (trmdn bit of csimn register = 0). <2> read sirbn register (start transfer with dummy read). <3> wait for transmission/reception completion interrupt request (intcsin). <4> when the transmission/reception completion interrupt request (intcsin) has been set (1), read the sirbn register note (reserve next transfer). <5> repeat steps <3> and <4> (n ? 2) times. (n: number of transfer data) <6> following output of the last transmission/reception completion interrupt request (intcsin), read the sirben register and the sion register note . note when transferring n number of data, receive data is loaded by reading the sirbn register from the first data to the (n ? 2)th data. the (n ? 1)th data is loaded by reading the sirben register, and the nth (last) data is loaded by reading the sion register.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 362 figure 11-16. repeat transfer (receive-only) timing chart din-1 sckn (i/o) sin (input) son (output) l sioln register sirbln register reg_rd csotn bit intcsin interrupt rq_clr trans_rq din-2 din-1 sirbn (dummy) sirbn (d1) sirbn (d2) sirbn (d3) sirben (d4) sion (d5) < 4 >< 6 > < 4 >< 3 > < 3 > < 4 > < 5 > period during which next transfer can be reserved < 3 > < 2 > < 1 > din-2 din-3 din-4 din-5 din-5 din-3 din-4 remarks 1. n = 5, 6 2. reg_rd: internal signal. this signal indicates that the receive data buffer register (sirbn/sirbln) has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. in the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer. following the transmission/reception completion interrupt request (intcsin), transfer is continued if the sirbn register can be read within the next transfer reservation period. if the sirbn register cannot be read, transfer ends and the sirbn register does not receive the new value of the sion register. the last data can be obtained by reading the sion register following completion of the transfer.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 363 (b) usage (transmission/reception) <1> set the repeat transfer mode (auton bit of csimn register = 1) and the transmission/reception mode (trmdn bit of csimn register = 1) <2> write the first data to the sotbfn register. <3> write the 2nd data to the sotbn register (start transfer). <4> wait for a transmission/reception completion interrupt request (intcsin). <5> when the transmission/reception completion interrupt request (intcsin) has been set (1), write the next data to the sotbn register (reserve next transfer), and read the sirbn register to load the receive data. <6> repeat steps <4> and <5> as long as data to be sent remains. <7> wait for the intcsin interrupt. when the interrupt request signal is set (1), read the sirbn register to load the (n ? 1)th receive data (n: number of transfer data). <8> following the last transmission/reception completion interrupt request (intcsin), read the sion register to load the nth (last) receive data.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 364 figure 11-17. repeat transfer (transmission/reception) timing chart dout-1 dout-1 sckn (i/o) son (output) sin (input) sotbfln register sotbln register sioln register sirbln register reg_wr reg_rd csotn bit intcsin interrupt rq_clr trans_rq dout-2 dout-3 dout-4 dout-5 dout-2 dout-3 dout-4 dout-5 din-1 din-1 sotbfn (d1) sotbn (d2) sotbn (d3) sotbn (d4) sotbn (d5) sirbn (d1) sirbn (d2) < 5 >< 7 >< 8 > < 4 > < 5 > < 4 > < 6 > period during which next transfer can be reserved < 5 > < 4 > < 3 > < 2 > < 1 > sirbn (d3) sirbn (d4) sion (d5) din-2 din-3 din-4 din-5 din-2 din-3 din-4 din-5 remarks 1. n = 5, 6 2. reg_wr: internal signal. this signal indicates that the transmit data buffer register (sotbn/sotbln) has been written. reg_rd: internal signal. this signal indicates that the receive data buffer register (sirbn/sirbln) has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. in the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer. following the transmission/reception completion interrupt request (intcsin), transfer is continued if the sotbn register can be written within the next transfer reservation period. if the sotbn register cannot be written, transfer ends and the sirbn register does not receive the new value of the sion register. the last receive data can be obtained by reading the sion register following completion of the transfer.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 365 (c) next transfer reservation period in the repeat transfer mode, the next transfer must be prepared within the period shown below. figure 11-18. timing chart of next transfer reservation period (1/2) (a) when data length is 8 bits, operation mode: ckpn bit = 0, dapn bit = 0 sckn (i/o) intcsin interrupt reservation period: 7 sckn cycles (b) when data length is 16 bits, operation mode: ckpn bit = 0, dapn bit = 0 sckn (i/o) intcsin interrupt reservation period: 15 sckn cycles remark n = 5, 6
chapter 11 serial interface function user ? s manual u15109ej3v0ud 366 figure 11-18. timing chart of next transfer reservation period (2/2) (c) when data length is 8 bits, operation mode: ckpn bit = 0, dapn bit = 1 sckn (i/o) intcsin interrupt reservation period: 6.5 sckn cycles (d) when data length is 16 bits, operation mode: ckpn bit = 0, dapn bit = 1 sckn (i/o) intcsin interrupt reservation period: 14.5 sckn cycles remark n = 5, 6
chapter 11 serial interface function user ? s manual u15109ej3v0ud 367 (d) cautions to continue repeat transfers, it is necessary to either read the sirbn register or write to the sotbn register during the transfer reservation period. if the sirbn register or the sotbn register is accessed when the transfer reservation period is over, the following occurs. (i) in case of contention between transfer request clear and register access since request cancellation has higher priority, the next transfer request is ignored. therefore, transfer is interrupted, and normal data transfer cannot be performed. figure 11-19. transfer request clear and register access contention sckn (i/o) intcsin interrupt rq_clr reg_r/w transfer reservation period remarks 1. n = 5, 6 2. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indicates that the receive data buffer register (sirbn/sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 368 (ii) in case of contention between interrupt request and register access since continuous transfer has stopped once, the transfer is executed as a new repeat transfer. in the slave mode, a bit phase error transfer error results (refer to figure 11-20 ). in the transmit/receive mode, the value of the sotbfn register is retransmitted, and illegal data is sent. figure 11-20. interrupt request and register access contention sckn (i/o) intcsin interrupt rq_clr reg_r/w transfer reservation period 01 234 remarks 1. n = 5, 6 2. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indicates that receive data buffer register (sirbn/sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 369 11.4.5 output pins (1) sckn pin when csin operation is disabled (csien bit of csimn register = 0), the sckn pin output status is as follows (n = 5, 6). table 11-4. sckn pin output status ckpn cksn2 cksn1 cksn0 sckn pin output 0 don ? t care don ? t care don ? t care fixed to high level 1 1 1 fixed to high level 1 other than above fixed to low level remarks 1. n = 5, 6 2. when any of bits ckpn and cksn2 to cksn0 of the csickn register is overwritten, the sckn pin output changes. (2) son pin when csin operation is disabled (csien bit of csimn register = 0), the son pin output status is as follows (n = 5, 6). table 11-5. son pin output status trmdn dapn auton ccln dirn son pin output 0 don ? t care don ? t care don ? t care don ? t care fixed at low level 0 don ? t care don ? t care don ? t care so latch value (low level) 0sotb7 value 0 1sotb0 value 0sotb15 value 0 1 1sotb0 value 0sotbf7 value 0 1sotbf0 value 0 sotbf15 value 1 1 1 1 1sotbf0 value remarks 1. n = 5, 6 2. when any of bits trmdn, ccln, dirn, and auton of the csimn register or dapn bit of the csickn register is overwritten, the son pin output changes. 3. sotbm: bit m of sotbn register (m = 0, 7, 15) 4. sotbfm: bit m of sotbfn register (m = 0, 7, 15)
chapter 11 serial interface function 370 user?s manual u15109ej3v0ud 11.5 i 2 c bus to use the i 2 c bus function, set the p10/sda0, p12/scl0, p20/sda1, and p22/scl1 pins to n-ch open-drain output. i 2 c0 and i 2 c1 have the following two modes. ? operation stopped mode ? i 2 c (inter ic) bus mode (multimasters supported) (1) operation stopped mode in this mode, serial transfers are not performed, thus enabling a reduction in power consumption. (2) i 2 c bus mode (multimasters support) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock line (scln) and a serial data bus line (sdan). this mode complies with the i 2 c bus format and the master device can output ?start condition?, ?data?, and ?stop condition? data to the slave device via the serial data bus. the slave device automatically detects these received data by hardware. this function can simplify the part of an application program that controls the i 2 c bus. since scln and sdan are open-drain outputs, i 2 cn requires pull-up resistors for the serial clock line and the serial data bus line. remark n = 0, 1
chapter 11 serial interface function user?s manual u15109ej3v0ud 371 figure 11-21. block diagram of i 2 cn iicen dq cln1, cln0 sdan scln intiicn lreln wreln spien wtimn acken sttn sptn mstsn aldn excn coin trcn ackdn stdn spdn fxx stcfn iicbsyn stcenn iicrsvn cldn dadn smcn dfcn cln1 cln0 clxn iiccen1 prescaler iiccen0 tmx output internal bus internal bus iic control register n (iiccn) iic status register n (iicsn) set clear slave address register n (svan) noise eliminator match signal iic shift register n (iicn) so latch start condition generator data hold time correction circuit acknowledge output circuit wakeup controller n-ch open-drain output acknowledge detector start condition detector stop condition detector serial clock counter interrupt request signal generator noise eliminator serial clock controller serial clock wait controller bus status detector iic clock select register n (iiccln) iic function expansion register n (iicxn) iic clock expansion register n (iiccen) iic flag register n (iicfn) n-ch open-drain output remarks 1. n = 0, 1 2. tmx output n = 0: tm5 output n = 1: tm6 output
chapter 11 serial interface function 372 user ? s manual u15109ej3v0ud a serial bus configuration example is shown below. figure 11-22. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2
chapter 11 serial interface function user ? s manual u15109ej3v0ud 373 11.5.1 configuration i 2 cn includes the following hardware (n = 0, 1). table 11-6. configuration of i 2 cn item configuration registers iic shift registers 0 and 1 (iic0, iic1) slave address registers 0 and 1 (sva0, sva1) control registers iic control registers 0 and 1 (iicc0, iicc1) iic status registers 0 and 1 (iics0, iics1) iic flag registers 0 and 1 (iicf0, iicf1) iic clock expansion registers 0 and 1 (iicce0, iicce1) iic function expansion registers 0 and 1 (iicx0, iicx1) iic clock select registers 0 and 1 (iiccl0, iiccl1) (1) iic shift registers 0 and 1 (iic0, iic1) these registers are used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data, and can be used for both transmission and reception (n = 0, 1). write and read operations to iicn are used to control the actual transmit and receive operations. iicn is set by an 8-bit memory manipulation instruction. reset input sets the iic0 and iic1 to 00h. (2) slave address registers 0 and 1 (sva0, sva1) this register sets local addresses when in slave mode. svan is set by an 8-bit memory manipulation instruction (n = 0, 1). reset input sets the sva0 and sva1 to 00h. (3) so latch the so latch is used to retain the output level of the sdan pin (n = 0, 1). (4) wake-up controller this circuit generates an interrupt request when the address received by this register matches the address value set to slave address register n (svan) or when an extension code is received (n = 0, 1). (5) clock selector this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent or received.
chapter 11 serial interface function 374 user ? s manual u15109ej3v0ud (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiicn). an i 2 c interrupt is generated following either of two triggers. ? eighth or ninth clock of the serial clock (set by wtimn bit) ? interrupt request generated when a stop condition is detected (set by spien bit) remarks 1. n = 0, 1 2. wtimn bit: bit 3 of the iic control register n (iiccn) spien bit: bit 4 of the iic control register n (iiccn) (8) serial clock controller in master mode, this circuit generates the clock output via the scln pin from a sampling clock (n = 0, 1). (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector, start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corresponding to the falling edge of the serial clock. (12) start condition generator a start condition is issued when the sttn bit is set. however, in the communication reservation disabled status (iicrsvn bit = 1), this request is ignored and the stcfn bit is set if the bus is not released (iicbsyn bit = 1). remark iicrsvn bit: bit 0 of iic flag register n (iicfn) iicbsyn bit: bit 6 of iic flag register n (iicfn) stcfn bit: bit 7 of iic flag register n (iicfn) (13) bus status detector whether the bus is released or not is ascertained by detecting a start condition and stop condition. however, the bus status cannot be detected immediately after operation, so set the initial status by using the stcenn bit. remark stcenn bit: bit 1 of iic flag register n (iicfn)
chapter 11 serial interface function user ? s manual u15109ej3v0ud 375 11.5.2 i 2 c control registers i 2 c0 and i 2 c1 are controlled by the following registers. ? iic control registers 0, 1 (iicc0, iicc1) ? iic status registers 0, 1 (iics0, iics1) ? iic flag registers 0, 1 (iicf0, iicf1) ? iic clock expansion registers 0, 1 (iicce0, iicce1) ? iic function expansion registers 0, 1 (iicx0, iicx1) ? iic clock select registers 0, 1 (iiccl0, iiccl1) the following registers are also used. ? iic shift registers 0, 1 (iic0, iic1) ? slave address registers 0, 1 (sva0, sva1) (1) iic control registers 0, 1 (iicc0, iicc1) these registers are used to enable/disable i 2 c operations, set the wait timing, and set other i 2 c operations. iiccn can be set by an 8-bit or 1-bit memory manipulation instruction (n = 0, 1). reset input sets iiccn to 00h. caution in i 2 c0, i 2 c1 bus mode, set the port 1 mode register (pm1), port 2 mode register (pm2), port 1 function register (pf1), and port 2 function register (pf2) as follows. in addition, set each output latch to 0. pin port mode register port function register p10/si0/sda0 pm10 of pm1 register = 0 pf10 of pf1 register = 1 p12/sck0/scl0 pm12 of pm1 register = 0 pf12 of pf1 register = 1 p20/si2/sda1 pm20 of pm2 register = 0 pf20 of pf2 register = 1 p22/sck2/scl1 pm22 of pm2 register = 0 pf22 of pf2 register = 1
chapter 11 serial interface function 376 user ? s manual u15109ej3v0ud (1/4) after reset: 00h r/w address: fffff340h, fffff350h <7> <6> <5> <4> <3> <2> <1> <0> iiccn iicen lreln wreln spien wtimn acken sttn sptn (n = 0, 1) iicen i 2 cn operation enable/disable specification 0 operation stopped. iic status register n (iicsn) preset. internal operation stopped. 1 operation enabled. condition for clearing (iicen = 0) condition for setting (iicen = 1) ? cleared by instruction ? when reset is input ? set by instruction lreln exit from communications 0 normal operation 1 this exits from the current communication operation and sets standby mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scln and sdan lines are set for high impedance. the following flags are cleared. ? stdn ? ackdn ? trcn ? coin ? excn ? mstsn ? sttn ? sptn the standby mode following exit from communications remains in effect until the following communication entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code reception occurs after the start condition. condition for clearing (lreln = 0) note condition for setting (lreln = 1) ? automatically cleared after execution ? when reset is input ? set by instruction note this flag ? s signal is invalid when iicen = 0. remark stdn: bit 1 of iic state register n (iicsn) ackdn: bit 2 of iic state register n (iicsn) trcn: bit 3 of iic state register n (iicsn) coin: bit 4 of iic state register n (iicsn) excn: bit 5 of iic state register n (iicsn) mstsn: bit 7 of iic state register n (iicsn)
chapter 11 serial interface function user ? s manual u15109ej3v0ud 377 (2/4) wreln wait cancellation control 0 wait not cancelled 1 wait cancelled. this setting is automatically cleared after wait is canceled. condition for clearing (wreln = 0) note condition for setting (wreln = 1) ? automatically cleared after execution ? when reset is input ? set by instruction spien enable/disable generation of interrupt request when stop condition is detected 0 disabled 1 enabled condition for clearing (spien = 0) note condition for setting (spien = 1) ? cleared by instruction ? when reset is input ? set by instruction wtimn control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock ? s falling edge. master mode: after output of eight clo cks, clock output is set to low level and wait is set. slave mode: after input of eight clo cks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock ? s falling edge. master mode: after output of nine clo cks, clock output is set to low level and wait is set. slave mode: after input of nine clo cks, the clock is set to low level and wait is set for master device. this bit ? s setting is invalid during an address transfer and is valid as the transfer is completed. in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtimn = 0) note condition for setting (wtimn = 1) ? cleared by instruction ? when reset is input ? set by instruction note this flag ? s signal is invalid when iicen = 0. remark n = 0, 1
chapter 11 serial interface function 378 user ? s manual u15109ej3v0ud (3/4) acken acknowledge control 0 acknowledgement disabled. 1 acknowledgement enabled. during the ninth clock period, the sda line is set to low level. however, the ack is invalid during address transfers and is valid when excn = 1. condition for clearing (acken = 0) note condition for setting (acken = 1) ? cleared by instruction ? when reset is input ? set by instruction sttn start condition trigger 0 start condition is not generated. 1 when bus is released (in stop mode): generates a start condition (for starting as master). the sdan line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, scln is changed to low level. when bus is not used: if the communication reservation function is enabled (iicrsvn = 0) ? this trigger functions as a start condition reserve flag. when set, it releases the bus and then automatically generates a start condition. if the communication reservation function is disabled (iicrsvn = 1) ? the stcfn bit is set. this trigger does not generate a start condition. in the wait state (when master device) generates a restart condition after releasing the wait. cautions concerning set timing ? for master reception: cannot be set during transfer. can be set only when acken has been set to 0 and slave has been notified of final reception. ? for master transmission: a start condition cannot be generated normally during the ackn period. set during the wait period. ? for slave: even when the communication reservation function is disabled (iicrsvn = 1), the communication reservation status is entered. ? cannot be set at the same time as sptn condition for clearing (sttn = 0) condition for setting (sttn = 1) ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when lreln = 1 ? when iicen = 0 ? when reset is input ? set by instruction note this flag ? s signal is invalid when iicen = 0. remarks 1. bit 1 (sttn) is 0 if it is read immediately after data setting. 2. iicrsvn: bit 0 of iic flag register n (iicfn) stcfn: bit 7 of iic flag register n (iicfn) 3. n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 379 (4/4) sptn stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (termination of master device ? s transfer). after the sdan line goes to low level, either set the scln line to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sdan line is changed from low level to high level and a stop condition is generated. cautions concerning set timing ? for master reception: cannot be set during transfer. can be set only when acken has been set to 0 and during the wait period after slave has been notified of final reception. ? for master transmission: a stop condition cannot be generated normally during the ackn period. set during the wait period. ? cannot be set at the same time as sttn. ? sptn can be set only when in master mode. note ? when wtimn has been set to 0, if sptn is set during the wait period that follows output of eight clo cks, note that a stop condition will be generated during the high-level period of the ninth clock. when a ninth clock must be output, wtimn should be changed from 0 to 1 during the wait period following output of eight clocks, and sptn should be set during the wait period that follows output of the ninth clock. condition for clearing (sptn = 0) condition for setting (sptn = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when lreln = 1 ? when iicen = 0 ? when reset is input ? set by instruction note set sptn only in master mode. however, when the iicrsvn bit of iic flag register n (iicfn) is 0, sptn must be set and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. for details, see 11.5.13 cautions . caution when bit 3 (trcn) of iic status register n (iicsn) is set to 1, wreln is set during the ninth clock and wait is canceled, after which trcn is cleared and the sdan line is set to high impedance. remarks 1. bit 0 (sptn) is 0 if it is read immediately after data setting. 2. n = 0, 1
chapter 11 serial interface function 380 user ? s manual u15109ej3v0ud (2) iic status registers 0, 1 (iics0, iics1) these registers indicate the status of the i 2 cn bus. iicsn can be set by an 8-bit or 1-bit memory manipulation instruction. iicsn is a read-only register (n = 0, 1). reset input sets iicsn to 00h. (1/3) after reset: 00h r address: fffff342h, fffff352h <7> <6> <5> <4> <3> <2> <1> <0> iicsn mstsn aldn excn coin trcn ackdn stdn spdn (n = 0, 1) mstsn master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (mstsn = 0) condition for setting (mstsn = 1) ? when a stop condition is detected ? when aldn = 1 ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? when a start condition is generated aldn detection of arbitration loss 0 this status means either that there was no arbitration or that the arbitration result was a ? win ? . 1 this status indicates the arbitration result was a ? loss ? . mstsn is cleared. condition for clearing (aldn = 0) condition for setting (aldn = 1) ? automatically cleared after iicsn is read note ? when iicen changes from 1 to 0 ? when reset is input ? when the arbitration result is a ? loss ? . note this register is also cleared when a bit manipulation instruction is executed for bits other than iicsn. remark lreln: bit 6 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn)
chapter 11 serial interface function user ? s manual u15109ej3v0ud 381 (2/3) excn detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (excn = 0) condition for setting (excn = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? when the high-order four bits of the received address data is either ? 0000 ? or ? 1111 ? (set at the rising edge of the eighth clock). coin detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coin = 0) condition for setting (coin = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? when the received address matches the local address (svan) (set at the rising edge of the eighth clock). trcn detection of transmit/receive status 0 receive status (other than transmit status). the sdan line is set for high impedance. 1 transmit status. the value in the so latch is enabled for output to the sdan line (valid starting at the falling edge of the first byte ? s ninth clock). condition for clearing (trcn = 0) condition for setting (trcn = 1) ? when a stop condition is detected ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? cleared by wreln = 1 note ? when aldn changes from 0 to 1 ? when reset is input master ? when ? 1 ? is output to the first byte ? s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated slave ? when ? 1 ? is input by the first byte ? s lsb (transfer direction specification bit) note trcn is cleared and sdan line becomes high impedance when bit 5 (wreln) of iic control register n (iiccn) is set and the wait state is cancelled at the ninth clock by bit 3 (trcn) of iic status register n (iicsn) = 1. remarks 1. wreln: bit 5 of iic control register n (iiccn) lreln: bit 6 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn) 2. n = 0, 1
chapter 11 serial interface function 382 user ? s manual u15109ej3v0ud (3/3) ackdn detection of ack 0 ack was not detected. 1 ack was detected. condition for clearing (ackdn = 0) condition for setting (ackd = 1) ? when a stop condition is detected ? at the rising edge of the next byte ? s first clock ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? after the sdan line is set to low level at the rising edge of the scln ? s ninth clock stdn detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (stdn = 0) condition for setting (stdn = 1) ? when a stop condition is detected ? at the rising edge of the next byte ? s first clock following address transfer ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input when a start condition is detected spdn detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device ? s communication is terminated and the bus is released. condition for clearing (spdn = 0) condition for setting (spdn = 1) ? at the rising edge of the address transfer byte ? s first clock following setting of this bit and detection of a start condition ? when iicen changes from 1 to 0 ? when reset is input when a stop condition is detected remarks 1. lreln: bit 6 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn) 2. n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 383 (3) iic flag registers 0, 1 (iicf0, iicf1) these registers set the i 2 cn operation mode and indicate the i 2 c bus status (n = 0, 1). iicfn can be set by an 8-bit or 1-bit memory manipulation instruction. iicrsvn enables/disables the communication reservation function (see 11.5.12 communication reservation ). the initial value of the iicbsyn bit is set by using the stcenn bit (see 11.5.13 cautions ). the iicrsvn and stcenn bits can be written only when operation of i 2 cn is disabled (iicen of iic control register n (iiccn) = 0). after operation is enabled (iicen = 1), iicfn can be read. (1/2) after reset: 00h r/w note address: fffff368h, fffff36ah <7> <6> 5 4 3 2 <1> <0> iicfn stcfn iicbsyn 0000stcenniicrsvn (n = 0, 1) stcfn sttn clear flag 0 start condition issued 1 sttn flag cleared condition for clearing (stcfn = 0) condition for setting (stcfn = 1) ? cleared by sttn = 1 ? when reset is input ? clearance of sttn when communication reservation disabled (iicrsvn = 1) iicbsyn i 2 cn bus status flag 0 bus released status 1 bus communication status condition for clearing (iicbsyn = 0) condition for setting (iicbsyn = 1) ? when stop condition is detected ? when reset is input ? when start condition is detected ? by setting iicen when stcenn = 0 note bits 6 and 7 are read-only bits. remark sttn: bit 1 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn)
chapter 11 serial interface function 384 user ? s manual u15109ej3v0ud (2/2) stcenn initial start enable trigger 0 start conditions cannot be generated until a stop condition is detected following operation enable (iicen = 1). 1 start conditions can be generated even if a stop condition is not detected following operation enable (iicen = 1). condition for clearing (stcenn = 0) condition for setting (stcenn = 1) ? when start condition is detected ? when reset is input ? setting by instruction iicrsvn communication reservation function disable bit 0 communication reservation enabled 1 communication reservation disabled condition for clearing (iicrsvn = 0) condition for setting (iicrsvn = 1) ? clearing by instruction ? when reset is input ? setting by instruction cautions 1. write stcenn and iicrsvn only when operation is stopped (iicen = 0). 2. when stcenn = 1, the bus released status (iicbsyn = 0) is recognized regardless of the actual bus status immediately after the i 2 cn bus operation is enabled. therefore, to issue the first start condition (sttn = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. remarks 1. sttn: bit 1 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn) 2. n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 385 (4) iic clock expansion registers 0, 1 (iicce0, iicce1), iic function expansion registers 0, 1 (iicx0, iicx1), iic clock select registers 0, 1 (iiccl0, iiccl1) these registers are used to set the transfer clock for the i 2 cn bus. iiccen can be set by an 8-bit memory manipulation instruction, and iicxn and iiccln can be set by an 8-bit or 1-bit memory manipulation instruction (n = 0, 1). reset input sets these registers to 00h. (1/2) after reset: 00h r/w address: fffff34ch, fffff35ch 76543210 iiccen000000iiccen1iiccen0 (n = 0, 1) after reset: 00h r/w address: fffff34ah, fffff35ah 7654321<0> iicxn0000000clxn (n = 0, 1) after reset: 00h r/w note address: fffff344h, fffff354h 76<5><4>321 0 iiccln 0 0 cldn dadn smcn dfcn cln1 cln0 (n = 0, 1) cldn detection of scln line level (valid only when iicen = 1) 0 scln line was detected at low level. 1 scln line was detected at high level. condition for clearing (cldn = 0) condition for setting (cldn = 1) ? when the scln line is at low level ? when iicen = 0 ? when reset is input ? when the scln line is at high level dadn detection of sdan line level (valid only when iicen = 1) 0 sdan line was detected at low level. 1 sdan line was detected at high level. condition for clearing (dadn = 0) condition for setting (dadn = 1) ? when the sdan line is at low level ? when iicen = 0 ? when reset is input ? when the sdan line is at high level note bits 4 and 5 of iiccln are read-only bits. caution always set bits 7 and 6 of iiccln to 0. remark iicen: bit 7 of iic control register n (iiccn)
chapter 11 serial interface function 386 user ? s manual u15109ej3v0ud (2/2) smcn operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfcn digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of dfcn switching (on/off). iiccen1 iiccen0 clxn smcn cln1 cln0 selection clock (f xx /m) settable main clock frequency (f xx ) range operation mode xx110xf xx /12 4.0 mhz to 4.19 mhz xx010xf xx /24 4.0 mhz to 8.38 mhz xx0110f xx /48 8.0 mhz to 16.67 mhz 010111f xx /36 12.0 mhz to 13.4 mhz 100111f xx /54 16.0 mhz to 20.0 mhz n = 0 tm5 output/18 tm5 setting 000111 n = 1 tm6 output/18 tm6 setting high-speed mode xx0000f xx /44 4.0 mhz to 4.19 mhz xx0001f xx /86 4.19 mhz to 8.38 mhz xx0010f xx /172 8.38 mhz to 16.67 mhz 010011f xx /132 12.0 mhz to 13.4 mhz 100011f xx /198 16.0 mhz to 20.0 mhz n = 0 tm5 output/66 tm5 setting 000011 n = 1 tm6 output/66 tm6 setting other than above setting prohibited normal mode remarks 1. n = 0, 1 2. x: don ? t care 3. if the selected clock is specified as a timer output, the p17/t05/ti5 and p30/t06/ti6 pins do not need to be in timer output mode.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 387 (a) i 2 cn transfer clock setting method the i 2 cn transfer clock frequency (f scl ) is calculated using the following expression (n = 0, 1). f scl = 1/(m t + t r + t f ) m = 12, 24, 48, 36, 54, 44, 86, 172, 132, 198 (see the descriptions for bits iiccen1, iiccen0, clxn, smcn, cln1, and cln0 in 11.5.2 (4) .) t: 1/f xx t r : scln rise time t f : scln fall time for example, the i 2 cn transfer clock frequency (f scl ) when f xx = 20 mhz, m = 198, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(198 50 ns + 200 ns + 50 ns) ? 98.5 khz m t + t r + t f m/2 t t f t r m/2 t scln scln inversion scln inversion scln inversion (5) iic shift registers 0, 1 (iic0, iic1) iicn is used for serial transmission/reception (shift operations) synchronized with the serial clock. it can be read from or written to in 8-bit units, but data should not be written to iicn during a data transfer (n = 0, 1). after reset: 00h r/w address: fffff348h, fffff358h 76543210 iicn (n = 0, 1) (6) slave address registers 0, 1 (sva0, sva1) svan holds the i 2 c bus ? s slave addresses. it can be read from or written to in 8-bit units, but bit 0 should be fixed to 0. after reset: 00h r/w address: fffff346h, fffff356h 76543210 svan 0 (n = 0, 1)
chapter 11 serial interface function 388 user ? s manual u15109ej3v0ud 11.5.3 i 2 c bus mode functions (1) pin configuration the serial clock pin (scln) and serial data bus pin (sdan) are configured as follows (n = 0, 1). scln ................this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. sdan ................this pin is used for serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drain outputs, an external pull- up resistor is required. figure 11-23. pin configuration diagram portv dd scln sdan scln sdan portv dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
chapter 11 serial interface function user ? s manual u15109ej3v0ud 389 11.5.4 i 2 c bus definitions and control methods the following section describes the i 2 c bus ? s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ? start condition ? , ? data ? , and ? stop condition ? output via the i 2 c bus ? s serial data bus is shown below. figure 11-24. i 2 c bus serial data transfer timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 scl sda start condition address r/w ack data data stop condition ack ack the master device outputs the start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scln) is continuously output by the master device. however, in the slave device, the scln ? s low-level period can be extended and a wait can be inserted (n = 0, 1). (1) start condition a start condition is met when the scln pin is high level and the sdan pin changes from high level to low level. the start conditions for the scln pin and sdan pin are signals that the master device outputs to the slave device when starting a serial transfer. the slave device includes hardware for detecting start conditions (n = 0, 1). figure 11-25. start conditions h scln sdan a start condition is output when bit 1 (sttn) of iic control register n (iiccn) is set to 1 after a stop condition has been detected (spdn: bit 0 = 1 in iic status register n (iicsn)). when a start condition is detected, iicsn ? s bit 1 (stdn) is set to 1 (n = 0, 1).
chapter 11 serial interface function 390 user ? s manual u15109ej3v0ud (2) addresses the 7 bits of data that follow the start condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in slave address register n (svan). if the address data matches the svan values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition (n = 0, 1). figure 11-26. address address scln 1 sdan intiicn note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note intiicn is generated if a local address or extension code is received during slave device operation. remark n = 0, 1 the slave address and the eighth bit, which specifies the transfer direction as described in (3) transfer direction specification below, are written together to the iic shift register (iicn) and then output. received addresses are written to iicn (n = 0, 1). the slave address is assigned to the higher 7 bits of iicn.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 391 (3) transfer direction specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. when this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. figure 11-27. transfer direction specification scln 1 sdan intiicn 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note intiicn is generated if a local address or extension code is received during slave device operation. remark n = 0, 1
chapter 11 serial interface function 392 user ? s manual u15109ej3v0ud (4) acknowledge signal (ack) the acknowledge signal (ack) is used by the transmitting and receiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. the transmitting device normally receives an ack signal after transmitting 8 bits of data. however, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. failure to return an ack signal may be caused by the following two factors. (a) reception was not performed normally. (b) the final data was received. when the receiving device sets the sdan line to low level during the ninth clock, the ack signal becomes active (normal receive response). when bit 2 (acken) of iic control register n (iiccn) is set to 1, automatic ack signal generation is enabled (n = 0, 1). transmission of the eighth bit following the 7 address data bits causes bit 3 (trcn) of iic status register n (iicsn) to be set. when this trcn bit ? s value is 0, it indicates receive mode. therefore, acken should be set to 1 (n = 0, 1). when the slave device is receiving (when trcn = 0), if the slave device does not need to receive any more data after receiving several bytes, setting acken to 0 will prevent the master device from starting transmission of the subsequent data. similarly, when the master device is receiving (when trcn = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, setting acken to 0 will prevent the ack signal from being returned. this prevents the msb data from being output via the sdan line (i.e., stops transmission) during transmission from the slave device. figure 11-28. ack signal scln 1 sdan 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack remark n = 0, 1 when the local address is received, an ack signal is automatically output in synchronization with the falling edge of the scln ? s eighth clock regardless of the acken value. no ack signal is output if the received address is not a local address (n = 0, 1). the ack signal output method during data reception is based on the wait timing setting, as described below. when 8-clock wait is selected: ack signal is output at the falling edge of the scln ? s eighth clock if acken is set to 1 before wait cancellation. when 9-clock wait is selected: ack signal is automatically output at the falling edge of the scln ? s eighth clock if acken has already been set to 1.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 393 (5) stop condition when the scln pin is high level, changing the sdan pin from low level to high level generates a stop condition (n = 0, 1). a stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. the slave device includes hardware that detects stop conditions. figure 11-29. stop condition h scln sdan remark n = 0, 1 a stop condition is generated when bit 0 (sptn) of iic control register n (iiccn) is set to 1. when the stop condition is detected, bit 0 (spdn) of iic status register n (iicsn) is set to 1 and intiicn is generated when bit 4 (spien) of iiccn is set to 1 (n = 0, 1).
chapter 11 serial interface function 394 user ? s manual u15109ej3v0ud (6) wait signal (wait) the wait signal (wait) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scln pin to low level notifies the communication partner of the wait status. when the wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1). figure 11-30. wait signal (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and acken = 1) scln 6 sdan 78 9 123 scln iicn 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iicn scln acken master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iicn data write (cancel wait) slave wait after output of eighth clock. ffh is written to iicn or wreln is set to 1. transfer lines remark n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 395 figure 11-30. wait signal (2/2) (2) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acken = 1) scln 6 sdan 789 123 scln iicn 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iicn scln acken master master and slave both wait after output of ninth clock. iicn data write (cancel wait) slave ffh is written to iicn or wreln is set to 1. output according to previously set acken value transfer lines remarks 1. acken: bit 2 of iic control register n (iiccn) wreln: bit 5 of iic control register n (iiccn) 2. n = 0, 1 a wait may be automatically generated depending on the setting of bit 3 (wtimn) of iic control register n (iiccn) (n = 0, 1). normally, when bit 5 (wreln) of iiccn is set to 1 or when ffh is written to iic shift register n (iicn) on the receiving side, the wait status is canceled and the transmitting side writes data to iicn to cancel the wait status. the master device can also cancel the wait status via either of the following methods. ? by setting bit 1 (sttn) of iiccn to 1 ? by setting bit 0 (sptn) of iiccn to 1
chapter 11 serial interface function 396 user ? s manual u15109ej3v0ud 11.5.5 i 2 c interrupt requests (intiicn) the following shows the value of iic status register n (iicsn) at the intiicn interrupt request generation timing and at the intiicn interrupt timing (n = 0, 1). (1) master device operation (a) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when wtimn = 0 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 10xxx110b 2: iicsn = 10xxx000b 3: iicsn = 10xxx000b (wtimn = 1) 4: iicsn = 10xxxx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 10xxx110b 2: iicsn = 10xxx100b 3: iicsn = 10xxxx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 397 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) <1> when wtimn = 0 sttn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iicsn = 10xxx110b 2: iicsn = 10xxx000b (wtimn = 1) 3: iicsn = 10xxxx00b (wtimn = 0) 4: iicsn = 10xxx110b (wtimn = 0) 5: iicsn = 10xxx000b (wtimn = 1) 6: iicsn = 10xxxx00b ? 7: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 sttn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 10xxx110b 2: iicsn = 10xxxx00b 3: iicsn = 10xxx110b 4: iicsn = 10xxxx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function 398 user ? s manual u15109ej3v0ud (c) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtimn = 0 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 1010x110b 2: iicsn = 1010x000b 3: iicsn = 1010x000b (wtimn = 1) 4: iicsn = 1010xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 1010x110b 2: iicsn = 1010x100b 3: iicsn = 1010xx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 399 (2) slave device operation (when receiving slave address data (matches with svan)) (a) start ~ address ~ data ~ data ~ stop <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 0001x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001x100b 3: iicsn = 0001xx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function 400 user ? s manual u15109ej3v0ud (b) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 0001x110b 4: iicsn = 0001x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0001x110b 2: iicsn = 0001xx00b 3: iicsn = 0001x110b 4: iicsn = 0001xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 401 (c) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtimn = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 0010x010b 4: iicsn = 0010x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iicsn = 0001x110b 2: iicsn = 0001xx00b 3: iicsn = 0010x010b 4: iicsn = 0010x110b 5: iicsn = 0010xx00b ? 6: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function 402 user ? s manual u15109ej3v0ud (d) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 00000x10b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001xx00b 3: iicsn = 00000x10b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 403 (3) slave device operation (when receiving extension code) (a) start ~ code ~ data ~ data ~ stop <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 0010x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010x100b 4: iicsn = 0010xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function 404 user ? s manual u15109ej3v0ud (b) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 0001x110b 4: iicsn = 0001x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010xx00b 4: iicsn = 0001x110b 5: iicsn = 0001xx00b ? 6: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 405 (c) start ~ code ~ data ~ start ~ code ~ data ~ stop <1> when wtimn = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 0010x010b 4: iicsn = 0010x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010xx00b 4: iicsn = 0010x010b 5: iicsn = 0010x110b 6: iicsn = 0010xx00b ? 7: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function 406 user ? s manual u15109ej3v0ud (d) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 00000x10b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010xx00b 4: iicsn = 00000x10b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 407 (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? 1 ? 1: iicsn = 00000001b remark ? : generated only when spien = 1 n = 0, 1 (5) arbitration loss operation (operation as slave after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0101x110b (example: when aldn is read during interrupt servicing) 2: iicsn = 0001x000b 3: iicsn = 0001x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0101x110b (example: when aldn is read during interrupt servicing) 2: iicsn = 0001x100b 3: iicsn = 0001xx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function 408 user ? s manual u15109ej3v0ud (b) when arbitration loss occurs during transmission of extension code <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) 2: iicsn = 0010x000b 3: iicsn = 0010x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) 2: iicsn = 0010x110b 3: iicsn = 0010x100b 4: iicsn = 0010xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 409 (6) operation when arbitration loss occurs (no communication after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iicsn = 01000110b (example: when aldn is read during interrupt servicing) ? 2: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 n = 0, 1 (b) when arbitration loss occurs during transmission of extension code st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) iiccn ? s lreln is set to 1 by software ? 2: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function 410 user ? s manual u15109ej3v0ud (c) when arbitration loss occurs during data transfer <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 10001110b 2: iicsn = 01000000b (example: when aldn is read during interrupt servicing) ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 n = 0, 1 <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 10001110b 2: iicsn = 01000100b (example: when aldn is read during interrupt servicing) ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 411 (d) when arbitration loss occurs due to restart condition during data transfer <1> not extension code (example: mismatches with svan) st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 1000x110b 2: iicsn = 01000110b (example: when aldn is read during interrupt servicing) ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care dn = d6 to d0 n = 0, 1 <2> extension code st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 1000x110b 2: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) iiccn ? s lreln is set to 1 by software ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care dn = d6 to d0 n = 0, 1
chapter 11 serial interface function 412 user ? s manual u15109ej3v0ud (e) when arbitration loss occurs due to stop condition during data transfer st ad6 to ad0 rw ak d7 to dn sp 1 ? 2 1: iicsn = 1000x110b ? 2: iicsn = 01000001b remark : always generated ? : generated only when spien = 1 x: don ? t care dn = d6 to d0 n = 0, 1 (f) when arbitration loss occurs due to low-level data when attempting to generate a restart condition when wtimn = 1 sttn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 1000x110b 2: iicsn = 1000xx00b 3: iicsn = 01000100b (example: when aldn is read during interrupt servicing) ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 413 (g) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition when wtimn = 1 sttn = 1 st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 1000x110b 2: iicsn = 1000xx00b ? 3: iicsn = 01000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1 (h) when arbitration loss occurs due to low-level data when attempting to generate a stop condition when wtimn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 1000x110b 2: iicsn = 1000xx00b 3: iicsn = 01000000b (example: when aldn is read during interrupt servicing) ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0, 1
chapter 11 serial interface function 414 user ? s manual u15109ej3v0ud 11.5.6 interrupt request (intiicn) generation timing and wait control the setting of bit 3 (wtimn) in iic control register n (iiccn) determines the timing by which intiicn is generated and the corresponding wait control, as shown below (n = 0, 1). table 11-7. intiicn generation timing and wait control during slave device operation during master device operation wtimn address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 988 1 9 notes 1, 2 9 note 2 9 note 2 999 notes 1. the slave device ? s intiicn signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register n (svan). at this point, ack is output regardless of the value set to bit 2 (acken) of iiccn. for a slave device that has received an extension code, intiicn occurs at the falling edge of the eighth clock. 2. if the received address does not match the contents of the slave address register n (svan), neither intiicn nor a wait occurs. remarks 1. the numbers in the table indicate the number of the serial clock ? s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0, 1 (1) during address transmission/reception ? slave device operation: interrupt and wait timing are determined regardless of the wtimn bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtimn bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtimn bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtimn bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? by setting bit 5 (wreln) of iic control register n (iiccn) to 1 ? by writing to the iic shift register n (iicn) ? by start condition setting (bit 1 (sttn) of iic control register n (iiccn) = 1) ? by step condition setting (bit 0 (sptn) of iic control register n (iiccn) = 1) when an 8-clock wait has been selected (wtimn = 0), the output level of ack must be determined prior to wait cancellation. (5) stop condition detection intiicn is generated when a stop condition is detected. remark n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 415 11.5.7 address match detection method in i 2 c bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. address match detection is performed automatically by hardware. an interrupt request (intiicn) occurs when a local address has been set to slave address register n (svan) and when the address set to svan matches the slave address sent by the master device, or when an extension code has been received (n = 0, 1). 11.5.8 error detection in i 2 c bus mode, the status of the serial data bus (sdan) during data transmission is captured by iic shift register n (iicn) of the transmitting device, so the iicn data prior to transmission can be compared with the transmitted iicn data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match (n = 0, 1). 11.5.9 extension code (1) when the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (excn) is set for extension code reception and an interrupt request (intiicn) is issued at the falling edge of the eighth clock (n = 0, 1). the local address stored in slave address register n (svan) is not affected. (2) if 11110xx0 is set to svan by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that intiicn occurs at the falling edge of the eighth clock (n = 0, 1). ? higher four bits of data match: excn = 1 note ? seven bits of data match: coin = 1 note note excn: bit 5 of iic status register n (iicsn) coin: bit 4 of iic status register n (iicsn) (3) since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. for example, when operation as a slave is not desired after the extension code is received, set bit 6 (lreln) of iic control register n (iiccn) to 1 and the cpu will enter the next communication wait state. table 11-8. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification
chapter 11 serial interface function 416 user ? s manual u15109ej3v0ud 11.5.10 arbitration when several master devices simultaneously output a start condition (when sttn is set to 1 before stdn is set to 1 note ), communication among the master devices is performed while the number of clocks are being adjusted until the data differs. this kind of operation is called arbitration (n = 0, 1). when one of the master devices loses in arbitration, an arbitration loss flag (aldn) in iic status register n (iicsn) is set via the timing by which the arbitration loss occurred, and the scln and sdan lines are both set to high impedance, which releases the bus (n = 0, 1). the arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the aldn = 1 setting that has been made by software (n = 0, 1). for details of interrupt request timing, see 11.5.5 i 2 c interrupt requests (intiicn) . note stdn: bit 1 of iic status register n (iicsn) sttn: bit 1 of iic control register n (iiccn) figure 11-31. arbitration timing example master 1 master 2 transfer lines scln sdan scln sdan scln sdan master 1 loses arbitration hi-z hi-z remark n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 417 table 11-9. status during arbitration and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data reception when restart condition is detected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected during data transfer when stop condition is output (when spien = 1) note 2 when data is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to output a restart condition when stop condition is output (when spien = 1) note 2 when data is at low level while attempting to output a stop condition when scln is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when wtimn (bit 3 of iic control register n (iiccn)) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtimn = 0 and the extension code ? s slave address is received, an interrupt request occurs at the falling edge of the eighth clock (n = 0, 1). 2. when there is a possibility that arbitration will occur, set spien = 1 for master device operation (n = 0, 1). remark spien: bit 5 of the iic control register n (iiccn) 11.5.11 wakeup function the i 2 c bus slave function is a function that generates an interrupt request (intiicn) when a local address and extension code have been received. this function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wake-up standby mode is set. this wake-up standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detected, bit 5 (spien) of iic control register n (iiccn) is set regardless of the wake up function, and this determines whether interrupt requests are enabled or disabled (n = 0, 1).
chapter 11 serial interface function 418 user ? s manual u15109ej3v0ud 11.5.12 communication reservation (1) when communication reservation function is enabled (iicrsvn of iicfn = 0) to start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lreln) of iic control register n (iiccn) was set to ? 1 ? ) (n = 0, 1). if bit 1 (sttn) of iiccn is set while the bus is not used, a start condition is automatically generated and wait status is set after the bus is released (after a stop condition is detected). when the bus release is detected (when a stop condition is detected), writing to iic shift register n (iicn) causes the master ? s address transfer to start. at this point, iiccn ? s bit 4 (spien) should be set (n = 0, 1). when sttn has been set, the operation mode (as start condition or as communication reservation) is determined according to the bus status (n = 0, 1). if the bus has been released .............................................. a start condition is generated if the bus has not been released (standby mode) .............. communication reservation to detect which operation mode has been determined for sttn, set sttn, wait for the wait period, then check mstsn (bit 7 of the iic status register n (iicsn)) (n = 0, 1). the wait periods, which should be set via software, are listed in table 11-10. these wait periods can be set by bits 3, 1, and 0 (smcn, cln1, and cln0) of iic clock select register n (iiccln) (n = 0, 1). table 11-10. wait periods smcn cln1 cln0 wait period 0 0 0 26 clocks 0 0 1 46 clocks 0 1 0 92 clocks 0 1 1 37 clocks 100 101 16 clocks 1 1 0 32 clocks 1 1 1 13 clocks remark n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 419 the communication reservation timing is shown below. figure 11-32. communication reservation timing 2 1 3456 2 1 3456 789 scln sdan program processing hardware processing write to iicn set spdn and intiicn sttn =1 communication reservation set stdn output by master with bus access iicn: iic shift register n sttn: bit 1 of iic control register n (iiccn) stdn: bit 1 of iic status register n (iicsn) spdn: bit 0 of iic status register n (iicsn) remark n = 0, 1 communication reservations are accepted via the following timing. after bit 1 (stdn) of iic status register n (iicsn) is set to 1, a communication reservation can be made by setting bit 1 (sttn) of iic control register n (iiccn) to 1 before a stop condition is detected (n = 0, 1). figure 11-33. timing for accepting communication reservations scln sdan stdn spdn standby mode remark n = 0, 1
chapter 11 serial interface function 420 user ? s manual u15109ej3v0ud the communication reservation flowchart is illustrated below. figure 11-34. communication reservation flowchart (1) di set1 sttn define communication reservation wait cancel communication reservation no yes iicn xxh ei mstsn = 0? (communication reservation) note (generate start condition) sets sttn bit (communication reservation). secures wait period set by software (see table 11-10 ). confirmation of communication reservation clears user flag. iicn write operation defines that communication reservation is in effect (defines and sets user flag to any part of ram). note the communication reservation operation executes a write to iic shift register n (iicn) when a stop condition interrupt request occurs. remark n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 421 (2) when communication reservation function is disabled (iicrsvn of iicfn register = 1) when the sttn bit of the iiccn register is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. the following two statuses are included in the status where bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when lreln of iic control register n (iiccn) was set to 1) (n = 0, 1). to confirm whether the start condition was generated or request was rejected, check the stcfn flag of the iicfn register. the time shown in table 11-11 is required until the stcfn flag is set after setting sttn = 1. therefore, secure the time by software. table 11-11. wait time iiccen1 iiccen0 cln1 cln0 wait time 0 0 3 clocks 0 1 3 clocks 1 0 6 clocks 0011 3 n 0 1 1 1 6 clocks 1 0 1 1 9 clocks remarks 1. n: tm5 and tm6 outputs : don ? t care 2. n = 0, 1 caution if the slave status is entered by an address match or expansion code reception (timing shown in figure 11-35), do not set sttn to 1. when set, the communication reservation status is entered. figure 11-35. sttn = 1 setting disabled timing remark n = 0, 1 sdan ad6 ad5 ad4 ad3 ad2 ad1 ad0 d7 d6 d5 d2 d1 d0 ack r/w ack scln iicbsyn when coin = 1 or excn = 1, setting sttn = 1 is disabled start condition stop condition rising edge of 8th address clock
chapter 11 serial interface function 422 user ? s manual u15109ej3v0ud figure 11-36. communication reservation flowchart (2) di ei di no yes no yes iicbsyn = 0 ? set1 sttn ei stcfn = 0 ? iicn h set sttn bit wait time (table 11-11) is secured by software iicn write operation bus communicating status wait master communication stopped remark n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 423 11.5.13 cautions (1) when stcenn of iic flag register n (iicfn) = 0 immediately after the i 2 cn operation is enabled, the bus communication status (iicbsyn of iicfn register = 1) is recognized regardless of the actual bus status. to execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication. use the following sequence for generating a stop condition. <1> set iic clock select register n (iiccln). <2> set iicen of the iic control register n (iiccn). <3> set sptn of iiccn. (2) when stcenn of iic flag register n (iicfn) = 1 immediately after i 2 cn operation is enabled, the bus released status (iicbsyn of iicfn register = 0) is recognized regardless of the actual bus status. to issue the first start condition (sttn of iiccn register = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. remark n = 0, 1
chapter 11 serial interface function 424 user ? s manual u15109ej3v0ud 11.5.14 communication operations (1) master operations (1) the following shows the flowchart for master communication when the communication reservation function is enabled (iicrsvn = 0) and the master operation is started after a stop condition is detected (stcenn = 0). figure 11-37. master operation flowchart (1) iiccn h iicen = spien = wtimn = 1 iiccln h select transfer clock sttn = 1 start acken = 0 no no no no no no no no no yes yes yes yes yes yes yes intiicn = 1? wtimn = 0 acken = 1 intiicn = 1? intiicn = 1? trcn = 1? ackdn = 1? mstsn = 1? yes no intiicn = 1? intiicn = 1? ackdn = 1? wreln = 1 start reception yes (stop condition detection) wait wait time is secured by software (see table 11-10 ) yes (start condition generation) communication reservation start iicn write transfer stop condition detection, start condition generation by communication reservation generate stop condition (no slave with matching address) no (receive) address transfer completion yes (transmit) end start iicn write transfer data processing transfer completed? generate stop condition sptn = 1 (restart) end transfer completed? data processing remark n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 425 (2) master operations (2) the following shows the flowchart for master communication when the communication reservation function is disabled (iicrsvn = 1) and the master operation is started without detecting a stop condition (stcenn = 1). figure 11-38. master operation flowchart (2) no (receive) iiccln h iicfn h iiccn h iicen = spien = wtimn = 1 sttn = 1 start no yes iicbsyn = 0? no yes wtimn = 0 acken = 1 wreln = 1 start reception acken = 0 sptn = 1 generate stop condition no yes yes (transmit) intiicn = 1? no yes yes intiicn = 1? no yes intiicn = 1? no yes ackdn = 1? no yes no ackdn = 1? trcn = 1? stcfn = 0? end transfer clock selection iicfn register setting iiccn register initial setting wait time is secured by software (see table 11-11 ) insert wait start iicn write transfer stop master communication master communication is stopped because bus is occupied yes (address transfer completion) start iicn write transfer generate stop condition (no slave with matching address) end data processing data processing reception completed? transfer completed? (restart) remark n = 0, 1
chapter 11 serial interface function 426 user ? s manual u15109ej3v0ud (3) slave operation the following shows the flowchart for slave communication. figure 11-39. slave operation flowchart iiccn h iicen = 1 wreln = 1 start reception start acken = 0 lreln = 1 no yes no no no no no no yes no yes yes yes start (restart detection) yes yes wtimn = 0 acken = 1 intiicn = 1? yes intiicn = 1? wtimn = 1 start iicn write transfer intiicn = 1? excn = 1? coin = 1? trcn = 1? ackdn = 1? start or stop transfer completed? communicate? no (receive) yes (transmit) data processing data processing end stop (stop condition detection) remark n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 427 11.5.15 timing of data communication when using i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits the trcn bit (bit 3 of iic status register n (iicsn)), which specifies the data transfer direction, and then starts serial communication with the slave device. the shift operation of iic bus shift register n (iicn) is synchronized with the falling edge of the serial clock (scln). the transmit data is transferred to the so latch and is output (msb first) via the sdan pin. data input via the sdan pin is captured by iicn at the rising edge of scln. the data communication timing is shown below. remark n = 0, 1
chapter 11 serial interface function 428 user ? s manual u15109ej3v0ud figure 11-40. example of master to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l l h h h l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iicn address iicn data iicn ffh transmit start condition receive (when exc = 1) note note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 429 figure 11-40. example of master to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h l l l l l l h h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iicn data iicn ffh note iicn ffh note iicn data transmit receive note note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1
chapter 11 serial interface function 430 user ? s manual u15109ej3v0ud figure 11-40. example of master to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l l h h h l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn data iicn address iicn ffh note iicn ffh note stop condition start condition transmit note note (when spien = 1) receive (when spien = 1) note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 431 figure 11-41. example of slave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l h h l acken mstsn sttn l l sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iicn address iicn ffh note note iicn data start condition note to cancel master wait, write ffh to iicn or set wreln. remark n = 0, 1
chapter 11 serial interface function 432 user ? s manual u15109ej3v0ud figure 11-41. example of slave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h h l l l l l l h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iicn data iicn data iicn ffh note iicn ffh note note to cancel master wait, write ffh to iicn or set wreln. remark n = 0, 1
chapter 11 serial interface function user ? s manual u15109ej3v0ud 433 figure 11-41. example of slave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l h h acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn address iicn ffh note note iicn data stop condition start condition (when spien = 1) n ? ack (when spien = 1) note to cancel master wait, write ffh to iicn or set wreln. remark n = 0, 1
chapter 11 serial interface function user?s manual u15109ej3v0ud 434 11.6 asynchronous serial interface (uart0 to uart3) uartn (n = 0 to 3) has the following two operation modes. (1) operation stop mode in this mode, serial transfers are not performed, thus enabling a reduction in power consumption. (2) asynchronous serial interface mode this mode enables full-duplex operation in which one byte of data after the start bit is transmitted and received. the on-chip dedicated uartn baud rate generator enables communications using a wide range of selectable baud rates. in addition, a baud rate based on divided-clock input to the asckn pin can also be defined. the uartn baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). 11.6.1 configuration the uartn includes the following hardware. table 11-12. configuration of uartn item configuration registers transmit shift registers 0 to 3 (txs0 to txs3) receive buffer registers 0 to 3 (rxb0 to rxb3) control registers asynchronous serial interface mode registers 0 to 3 (asim0 to asim3) asynchronous serial interface status registers 0 to 3 (asis0 to asis3) baud rate generator control registers 0 to 3 (brgc0 to brgc3) baud rate generator mode control registers 00 to 03 (brgmc00 to brgmc03) baud rate generator mode control registers 10 to 13 (brgmc10 to brgmc13)
chapter 11 serial interface function user?s manual u15109ej3v0ud 435 figure 11-42. block diagram of uartn baud rate generator f xx to f xx /2 9 txdn asckn rxdn intstn intsrn internal bus selector 8 8 receive shift register n (rxn) receive buffer register n (rxbn) 8 transmit control parity addition receive control parity check transmit shift register n (txsn) tmx output remarks 1. n = 0 to 3 2. tmx output is as shown below. when n = 0, 2: tm6 output when n = 1, 3: tm5 output (1) transmit shift registers 0 to 3 (txs0 to txs3) txsn is the register for setting transmit data. data written to txsn is transmitted as serial data. when the data length is set as 7 bits, bit 0 to bit 6 of the data written to txsn is transmitted as serial data. writing data to txsn starts the transmit operation. txsn is written by an 8-bit memory manipulation instruction. it cannot be read. reset input sets these registers to ffh. caution do not write to txsn during a transmit operation. (2) receive shift registers 0 to 3 (rx0 to rx3) the rxn register converts serial data input via the rxdn pin to parallel data. when one byte of data is received at rxn, the received data is transferred to receive buffer registers n (rxbn). rxn cannot be manipulated directly by a program. (3) receive buffer registers 0 to 3 (rxb0 to rxb3) rxbn is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred. when the data length is set as 7 bits, received data is sent to bit 0 to bit 6 of rxbn. in rxbn, the msb must be set to 0. rxbn is read by an 8-bit memory manipulation instruction. it cannot be written. reset input sets rxbn to ffh.
chapter 11 serial interface function user?s manual u15109ej3v0ud 436 (4) transmission controller the transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register n (txsn), based on the values set to asynchronous serial interface mode register n (asimn). (5) reception controller the reception controller controls receive operations based on the values set to asynchronous serial interface mode register n (asimn). during a receive operation, it performs error checking, such as for parity errors, and sets various values to asynchronous serial interface status register n (asisn) according to the type of error that is detected. 11.6.2 uartn control registers uartn is controlled by the following registers (n = 0 to 3). ? asynchronous serial interface mode register n (asimn) ? asynchronous serial interface status register n (asisn) ? baud rate generator control register n (brgcn) ? baud rate generator mode control registers n0, n1 (brgmcn0, brgmcn1)
chapter 11 serial interface function user?s manual u15109ej3v0ud 437 (1) asynchronous serial interface mode registers 0 to 3 (asim0 to asim3) asimn is an 8-bit register that controls uartn?s serial transfer operations. asimn can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r/w address: asim0: fffff300h asim1: fffff310h asim2: fffff230h asim3: fffff2b0h <7><6>543210 asimn txen rxen ps1n ps0n ucln sln isrmn 0 (n = 0 to 3) txen rxen operating mode rxdn/pxx pin function txdn/pxx pin function 0 0 operation stopped port function port function 0 1 uartn mode (receive only) serial function port function 1 0 uartn mode (transmit only) port function serial function 1 1 uartn mode (transmit and receive) serial function serial function ps1n ps0n parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity ucln character length specification 0 7 bits 1 8 bits sln stop bit length specification for transmit data 01 bit 1 2 bits isrmn receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs cautions 1. do not switch the operating mode until after the current serial transmit/receive operation has stopped. 2. receive error interrupts are not provided in the v850/sc1, v850/sc2, and v850/sc3. to detect receive errors, always set isrmn to 0. 3. always set bit 0 to 0.
chapter 11 serial interface function user?s manual u15109ej3v0ud 438 (2) asynchronous serial interface status registers 0 to 3 (asis0 to asis3) when a receive error occurs in asynchronous serial interface mode, these registers indicate the type of error. asisn can be read using an 8-bit or 1-bit memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r address: asis0: fffff302h asis1: fffff312h asis2: fffff232h asis3: fffff2b2h 76543<2><1><0> asisn 0 0 0 0 0 pen fen oven (n = 0 to 3) pen parity error flag 0 no parity error 1 parity error (transmit data parity does not match) fen framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) oven overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if the stop bit length has been set as two bits by setting bit 2 (sln) of asynchronous serial interface mode register n (asimn), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of receive buffer register n (rxbn) when an overrun error has occurred. until the contents of rxbn are read, further overrun errors will occur when receiving data.
chapter 11 serial interface function user?s manual u15109ej3v0ud 439 (3) baud rate generator control registers 0 to 3 (brgc0 to brgc3) these registers set the serial clock for uartn. brgcn can be set by an 8-bit memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r/w address: brgc0: fffff304h brgc1: fffff314h brgc2: fffff234h brgc3: fffff2b4h 76543210 brgcn mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 (n = 0 to 3) md ln7 md ln6 md ln5 md ln4 md ln3 md ln2 md ln1 md ln0 selection of input clock k 00000 setting prohibited ? 00001000f sck /8 8 00001001f sck /9 9 00001010f sck /10 10 00001011f sck /11 11 00001100f sck /12 12 00001101f sck /13 13 00001110f sck /14 14 00001111f sck /15 15 00010000f sck /16 16 11111111f sck /255 255 cautions 1. the value of brgcn becomes 00h after reset. before starting operation, select a setting other than ?setting prohibited?. selecting the ?setting prohibited? setting in stop mode does not cause any problems. 2. if brgcn is written during communication processing, the output of the baud rate generator will be disturbed and communication will not be performed normally. therefore, do not write to brgcn during communication processing. remark f sck : source clock of 8-bit counter
chapter 11 serial interface function user?s manual u15109ej3v0ud 440 (4) baud rate generator mode control registers n0, n1 (brgmcn0, brgmcn1) these registers set the uartn source clock. brgmcn0 and brgmcn1 are set by an 8-bit memory manipulation instruction (n = 0 to 3). reset input sets these registers to 00h. after reset: 00h r/w address: brgmc01: fffff320h brgmc11: fffff322h brgmc21: fffff23ch brgmc31: fffff2bch 76543210 brgmcn10000000tpsn3 (n = 0 to 3) after reset: 00h r/w address: brgmc00: fffff30eh brgmc10: fffff31eh brgmc20: fffff23ah brgmc30: fffff2bah 76543210 brgmcn0 0 0 0 0 0 tpsn2 tpsn1 tpsn0 (n = 0 to 3) tpsn3 tpsn2 tpsn1 tpsn0 8-bit counter source clock selection m 0 0 0 0 external clock (asckn) ? 0001f xx 0 0010f xx /2 1 0011f xx /4 2 0100f xx /8 3 0101f xx /16 4 0110f xx /32 5 0 1 1 1 at n = 0, 2: tm6 output at n = 1, 3: tm5 output ? 1000f xx /64 6 1001f xx /128 7 1010f xx /256 8 1011f xx /512 9 1100 ? 1101 ? 1110 ? 1111 setting prohibited ? cautions 1. if brgmcn0 or n1 is written during communication processing, the output of the baud rate generator will be disturbed and communication will not be performed normally. therefore, do not write to brgmcn0 or n1 during communication processing. 2. always set bit 7 to 3 of brgmcn0 to 0. remarks 1. source clock of 8-bit counter: f sck 2. if the selected clock is specified as a timer output, the p17/t05/ti5 and p30/t06/ti6 pins do not need to be in timer output mode.
chapter 11 serial interface function user?s manual u15109ej3v0ud 441 11.6.3 operations uartn has the following two operation modes. ? operation stopped mode ? asynchronous serial interface mode (1) operation stopped mode in this mode, serial transfers are not performed, thus enabling a reduction in power consumption. in operation stopped mode, pins can be used as ordinary port pins. (a) register settings operation stopped mode settings are made via bits txen and rxen of asynchronous serial interface mode register n (asimn). figure 11-43. asimn setting (operation stopped mode) after reset: 00h r/w address: asim0: fffff300h asim1: fffff310h asim2: fffff230h asim3: fffff2b0h <7><6>543210 asimn txen rxen ps1n ps0n ucln sln isrmn 0 (n = 0 to 3) txen rxen operating mode rxdn/pxx pin function txdn/pxx pin function 0 0 operation stopped port function port function cautions 1. do not switch the operating mode until after the current serial transmit/receive operation has stopped. 2. always set bit 0 to 0.
chapter 11 serial interface function user?s manual u15109ej3v0ud 442 (2) asynchronous serial interface mode this mode enables full-duplex operation in which one byte of data after the start bit is transmitted and received. the on-chip dedicated uartn baud rate generator enables communications using a wide range of selectable baud rates. the uartn baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). (a) register settings the asynchronous serial interface mode settings are made via asimn, brgcn, brgmcn0, and brgmcn1 (n = 0 to 3). figure 11-44. asimn setting (asynchronous serial interface mode) after reset: 00h r/w address: asim0: fffff300h asim1: fffff310h asim2: fffff230h asim3: fffff2b0h <7><6>543210 asimn txen rxen ps1n ps0n ucln sln isrmn 0 (n = 0 to 3) txen rxen operating mode rxdn/pxx pin function txdn/pxx pin function 0 1 uartn mode (receive only) serial function port function 1 0 uartn mode (transmit only) port function serial function 1 1 uartn mode (transmit and receive) serial function serial function ps1n ps0n parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity ucln character length specification 0 7 bits 1 8 bits sln stop bit length specification for transmit data 01 bit 1 2 bits isrmn receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs cautions 1. do not switch the operating mode until after the current serial transmit/receive operation has stopped. 2. receive error interrupts are not provided in the v850/sc1, v850/sc2, and v850/sc3. to detect receive errors, always set isrmn to 0. 3. always set bit 0 to 0.
chapter 11 serial interface function user?s manual u15109ej3v0ud 443 figure 11-45. asisn setting (asynchronous serial interface mode) after reset: 00h r address: asis0: fffff302h asis1: fffff312h asis2: fffff232h asis3: fffff2b2h 76543<2><1><0> asisn 0 0 0 0 0 pen fen oven (n = 0 to 3) pen parity error flag 0 no parity error 1 parity error (transmit data parity does not match) fen framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) oven overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if the stop bit length has been set as two bits by setting bit 2 (sln) in the asynchronous serial interface mode register n (asimn), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of receive buffer register n (rxbn) when an overrun error has occurred. until the contents of rxbn are read, further overrun errors will occur when receiving data.
chapter 11 serial interface function user?s manual u15109ej3v0ud 444 figure 11-46. brgcn setting (asynchronous serial interface mode) after reset: 00h r/w address: brgc0: fffff304h brgc1: fffff314h brgc2: fffff234h brgc3: fffff2b4h 76543210 brgcn mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 (n = 0 to 3) md ln7 md ln6 md ln5 md ln4 md ln3 md ln2 md ln1 md ln0 input clock selection k 00000 setting prohibited ? 00001000f sck /8 8 00001001f sck /9 9 00001010f sck /10 10 00001011f sck /11 11 00001100f sck /12 12 00001101f sck /13 13 00001110f sck /14 14 00001111f sck /15 15 00010000f sck /16 16 11111111f sck /255 255 cautions 1. reset input sets brgcn to 00h. before starting operation, select a setting other than ?setting prohibited?. selecting ?setting prohibited? setting in stop mode does not cause any problems. 2. if brgcn is written during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. therefore, do not write to brgcn during communication processing. remark f sck : source clock of 8-bit counter
chapter 11 serial interface function user?s manual u15109ej3v0ud 445 figure 11-47. brgmcn0 and brgmcn1 settings (asynchronous serial interface mode) after reset: 00h r/w address: brgmc01: fffff320h brgmc11: fffff322h brgmc21: fffff23ch brgmc31: fffff2bch 76543210 brgmcn10000000tpsn3 (n = 0 to 3) after reset: 00h r/w address: brgmc00: fffff30eh brgmc10: fffff31eh brgmc20: fffff23ah brgmc30: fffff2bah 76543210 brgmcn0 0 0 0 0 0 tpsn2 tpsn1 tpsn0 (n = 0 to 3) tpsn3 tpsn2 tpsn1 tpsn0 8-bit counter source clock selection m 0 0 0 0 external clock (asckn) ? 0001f xx 0 0010f xx /2 1 0011f xx /4 2 0100f xx /8 3 0101f xx /16 4 0110f xx /32 5 0 1 1 1 at n = 0, 2: tm6 output at n = 1, 3: tm5 output ? 1000f xx /64 6 1001f xx /128 7 1010f xx /256 8 1011f xx /512 9 1100 ? 1101 ? 1110 ? 1111 setting prohibited ? cautions 1. if brgmcn0 or n1 is written during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. therefore, do not write to brgmcn0 or brgmcn1 during communication processing. 2. always set bits 7 to 3 of brgmcn0 to 0. remarks 1. f xx : main clock oscillation frequency 2. if the selected clock is specified as a timer output, the p17/t05/ti5 and p30/t06/ti6 pins do not need to be in timer output mode.
chapter 11 serial interface function user?s manual u15109ej3v0ud 446 (b) baud rate the baud rate transmit/receive clock that is generated is obtained by dividing the main clock. ? generation of baud rate transmit/receive clock using main clock the transmit/receive clock is obtained by dividing the main clock. the following equation is used to obtain the baud rate from the main clock. [baud rate] = [hz] f xx : main clock oscillation frequency m: value set by tpsn3 to tpsn0 (0 m 9) k: value set by mdln7 to mdln0 (8 k 255) ? baud rate tolerance the baud rate tolerance depends on the number of bits in a frame and the counter division ratio [1/(16 + k)]. table 11-13 shows the relationship between the main clock and the baud rate, and figure 11-48 shows an example of the allowable baud rate error range. table 11-13. relationship between main clock and baud rate f xx = 20 mhz f xx = 18.87 mhz f xx = 16 mhz baud rate (bps) k m error (%) k m error (%) k m error (%) 32 ? ? ? ? ? ? ? ? ? 64 ? ? ? ? ? ? 244 9 0.06 128 152 9 ?0.39 144 9 ?0.02 244 8 0.06 300 130 8 0.16 123 8 ?0.12 208 7 0.16 600 130 7 0.16 123 7 ?0.12 208 6 0.16 1200 130 6 0.16 123 6 ?0.12 208 5 0.16 2400 130 5 0.16 123 5 ?0.12 208 4 0.16 4800 130 4 0.16 123 4 ?0.12 208 3 0.16 9600 130 3 0.16 123 3 ?0.12 208 2 0.16 19200 130 2 0.16 123 2 ?0.12 208 1 0.16 38400 130 1 0.16 123 1 ?0.12 208 0 0.16 76800 130 0 0.16 123 0 ?0.12 104 0 0.16 150000 67 0 ?0.50 63 0 ?0.16 53 0 0.63 300000 33 0 1.01 31 0 1.45 27 0 ?1.24 524000 19 0 0.44 18 0 0.03 15 0 1.78 1250000 8 0 0.00 ? ? ? ? ? ? remark f xx : main clock oscillation frequency f xx 2 m+1 k
chapter 11 serial interface function user?s manual u15109ej3v0ud 447 figure 11-48. allowable baud rate error range (when k = 16), including sampling errors basic timing (clock cycle t) start d0 d7 p stop high-speed clock (clock cycle t ? ) enabling normal reception start d0 d7 p stop low-speed clock (clock cycle t ? ) enabling normal reception start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t remark t: 8-bit counter ? s source clock cycle allowable baud rate error range (when k = 16) = 100 = 4.8438 (%) 15.5 320
chapter 11 serial interface function user ? s manual u15109ej3v0ud 448 (3) communication operations (a) data format as shown in figure 11-49, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. asynchronous serial interface mode register n (asimn) is used to set the character bit length, parity selection, and stop bit length within each data frame (n = 0 to 3). figure 11-49. format of transmit/receive data in asynchronous serial interface d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame ? start bit ............. 1 bit ? character bits ... 7 bits or 8 bits ? parity bit ........... even parity, odd parity, zero parity, or no parity ? stop bit(s) ........ 1 bit or 2 bits when 7 bits is selected as the number of character bits, only the lower 7 bits (from bit 0 to bit 6) are valid, so during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to 0. asynchronous serial interface mode register n (asimn) and baud rate generator control register n (brgcn) are used to set the serial transfer rate (n = 0 to 3). if a receive error occurs, information about the receive error can be ascertained by reading asynchronous serial interface status register n (asisn) (n = 0 to 3).
chapter 11 serial interface function user ? s manual u15109ej3v0ud 449 (b) parity types and operations the parity bit is used to detect bit errors in transfer data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd- number bit) can be detected. when zero parity or no parity is set, errors are not detected. (i) even parity ? during transmission the number of bits in transmit data including a parity bit is controlled so that the number of ? 1 ? bits is even. the value of the parity bit is as follows. if the transmit data contains an odd number of ? 1 ? bits: the parity bit value is ? 1 ? if the transmit data contains an even number of ? 1 ? bits: the parity bit value is ? 0 ? ? during reception the number of ? 1 ? bits among the receive data is counted, including a parity bit, and a parity error is generated when the result is an odd number. (ii) odd parity ? during transmission the number of bits in transmit data including a parity bit is controlled so that the number of ? 1 ? bits is odd. the value of the parity bit is as follows. if the transmit data contains an odd number of ? 1 ? bits: the parity bit value is ? 0 ? if the transmit data contains an even number of ? 1 ? bits: the parity bit value is ? 1 ? ? during reception the number of ? 1 ? bits among the receive data is counted, including a parity bit, and a parity error is generated when the result is an even number. (iii) zero parity during transmission, the parity bit is set to ? 0 ? regardless of the transmit data. during reception, the parity bit is not checked. therefore, no parity errors will be generated regardless of whether the parity bit is a ? 0 ? or a ? 1 ? . (iv) no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will be generated.
chapter 11 serial interface function user ? s manual u15109ej3v0ud 450 (c) transmission a transmit operation is started when transmit data is written to transmit shift register n (txsn). a start bit, parity bit, and stop bit(s) are automatically added to the data. starting a transmit operation shifts out the data in txsn, thereby emptying txsn, after which a transmission completion interrupt (intstn) is issued. the timing of the transmission completion interrupt is shown below. figure 11-50. timing of asynchronous serial interface transmission completion interrupt txdn (output) d0 d1 d2 d6 d7 parity stop start intstn (a) stop bit length: 1 txdn (output) d0 d1 d2 d6 d7 parity start intstn (b) stop bit length: 2 stop caution do not write to asynchronous serial interface mode register n (asimn) during a transmit operation. writing to asimn during a transmit operation may disable further transmit operations (in such cases, enter a reset to restore normal operation). whether or not a transmit operation is in progress can be determined via software using the transmission completion interrupt (intstn) or the interrupt request flag (stifn) set by intstn. remark n = 0 to 3
chapter 11 serial interface function user ? s manual u15109ej3v0ud 451 (d) reception a receive operation is enabled when bit 6 (rxen) of asynchronous serial interface mode register n (asimn) is set to 1, and input via the rxdn pin is sampled. the serial clock specified by brgcn is used when sampling the rxdn pin. when the rxdn pin goes low, the 8-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. if sampling the rxdn pin input with this start timing signal yields a low-level result, a start bit is recognized, after which the 8-bit counter is initialized and starts counting, and data sampling begins. after the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once reception of one data frame is completed, the receive data in the shift register is transferred to receive buffer register n (rxbn) and a reception completion interrupt (intsrn) occurs. even if an error has occurred, the receive data in which the error occurred is still transferred to rxbn. when an error occurs, instrn is generated if bit 1 (isrmn) of asimn is cleared (0). on the other hand, intsrn is not generated if the isrmn bit is set (1). the receive error type can be ascertained by reading the contents of asisn in the reception completion interrupt servicing (intsrn). if the rxen bit is reset to 0 during a receive operation, the receive operation is stopped immediately. at this time, the contents of rxbn and asisn do not change, nor does intsrn occur. the timing of the asynchronous serial interface reception completion interrupt is shown below. figure 11-51. timing of asynchronous serial interface reception completion interrupt caution be sure to read the contents of receive buffer register n (rxbn) even when a receive error has occurred. if the contents of rxbn are not read, an overrun error will occur during the next data receive operation and the receive error status will remain. remark n = 0 to 3 rxdn (input) d0 d1 d2 d6 d7 parity stop start intsrn
chapter 11 serial interface function user ? s manual u15109ej3v0ud 452 (e) receive error there are three types of error during a receive operation: parity errors, framing errors, and overrun errors. when, as the result of data reception, an error flag is set in asynchronous serial interface status register n (asisn). by reading the contents of asisn during receive completion interrupt servicing (intsrn), it is possible to detect which error has occurred at reception. the contents of asisn are reset (0) by reading receive buffer register n (rxbn) or receiving subsequent data (if there is an error in the subsequent data, the error flag is set). table 11-14. receive error causes receive error cause asisn value parity error parity specification at transmission and receive data parity do not match. 04h framing error stop bit is not detected. 02h overrun error reception of subsequent data was completed before data was read from the receive buffer register. 01h figure 11-52. receive error timing rxdn ( input ) intsrn note d7 d6 d2 d1 d0 parity stop start note even if a receive error occurs when the isrmn bit of asimn is set (1), intsrn is not generated. the receive error type can be ascertained by reading the contents of asisn in the reception completion interrupt servicing (intsrn). cautions 1. the contents of asynchronous serial interface status register n (asisn) are reset (0) by reading receive buffer register n (rxbn) or receiving subsequent data. to check the contents of an error, always read asisn before reading rxbn. 2. be sure to read receive buffer register n (rxbn) even when a receive error has occurred. if rxbn is not read out, an overrun error will occur during subsequent data reception and as a result receive errors will continue to occur. remark n = 0 to 3
chapter 11 serial interface function user ? s manual u15109ej3v0ud 453 11.6.4 standby function (1) operation in halt mode serial transfer is performed normally. (2) operation in stop and idle modes (a) when internal clock is selected as serial clock the operations of asynchronous serial interface mode register n (asimn), transmit shift register n (txsn), and receive buffer register n (rxbn) are stopped and their values immediately before the clock stopped are held. the txdn pin output holds the data immediately before the clock is stopped (in stop mode) during transmission. when the clock is stopped during reception, the receive data until the clock stopped is stored and subsequent receive operations are stopped. reception resumes upon clock restart. (b) when external clock is selected as serial clock serial transfer is performed normally.
user?s manual u15109ej3v0ud 454 chapter 12 a/d converter 12.1 function the a/d converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 channels of analog input signals (ani0 to ani11). the v850/sc1, v850/sc2, and v850/sc3 support low-speed conversion and a low-power-consumption mode. (1) hardware start conversion is started by trigger input (adtrg) (rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting a/d converter mode register 1 (adm1). one analog input channel is selected from ani0 to ani11, and a/d conversion is performed. if a/d conversion has been started by a hardware start, conversion stops once it has been completed, and an interrupt request (intad) is generated. if conversion has been started by a software start, conversion is performed repeatedly. each time conversion has been completed, intad is generated.
chapter 12 a/d converter user?s manual u15109ej3v0ud 455 the block diagram is shown below. figure 12-1. block diagram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 adcgnd intad 4 ads3 ads2 ads1 ads0 adcs trg fr2 fr1 fr0 ega1 ega0 adps selector sample & hold circuit adcgnd voltage comparator tap selector adtrg edge detector controller a/d conversion result register (adcr) trigger enable analog input channel specification register (ads) a/d converter mode register 1 (adm1) internal bus iead a/d converter mode register 2 (adm2) successive approximation register (sar) adcv dd
chapter 12 a/d converter 456 user ? s manual u15109ej3v0ud 12.2 configuration the a/d converter includes the following hardware. table 12-1. configuration of a/d converter item configuration analog inputs 12 channels (ani0 to ani11) registers successive approximation register (sar) a/d conversion result register (adcr) a/d conversion result register h (adcrh): only higher 8 bits can be read control registers a/d converter mode register 1 (adm1) a/d converter mode register 2 (adm2) analog input channel specification register (ads) (1) successive approximation register (sar) this register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the result of the comparison starting from the most significant bit (msb). when the comparison result has been held down to the least significant bit (lsb) (i.e., when a/d conversion has been completed), the contents of the sar are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr), a/d conversion result register h (adcrh) each time a/d conversion is complete, the result of the conversion is loaded to this register from the successive approximation register. the higher 10 bits of this register hold the result of the a/d conversion (the lower 6 bits are fixed to 0). this register is read using a 16-bit memory manipulation instruction. reset input sets adcr to 0000h. when using only higher 8 bits of the result of the a/d conversion, adcrh is read using an 8-bit memory manipulation instruction. reset input sets adcrh to 00h. caution writing to a/d converter mode register 1 (adm1) and the analog input channel specification register (ads) may cause the adcr contents to be undefined. therefore, read the conversion result during a/d conversion (adcs = 1). incorrect conversion results may be read if the timing is other than the above. (3) sample & hold circuit the sample & hold circuit samples each of the analog input signals sequentially sent from the input circuit, and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input signal with the output voltage of the series resistor string. (5) series resistor string the series resistor string is connected between adcv dd and adcgnd and generates a voltage for comparison with the analog input signal.
chapter 12 a/d converter user ? s manual u15109ej3v0ud 457 (6) ani0 to ani11 pins these are analog input pins for the 12 channels of the a/d converter, and are used to input analog signals to be converted into digital signals. pins other than ones selected as analog input with the analog input channel specification register (ads) can be used as input ports. caution make sure that the voltages input to ani0 through ani11 do not exceed the rated values. if a voltage higher than adcv dd or lower than adcgnd (even within the range of the absolute maximum ratings) is input to a channel, the conversion value of the channel is undefined, and the conversion values of the other channels may also be affected. (7) adcgnd pin this is the ground pin of the a/d converter. always make the potential at this pin the same as that at the gnd0 pin even when the a/d converter is not in use. (8) adcv dd pin this is the analog power supply pin of the a/d converter. always make the potential at this pin the same as that at the v dd0 pin even when the a/d converter is not in use.
chapter 12 a/d converter 458 user ? s manual u15109ej3v0ud 12.3 control registers the a/d converter is controlled by the following registers. ? a/d converter mode register 1 (adm1) ? analog input channel specification register (ads) ? a/d converter mode register 2 (adm2) (1) a/d converter mode register 1 (adm1) this register specifies the conversion time of the input analog signal to be converted into a digital signal, starting or stopping the conversion, and an external trigger. adm1 is set by an 8-bit or 1-bit memory manipulation instruction. reset input sets adm1 to 00h. (1/2) after reset: 00h r/w address: fffff3c0h <7><6>54321<0> adm1 adcs trg fr2 fr1 fr0 ega1 ega0 adps adcs a/d conversion control 0 conversion stopped 1 conversion enabled trg software start or hardware start selection 0 software start 1 hardware start
chapter 12 a/d converter user ? s manual u15109ej3v0ud 459 (2/2) selection of conversion time f xx adps fr2 fr1 fr0 conversion time note 1 + stabilization time note 2 20 mhz 18.87 mhz 16 mhz 0 0 0 0 168/f xx 8.4 s8.9 s setting prohibited 0 0 0 1 120/f xx 6.0 s6.4 s7.5 s 001084/f xx setting prohibited setting prohibited 5.25 s 001160/f xx setting prohibited setting prohibited setting prohibited 010048/f xx setting prohibited setting prohibited setting prohibited 010136/f xx setting prohibited setting prohibited setting prohibited 0 1 1 0 setting prohibited setting prohibited setting prohibited setting prohibited 011112/f xx setting prohibited setting prohibited setting prohibited 1 0 0 0 168/f xx + 64/f xx 8.4 + 3.2 s 8.9 + 3.4 s setting prohibited 1 0 0 1 120/f xx + 60/f xx 6.0 + 3.0 s 6.4 + 3.2 s 7.5 + 3.75 s 101084/f xx + 42/f xx setting prohibited setting prohibited 5.25 + 2.63 s 101160/f xx + 30/f xx setting prohibited setting prohibited setting prohibited 110048/f xx + 24/f xx setting prohibited setting prohibited setting prohibited 110136/f xx + 18/f xx setting prohibited setting prohibited setting prohibited 1 1 1 0 setting prohibited setting prohibited setting prohibited setting prohibited 111112/f xx + 6/f xx setting prohibited setting prohibited setting prohibited ega1 ega0 valid edge specification for external trigger signal 0 0 no edge detection 0 1 detected at falling edge 1 0 detected at rising edge 1 1 detected at both rising and falling edges adps comparator control while a/d conversion is stopped (adcs = 0) 0 comparator on 1 comparator off notes 1. conversion time (actual a/d conversion time). always set the time to 5 s conversion time 10 s. 2. stabilization time (setup time of a/d converter) each a/d conversion requires ? conversion time + stabilization time ? . there is no stabilization time when adps = 0. cautions 1. the a/d converter cannot be used when the operation frequency is 2.4 to 3.6 mhz. 2. cut the current consumption by setting the adps bit to 1 when the adcs bit is set to 0.
chapter 12 a/d converter 460 user ? s manual u15109ej3v0ud (2) analog input channel specification register (ads) this register specifies the port for inputting the analog voltage to be converted into a digital signal. ads is set by an 8-bit or 1-bit memory manipulation instruction. reset input sets ads to 00h. after reset: 00h r/w address: fffff3c2h 76543210 ads 0 0 0 0 ads3 ads2 ads1 ads0 ads3 ads2 ads1 ads0 analog input channel specification 0000ani0 0001ani1 0010ani2 0011ani3 0100ani4 0101ani5 0110ani6 0111ani7 1000ani8 1001ani9 1010ani10 1011ani11 other than above setting prohibited caution always set bits 7 to 4 to 0. (3) a/d converter mode register 2 (adm2) this register specifies connection/disconnection of adcv dd and the series resistor string. adm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets adm2 to 00h. after reset: 00h r/w address: fffff3c8h 7654321<0> adm2 0 0 0 0 0 0 0 iead iead a/d current cut control 0 cut between adcv dd and series resistor string 1 connect between adcv dd and series resistor string
chapter 12 a/d converter user ? s manual u15109ej3v0ud 461 12.4 operation 12.4.1 basic operation <1> select one channel whose analog signal is to be converted into a digital signal by using the analog input channel specification register (ads). <2> the sample & hold circuit samples the voltage input to the selected analog input channel. <3> after sampling for a specific time, the sample & hold circuit enters the hold status, and holds the input analog voltage until it has been converted into a digital signal. <4> set bit 9 of the successive approximation register (sar). the tap selector sets the voltage tap of the series resistor string to (1/2) adcv dd . <5> the voltage difference between the voltage tap of the series resistor string and the analog input voltage is compared by the voltage comparator. if the analog input voltage is greater than (1/2) adcv dd , the msb of the sar remains set. if the analog input voltage is less than (1/2) adcv dd , the msb is reset. <6> next, bit 8 of the sar is automatically set, and the analog input voltage is compared again. depending on the value of bit 9 to which the result of the preceding comparison has been set, the voltage tap of the series resistor string is selected as follows: ? bit 9 = 1: (3/4) adcv dd ? bit 9 = 0: (1/4) adcv dd the analog input voltage is compared with one of these voltage taps, and bit 8 of the sar is manipulated as follows depending on the result of the comparison. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage voltage tap: bit 8 = 0 <7> the above steps are repeated until the bit 0 of the sar has been manipulated. <8> when comparison of all the 10 bits of the sar has been completed, the valid digital value remains in the sar, and the value of the sar is transferred and latched to the a/d conversion result register (adcr). at the same time, an a/d conversion end interrupt request (intad) can be generated. caution the first conversion value immediately after setting adcs to 1 (from 0) may not satisfy the ratings.
chapter 12 a/d converter 462 user ? s manual u15109ej3v0ud figure 12-2. basic operation of a/d converter sar adcr intad conversion time sampling time sampling operation of a/d converter a/d conversion undefined conversion result conversion result a/d conversion is successively executed until bit 7 (adcs) of a/d converter mode register 1 (adm1) is reset (0) by software. if adm1 and the analog input channel specification register (ads) are written during a/d conversion, the conversion is initialized. if adcs is set (1) at this time, conversion is started from the beginning. reset input sets the a/d conversion result register (adcr) to 0000h.
chapter 12 a/d converter user ? s manual u15109ej3v0ud 463 12.4.2 input voltage and conversion result the analog voltages input to the analog input pins (ani0 to ani11) and the result of the a/d conversion (contents of the a/d conversion result register (adcr)) are related as follows: adcr = int( 1024 + 0.5) or, (adcr ? 0.5) v in < (adcr + 0.5) int ( ): function that returns integer of value in ( ) v in : analog input voltage adcv dd : a/d converter reference voltage adcr: value of the a/d conversion result register (adcr) the relationship between the analog input voltage and a/d conversion result is shown below. figure 12-3. relationship between analog input voltage and a/d conversion result 113253 2043 1022 20451023 2047 1 2048 1024 20481024 2048 1024 2048 1024 20481024 2048 0 1 2 3 1021 1022 1023 a/d conversion result (adcr) input voltage/adcv dd v in adcv dd adcv dd 1024 adcv dd 1024
chapter 12 a/d converter 464 user ? s manual u15109ej3v0ud 12.4.3 a/d converter operation mode in this mode one of the analog input channels ani0 to ani11 is selected by the analog input channel specification register (ads) and a/d conversion is executed. a/d conversion can be started in the following two ways: ? hardware start: started by trigger input (adtrg) (rising edge, falling edge, or both rising and falling edges can be specified) ? software start: started by setting a/d converter mode register 1 (adm1) the result of the a/d conversion is stored in the a/d conversion result register (adcr) and an interrupt request signal (intad) is generated at the same time.
chapter 12 a/d converter user ? s manual u15109ej3v0ud 465 (1) a/d conversion by hardware start a/d conversion is on standby if bit 6 (trg) and bit 7 (adcs) of a/d converter mode register 1 (adm1) are set to 1. when an external trigger signal is input, the a/d converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ads) into a digital signal. when a/d conversion is complete, the result of the conversion is stored in the a/d conversion result register (adcr), and an interrupt request signal (intad) is generated. once a/d conversion has been started and completed, conversion is not started again unless a new external trigger signal is input. if data with adcs set to 1 is written to adm during a/d conversion, the conversion under execution is stopped, and the a/d converter stands by until a new external trigger signal is input. if the external trigger signal is input, a/d conversion is executed again from the beginning. if data with adcs set to 0 is written to adm1 during a/d conversion, the conversion is immediately stopped. figure 12-4. a/d conversion by hardware start (with falling edge specified) rewriting ads adcs = 1, trg = 1 rewriting ads adcs = 1, trg = 1 a/d conversion adcr intad anin standby status standby status standby status anin anin anim anim anim anin anin anin anim anim external trigger input signal remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11
chapter 12 a/d converter 466 user ? s manual u15109ej3v0ud (2) a/d conversion by software start if bit 6 (trg) and bit 7 (adcs) of a/d converter mode register 1 (adm1) are set to 1, the a/d converter starts converting the voltage applied to an analog input pin specified by the analog input channel specification register (ads) into a digital signal. when a/d conversion is complete, the result of the conversion is stored in the a/d conversion result register (adcr), and an interrupt request signal (intad) is generated. once a/d conversion has been started and completed, the next conversion is started immediately. a/d conversion is repeated until new data is written to ads. if ads is rewritten during a/d conversion, the conversion under execution is stopped, and conversion of the newly selected analog input channel is started. if data with adcs set to 0 is written to adm1 during a/d conversion, the conversion is immediately stopped. figure 12-5. a/d conversion by software start rewriting ads adcs = 1, trg = 0 rewriting ads adcs = 1, trg = 0 adcs = 0 a/d conversion adcr intad anin anin anin anim anim anin anin anim ? ? ? ? ? conversion stopped. conversion result does not remain. stopped remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11
chapter 12 a/d converter user ? s manual u15109ej3v0ud 467 12.5 low-power-consumption mode the v850/sc1, v850/sc2, and v850/sc3 feature a function that can cut or connect the current between adcv dd and the series resistor string. switching can be performed by setting a/d converter mode register 2 (adm2). when not using the a/d converter, cut off the tap selector (a function to reduce current) from the voltage supply block (adcv dd ) while a/d conversion is stopped (adcs = 0) to cut the current consumption. ? set the adps bit of a/d converter mode register 1 (adm1) to 1. ? set the adps bit of a/d converter mode register 2 (adm1) to 0. when the adps bit is reset to 0 (comparator on), stabilization time (5 s max.) is required before starting a/d conversion. therefore, secure a wait of at least 5 s by software. 12.6 cautions (1) current consumption in standby mode the a/d converter stops operation in the idle and stop modes (operable in the halt mode). at this time, the current consumption of the a/d converter can be reduced by stopping the conversion (by re-setting bit 7 (adcs) of a/d converter mode register 1 (adm1) to 0). (2) input range of ani0 to ani11 keep the input voltage of the ani0 through ani11 pins to within the rated range. if a voltage greater than adcv dd or lower than adcgnd (even within the range of the absolute maximum ratings) is input to a channel, the converted value of the channel becomes undefined. moreover, the values of the other channels may also be affected. (3) conflict <1> conflict between writing a/d conversion result register (adcr) and reading adcr at end of conversion reading adcr takes precedence. after adcr has been read, a new conversion result is written to adcr. <2> conflict between writing adcr and external trigger signal input at end of conversion the external trigger signal is not input during a/d conversion. therefore, the external trigger signal is not accepted during the writing of adcr. <3> conflict between writing of adcr and writing a/d converter mode register 1 (adm1) or analog input channel specification register (ads) when adm1 or ads is written immediately after adcr is written following the end of a/d conversion, an undefined value is stored in the adcr register, so the conversion result is not guaranteed.
chapter 12 a/d converter 468 user ? s manual u15109ej3v0ud (4) countermeasures against noise to keep the resolution of 10 bits, it is necessary to prevent noise from being superimposed on the ani0 to ani11 pins. the higher the output impedance of the analog input source, the heavier the influence of noise. to lower noise, connecting an external capacitor as shown below is recommended. figure 12-6. handling of analog input pin adcv dd v dd0 gnd0 adcgnd clamp with diode with a low v f (0.3 v max.) if noise higher than adcv dd or lower than adcgnd may be generated. c = 100 to 1000 pf (5) ani0 to ani11 the analog input (ani0 to ani11) pins function alternately as port pins. to execute a/d conversion with any of ani0 to ani11 selected, do not execute an instruction that inputs data to the port during conversion; otherwise, the resolution may drop. if a digital pulse is applied to pins adjacent to the pin whose input signal is converted into a digital signal, the expected a/d conversion result may not be obtained because of the influence of coupling noise. therefore, do not apply a pulse to the adjacent pins.
chapter 12 a/d converter user ? s manual u15109ej3v0ud 469 (6) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the analog input channel specification register (ads) are changed. if the analog input pin is changed during conversion, therefore, the result of the a/d conversion of the preceding analog input signal and the conversion end interrupt request flag may be set immediately before ads is rewritten. if adif is read immediately after ads has been rewritten, it may be set despite the fact that conversion of the newly selected analog input signal has not been completed yet. when stopping a/d conversion and then resuming, clear adif before resuming conversion. figure 12-7. a/d conversion end interrupt generation timing rewriting ads (anin conversion starts) rewriting ads (anim conversion starts) adif is set but conversion of anim is not completed. a/d conversion adcr intad anin anin anim anim anim anin anin anim remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11
chapter 12 a/d converter 470 user ? s manual u15109ej3v0ud (7) adcv dd pin the adcv dd pin is the power supply pin of the analog circuit, and also supplies power to the input circuit of ani0 to ani11. even in an application where a back-up power supply is used, therefore, be sure to apply the same voltage as the v dd0 pin to the adcv dd pin as shown below. figure 12-8. handling of adcv dd pin v dd0 gnd0 adcv dd adcgnd main power supply back-up capacitor (8) reading out a/d converter result register (adcr) writing to a/d converter mode register 1 (adm1) and the analog input channel specification register (ads) may cause the adcr contents to be undefined. therefore, read the conversion result during a/d conversion (adcs = 1). incorrect conversion results may be read if the timing is other than the above.
user?s manual u15109ej3v0ud 471 chapter 13 dma functions 13.1 functions the dma (direct memory access) controller transfers data between memory and peripheral i/os based on dma requests sent from on-chip peripheral hardware (such as the serial interfaces, timer, or a/d converter). this product includes six independent dma channels that can transfer data in 8-bit and 16-bit units. the maximum number of transfers is 256 (when transferring data in 8-bit units). after a dma transfer has occurred a specified number of times, dma transfer completion interrupt (intdma0 to intdma5) requests are output individually from the various channels. the priority levels of the dma channels are fixed as follows for simultaneous generation of multiple dma transfer requests. dma0 > dma1 > dma2 > dma3 > dma4 > dma5 13.2 transfer completion interrupt request after a dma transfer has occurred a specified number of times and the tcn bit in corresponding dma channel control register is 0 to 5 (dchc0 to dchc5) has been set to 1, a dma transfer completion interrupt request (intdma0 to intdma5) for the interrupt controller occurs on each channel.
chapter 13 dma functions user ? s manual u15109ej3v0ud 472 13.3 configuration figure 13-1. dma block diagram internal bus dma peripheral i/o address register n (dioan) dma byte count register n (dbcn) dma start factor expansion register (dmas) dma channel control register n (dchcn) dma internal ram address register n (dran) dma transfer start factor (int signal) dma transfer request control channel control cpu intdman dma transfer acknowledge signal interface control internal ram peripheral i/o register remark n = 0 to 5 (1) dma transfer request control block the dma transfer request control block generates a dma transfer request signal for the cpu when the dma transfer start factor (int signal) specified by dma channel control register n (dchcn) and the dma start factor expansion register (dmas) is input. when the dma transfer request signal is acknowledged, the cpu generates a dma transfer acknowledge signal for the channel control block and interface control block after the current cpu processing has finished. (2) channel control block the channel control block distinguishes the dma transfer channel (dma0 to dma5) to be transferred and controls the internal rom, peripheral i/o addresses, and access cycles (internal ram: 1 clock, peripheral i/o register: 3 clocks) set by the peripheral i/o registers of the channel to be transferred, the transfer direction, and the transfer count. in addition, it also controls the priority order when two or more dman transfer start factors (int signals) are generated simultaneously.
chapter 13 dma functions user ? s manual u15109ej3v0ud 473 473 13.4 control registers (1) dma peripheral i/o address registers 0 to 5 (dioa0 to dioa5) these registers are used to set the peripheral i/o register address for dma channel n. these registers can be read/written in 16-bit units. after reset: undefined r/w address: dioa0 fffff180h dioa3 fffff1b0h dioa1 fffff190h dioa4 fffff1c0h dioa2 fffff1a0h dioa5 fffff100h 15 14 13 12 11 10 9 1 0 dioan 000000 ioan9 to ioan1 0 (n = 0 to 5) caution the following peripheral i/o registers must not be set. p4, p5, p6, p9, p11, pm4, pm5, pm6, pm9, pm11, mm, dwc, bcc, syc, psc, pcc, sys, prcmd, dioan, dran, dbcn, dchcn, corcn, corrq, coradn, interrupt control register (xxicn), ispr, pocs, vm45c, fcan register (see chapter 19) (2) dma internal ram address registers 0 to 5 (dra0 to dra5) these registers set dma channel n internal ram addresses (n = 0 to 5). since each product has a different internal ram capacity, the internal ram areas that are usable for dma differ depending on the product. the internal ram areas that can be set in the dran register for each product are shown below. table 13-1. internal ram area usable in dma product internal ram capacity ram size usable in dma ram area usable in dma v850/sc1 pd703068y, 70f3089y v850/sc2 pd703069y, 70f3089y v850/sc3 pd703088y, 703089y, 70f3089y 24 kb 16 kb xxff9000h to xxffbfffh, xxffe000h to xxffefffh an address is incremented after each transfer is completed, when the dadn bit of the dchdn register is 0. the incrementation value is ? 1 ? during 8-bit transfers and ? 2 ? during 16-bit transfers (n = 0 to 5). these registers are can be read/written in 16-bit units. after reset: undefined r/w address: dra0 fffff182h dra3 fffff1b2h dra1 fffff192h dra4 fffff1c2h dra2 fffff1a2h dra5 fffff1d2h 15 14 13 0 dran 00 ran13 to ran00 (n = 0 to 5)
chapter 13 dma functions user ? s manual u15109ej3v0ud 474 the following shows the correspondence between the dran setting value and the internal ram area. (a) v850/sc1 ( pd703068y, 70f3089y) v850/sc2 ( pd703069y, 70f3089y) v850/sc3 ( pd703088y, 703089y, 70f3089y) set the dran register to a value in the range of 0000h to 0fffh or 1000h to 3fffh (n = 0 to 5). figure 13-2. correspondence between dran setting value and internal ram xxffffffh xxff9000h xxff8fffh xxfff000h xxffefffh xxff8000h xxff7fffh access-prohibited area expansion rom area internal peripheral i/o area internal ram area (dran setting value) (0fffh) (1000h) (0000h) (3fffh) xxffc000h xxffbfffh 12 kb (usable for dma) 4 kb (usable for dma) xxffe000h xxffdfffh caution do not set odd addresses for 16-bit transfer (dchcn register dsn = 1). remark the values in parentheses indicate the dran register setting values.
chapter 13 dma functions user ? s manual u15109ej3v0ud 475 475 (3) dma byte count registers 0 to 5 (dbc0 to dbc5) these are 8-bit registers that are used to set the number of transfers for dma channel n. the remaining number of transfers is retained during dma transfer. the transfer count is decremented by 1 per transfer if the transfer is a byte (8-bit) transfer, and by 2 per transfer if the transfer is a 16-bit transfer. transfer ends when a borrow operation occurs. accordingly, ? number of transfers ? 1 ? should be set for byte (8-bit) transfers and ? (number of transfers ? 1) 2 ? should be set for 16-bit transfers. these registers can be read/written in 8-bit units. after reset: undefined r/w address: dbc0 fffff184h dbc3 fffff1b4h dbc1 fffff194h dbc4 fffff1c4h dbc2 fffff1a4h dbc5 fffff1d4h 76543210 dbcn bcn7 bcn6 bcn5 bcn4 bcn3 bcn2 bcn1 bcn0 (n = 0 to 5) caution values set to bit 0 are ignored during 16-bit transfers. (4) dma start factor expansion register (dmas) this is an 8-bit register for expanding the factors that start dma. the dma start factor is decided according to the combination of ttypn1 and ttypn0 of the dchcn register. for setting bits dmas2 to dmas0, refer to (6) start factor settings (n = 0 to 5). this register can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff38eh 76543210 dmas 0 0 0 0 0 dmas2 dmas1 dmas0
chapter 13 dma functions user ? s manual u15109ej3v0ud 476 (5) dma channel control registers 0 to 5 (dchc0 to dchc5) these registers are used to control the dma transfer operation mode for dma channel n. refer to (6) start factor settings for the setting of the ttypn1 and ttypn0 bits. these registers can be read/written in 8- or 1-bit units. after reset: 00h r/w address: dchc0 fffff186h dchc3 fffff1b6h dchc1 fffff196h dchc4 fffff1c6h dchc2 fffff1a6h dchc5 fffff1d6h <7> 6 <5> 4 3 <2> <1> <0> dchcn tcn 0 ddadn ttypn1 ttypn0 tdirn dsn enn (n = 0 to 5) tcn dma transfer completed/not completed note 1 0 not completed 1 completed ddadn internal ram address count direction control 0 increment 1 address is fixed tdirn transfer direction control between peripheral i/o and internal ram note 2 0 from internal ram to peripheral i/o 1 from peripheral i/o to internal ram dsn control of transfer data size for dma transfer note 2 0 8-bit transfer 1 16-bit transfer enn control of dma transfer enable/disable status note 3 0 disabled 1 enabled (reset to 0 after dma transfer is completed) notes 1. tcn (n = 0 to 5) is set (1) when a specified number of transfers are complete, and is cleared (0) when a write instruction is executed. 2. make sure that the transfer format conforms to the peripheral i/o register specifications (access- enabled data size, read/write, etc.) for the dma peripheral i/o address register (dioan). 3. after the specified number of transfers is complete, this bit is cleared to 0.
chapter 13 dma functions user ? s manual u15109ej3v0ud 477 477 (6) start factor settings the dma start factor is set using bits 2 to 0 (dmas2 to dmas0) of the dma start factor expansion register (dmas) in combination with bits 4 and 3 (ttypn1, ttypn0) of dma channel control registers 0 to 5 (dchc0 to dchc5)(n = 0 to 5). table 13-2 shows the dma start factor settings. cautions 1. if the interrupt that is the dma start factor is not masked, interrupt servicing is performed each time dma starts. to prevent interrupt servicing from being performed, mask the interrupt. 2. if an interrupt source is generated asynchronously to the internal system clock, do not set the interrupt source as a multiple dma start trigger (for example, when the serial interface is operated on the external clock input). if set, the priority order of dma may be reversed.
chapter 13 dma functions user ? s manual u15109ej3v0ud 478 table 13-2. start factor settings channel n dmas2 dmas1 dmas0 ttypn1 ttypn0 dma transfer start factor setting 0 0 intcsi0/intiic0 01intcsi5 10intad 0xxx 1 1 inttm00 0 0 0 intcsi0/intiic0 1 0 0 intcsi1/intsr0 0 1 intst0 10intp0 1xx x 11intsr3 0 0 0 intcsi2/intiic1 1 0 0 intcsi3/intsr1 01intp6 1 0 intie1 (setting prohibited for other than v850/sc2) 2x x x 11intad 0 0 0 intcsi6 1 0 0 intcsi3/intsr1 0 1 intst2 1 0 intie1 (setting prohibited for other than v850/sc2) 3 x xx 1 1 inttm70 0 0 intst1 0 1 intcsi4/intsr0 10intcsi6 4xxx 11intsr2 0 0 intst3 0 1 intcsi4/intsr0 1 0 intcsi2/intiic1 5xxx 1 1 inttm6/intp9 remarks 1. dmas2 to dmas0: bits 2 to 0 of the dma start factor expansion register (dmas) 2. ttypn1, ttypn0: bits 4 and 3 of dma channel control register n (dchcn) 3. x: don ? t care
chapter 13 dma functions user ? s manual u15109ej3v0ud 479 479 13.5 operation when a dma transfer request is generated during cpu processing, dma transfer is started after the current cpu processing has finished. regardless of the transfer direction, 4 cpu clocks (f cpu ) are required for one dma transfer. the 4 cpu clocks are divided as follows. ? internal ram access: 1 clock ? peripheral i/o access: 3 clocks after one dma transfer (8/16 bits) ends, control always shifts to the cpu processing. a dma transfer operation timing chart is shown below. figure 13-3. dma transfer operation timing ram ram peripheral i/o peripheral i/o f cpu intdman occurs when a dbcn register borrow occurs dma transfer processing signal dma transfer acknowledge signal processing format access destination for transfer from internal ram to peripheral i/o access destination for transfer from peripheral i/o to internal ram cpu processing dma transfer processing cpu processing remark n = 0 to 5 if two or more dma transfer requests are generated simultaneously, the dma transfer requests are executed in accordance with the following priority order: dma0 > dma1 > dma2 > dma3 > dma4 > dma5. while a higher priority dma transfer request is being executed, the lower priority dma transfer requests are held pending. after the higher priority dma transfer ends, control always shifts to the cpu processing once, and then the lower priority dma transfer is executed. the processing when the transfer requests dma0 to dma5 are generated simultaneously is shown below.
chapter 13 dma functions user ? s manual u15109ej3v0ud 480 figure 13-4. processing when transfer requests dma0 to dma5 are generated simultaneously cpu processing dam0 processing cpu processing dam1 processing cpu processing dam2 processing cpu processing dam3 processing cpu processing dam4 processing cpu processing cpu processing dam5 processing transfer requests dma0 to dma5 are generated simultaneously dma operation stops only in the idle/stop mode. in the halt mode, dma operation continues. dma also operates during the bus hold period and after access to the external memory. 13.6 cautions when using the dma function, if all the following conditions are met during the ei state (interrupt enable state), two interrupts occur when only one interrupt would occur normally. [occurrence conditions] (i) a bit manipulation instruction (set1, clr1, not1, tst1) was executed to the interrupt request flag (xxifn) of the interrupt control register (xxicn). (ii) an interrupt was processed by hardware at the same register as the register used in (i). remark xx: identifying name of peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 ) for example, when using the dma function, if an unmasked intcsi0 interrupt occurs during bit manipulation of the interrupt request flag (csif0) of the csic0 register by the clr1 instruction, intcsi0 interrupt servicing occurs twice. under such conditions, because the interrupt request flag (xxif) is not cleared (0) by hardware when the interrupt servicing is acknowledged, the interrupt servicing is executed again after reti instruction execution (interrupt servicing restoration). therefore, use the dma function under either of the following conditions. [use conditions] (i) when bit manipulation is executed for the interrupt control register (xxicn), the di instruction must be executed before the manipulation and the ei instruction must be executed after the manipulation. (ii) the interrupt request flag (xxifn) must be cleared (0) at the start of the interrupt routine. caution when the dma function is not used, execution of (i) or (ii) is not necessary. remark xx: identifying name of peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 )
chapter 13 dma functions user ? s manual u15109ej3v0ud 481 481 figure 13-5. when interrupt servicing occurs twice during dma operation (1/2) (a) normal interrupt servicing reti ei interrupt request main routine interrupt servicing routine interrupt request flag (xxifn) is cleared (0). (b) interrupt servicing when interrupt servicing occurs twice ei reti reti interrupt request flag (xxifn) is cleared (0). main routine interrupt servicing routine interrupt request flag (xxifn) is not cleared and remains 1. bit manipulation instruction to xxifn interrupt request since the interrupt request flag (xxifn) remains 1, the interrupt is serviced again. remark xx: identifying name of peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 )
chapter 13 dma functions user ? s manual u15109ej3v0ud 482 figure 13-5. when interrupt servicing occurs twice during dma operation (2/2) (c) countermeasure (use condition (i)) ei di ei reti the interrupt is serviced in the ei state (interrupt enable state) (the interrupt is not serviced immediately after bit manipulation instruction execution). main routine interrupt servicing routine interrupt request flag (xxifn) is cleared (0). bit manipulation instruction to xxifn interrupt request (d) countermeasure (use condition (ii)) ei ei reti interrupt request main routine interrupt servicing routine interrupt request flag (xxifn) is not cleared (0) and remains 1. bit manipulation instruction to xxifn xxifn is cleared (0) at the start of the interrupt servicing routine remark xx: identifying name of peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 )
user?s manual u15109ej3v0ud 483 chapter 14 reset function 14.1 general there are three methods used to generate a reset signal. (1) external reset by reset signal input (2) internal reset by watchdog timer loop time detection (watchdog timer overflow) (3) internal reset by power-on-clear (poc) (1) external reset by reset signal input when low-level input occurs at the reset pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. in addition, oscillation of the main clock is stopped during the reset period, although oscillation of the subclock continues. when the input at the reset pin changes from low level to high level, the reset status is canceled and the cpu resumes program execution after the oscillation stabilization time has elapsed (2 18 /f xx ). the contents of the various registers should be initialized within the program as necessary. an on-chip noise eliminator uses analog delay to prevent noise-related malfunction at the reset pin. (2) internal reset by watchdog timer loop time detection when the watchdog timer overflows, a system reset is performed and the various on-chip hardware devices are initialized. in addition, the main clock stops oscillation during the reset period, although the subclock continues oscillation. the reset by the watchdog timer is released immediately after reset and the cpu resumes program execution after the oscillation stabilization time has elapsed (2 18 /f xx ). (3) internal reset by power-on-clear (poc) when either of the following conditions is satisfied, a system reset is performed by power-on-clear. ? when the supply voltage is less than 3.5 v note at power application ? when the supply voltage is less than 2.2 v note in stop mode ? when the supply voltage becomes less than 3.5 v note (other than when stop mode is selected) when any one of the conditions above is satisfied, a system reset is performed and the various on-chip hardware devices are initialized. in addition, the main clock stops oscillation during the reset period, although the subclock continues oscillation. the power-on-clear reset is released after the power supply voltage reaches a certain voltage and the system starts program execution after the oscillation stabilization time has elapsed (2 18 /f xx ). whether the 3.5 v power-on-clear reset detection voltage is enabled or disabled is set using the pocc register (when initial power is supplied, it is enabled). note the voltage values are maximum values; a system reset is actually performed at lower voltage than each.
chapter 14 r eset f unction user?s manual u15109ej3v0ud 484 14.2 pin operations during the system reset period, almost all pins are set to high impedance (except for reset, x2, xt2, cpureg, v dd0 , v dd1 , adcv dd , adcgnd, portv dd0 to portv dd2 , portgnd0, portgnd1, gnd0, gnd1, gnd2, and v pp /ic). accordingly, if connected to an external memory device, be sure to attach a pull-up (or pull-down) resistor to each pin. if such a resistor is not attached, these pins will be set to high impedance, which could damage the data in memory devices. likewise, make sure the pins are handled so as to prevent such effects at the signal outputs by on- chip peripheral i/o functions and output ports. figure 14-1. system reset timing by reset signal input hi-z analog delay analog delay analog delay eliminated as noise internal system reset signal reset x1 reset is accepted reset is canceled 13.1 ms (@20 mhz operation) oscillation stabilization time figure 14-2. system reset timing by watchdog timer overflow hi-z hi-z normal operation normal operation (reset processing) reset period (oscillation stopped) oscillation stabilization time wait x1 internal reset signal port pin of i/o port watchdog timer overflow
chapter 14 r eset f unction user ? s manual u15109ej3v0ud 485 figure 14-3. system reset timing by power-on-clear (a) at power application reset period (oscillation stopped) oscillation stabilization time wait normal operation (reset processing) power-on-clear voltage (3.5 v) hi-z v dd 3.5 v x1 i/o port pin internal reset signal (b) in stop mode normal operation normal operation (reset processing) stop status (oscillation stopped) reset period (oscillation stopped) oscillation stabilization time wait power-on-clear voltage (2.2 v) stop instruction execution hi-z hi-z 3.5 v 2.2 v x1 i/o port pin internal reset signal v dd (c) in normal operating mode (including halt mode) normal operation normal operation (reset processing) reset period (oscillation stopped) oscillation stabilization time wait power-on-clear voltage (3.5 v) hi-z hi-z x1 i/o port pin internal reset signal v dd 3.5 v
chapter 14 r eset f unction user ? s manual u15109ej3v0ud 486 14.3 power-on-clear operation the v850/sc1, v850/sc2, and v850/sc3 include a power-on-clear circuit (poc), through which low-voltage detection and v dd0 pin voltage detection (4.2 0.3 v) can be performed by means of the poc status register (pocs). (1) poc status register (pocs) when a power-on-clear is generated, bit 0 of the pocs register is set to 1. in addition, if the voltage level at the v dd0 pin is less than 4.2 0.3 v, bit 1 (vm45) of the pocs register is set to 1, enabling detection of a voltage level of less than 4.2 0.3 v at the v dd0 pin. in the case of a reset generated by the reset pin, however, the pocm and vm45 bits retain their previous statuses. a low-voltage state can be detected by reading the pocs register following reset cancellation. the pocs register is read-only, using an 8-bit memory manipulation instruction. this register is reset when read. after reset: retained note r address: fffff07ah 76543210 pocs000000vm45pocm pocm detection of power-on-clear generation status 0 power-on-clear not generated 1 power-on-clear reset generated vm45 detection of v dd0 pin voltage level 0v dd0 pin voltage of less than 4.5 v not detected 1v dd0 pin voltage of less than 4.5 v detected note this value is 03h only after a power-on-clear reset; it is not initialized by a reset from the reset pin.
chapter 14 r eset f unction user ? s manual u15109ej3v0ud 487 (2) vm45 control register (vm45c) the detection status (detected/undetected) according to the vm45 bit of the pocs register can be output (monitored) at the vm45/p176 pin via control by the vm45c register. after reset: 00h r/w address: fffff07ch 76543210 pocs 0 0 0 0 0 0 vm45c1 vm45c0 vm45c1 vm45 (v dd0 4.5 v monitor) output enabled/disabled 0 vm45 output at vm45/p176 pin disabled (port function) 1 vm45 output at vm45/p176 pin enabled note vm45c0 vm45 (v dd0 4.5 v monitor) output selection 0 high-level output when vm45 detected 1 low-level output when vm45 detected note when using p176 as an alternate function pin, it is necessary to set the pm176 bit of the port 17 mode register (pm17) to 0 (output mode), or the p176 bit of port 17 (p17) to 0 (0 output). (3) poc control register (pocc) this register sets whether the 3.5 v power-on-clear reset detection voltage is enabled disabled. however, detection of less than 2.5 v in stop mode cannot be disabled. reset by power-on-clear when the initial power supply is applied is enabled, and reset by power-on-clear caused by a subsequent voltage drop is prohibited. reset applied through the reset pin clears pocc to 00h. the pocc register is set by an 8-bit memory manipulation instruction. after reset: 00h r/w address: fffff076h 76543210 pocc0000000pocc0 pocc0 3.5 v power-on-clear reset detection voltage enabled/disabled 0 enabled (3.5 v power-on-clear reset detection voltage is valid) 1 disabled (3.5 v power-on-clear reset detection voltage is invalid)
user?s manual u15109ej3v0ud 488 chapter 15 regulator 15.1 outline the v850/sc1, v850/sc2, and v850/sc3 incorporate a regulator to realize a 5 v single power supply, low power consumption, and to reduce noise. this regulator supplies a voltage obtained by stepping down the v dd power supply voltage to oscillation block and on-chip logic circuits (excluding the a/d converter and output buffers). the regulator output voltage is set to 3.3 v. refer to 2.4 i/o circuit types, i/o buffer power supply and connection of unused pins for the power supply corresponding to each pin. figure 15-1. regulator ( pd70f3089y) v dd1 -system i/o buffer portv dd0 -system i/o buffer 4.0 v to 5.5 v 4.0 v to 5.5 v 3.0 v to 5.5 v 3.0 v to 5.5 v 3.0 v to 5.5 v internal digital circuit (3.3 v) main/sub oscillator flash memory a/d converter 4.5 v to 5.5 v adcv dd v dd1 portv dd2 v pp portv dd1 regulator v dd0 cpureg 1 f (recommended) portv dd0 portv dd2 -system i/o buffer portv dd1 -system i/o buffer adcv dd -system input buffer remark : bidirectional level shifter 15.2 operation the regulator of the v850/sc1, v850/sc2, and v850/sc3 operates in every mode (stop, idle, halt). for stabilization of regulator outputs, connect a capacitor of about 1 f (recommended value) to the cpureg pin.
user?s manual u15109ej3v0ud 489 chapter 16 rom correction function 16.1 general the rom correction function provided in the v850/sc1, v850/sc2, and v850/sc3 is a function that replaces part of a program in the mask rom with a program in the internal ram. first, the instruction of the address where the program replacement should start (correction address) is replaced with the jmp r0 instruction and instructed to jump to 00000000h. the correction request register (corrq) is then checked. at this time, if the corrqn flag is set to 1, program control shifts to the internal ram after jumping to the internal rom area by an instruction such as a jump instruction (n = 0 to 3). instruction bugs found in the mask rom can be avoided, and program flow can be changed by using the rom correction function. up to four correction addresses can be specified. cautions 1. the rom correction function cannot be used for the data in the internal rom; it can only be used for instruction codes. if the rom correction is carried out on data, that data will replace the instruction code of the jmp r0 instruction. 2. rom correction for the instructions that access the corcn, corrq, or corad0 to corad3 registers is prohibited. figure 16-1. block diagram of rom correction rom (1 mb area) instruction address bus s q r correction address register n (coradn) comparator correction control register (corcnn bit) jmp r0 instruction generator instruction replacement instruction data bus correction request register (corrqn bit) 0 clear instruction remark n = 0 to 3
chapter 16 rom correction function 490 user?s manual u15109ej3v0ud 16.2 rom correction peripheral i/o registers 16.2.1 correction control register (corcn) corcn controls whether or not the instruction of the correction address is replaced with the jmp r0 instruction when the correction address set to the correction address register (coradn) matches the fetch address (n = 0 to 3). whether match detection by a comparator is enabled or disabled can be set for each channel. corcn can be set by an 8-bit or 1-bit memory manipulation instruction. after reset: 00h r/w address: fffff36ch 7654<3><2><1><0> corcn 0 0 0 0 coren3 coren2 coren1 coren0 corenn coradn register and fetch address match detection control (n = 0 to 3) 0 match detection disabled 1 match detection enabled remark n = 0 to 3 16.2.2 correction request register (corrq) corrq saves the channel in which rom correction occurred. the jmp r0 instruction makes the program jump to 00000000h after the correction address matches the fetch address. at this time, the program can judge the following cases by reading corrq. ? reset input: corrq = 00h ? rom correction generation: corrqn bit = 1 (n = 0 to 3) ? branch to 00000000h by user program: corrq = 00h after reset: 00h r/w address: fffff36eh 7654<3><2><1><0> corrq 0 0 0 0 corrq3 corrq2 corrq1 corrq0 corrqn note channel n rom correction request flag 0 no rom correction request occurred. 1 rom correction request occurred. note the corrqn bit is cleared by a ?write 0? instruction. remark n = 0 to 3
chapter 16 rom correction function user?s manual u15109ej3v0ud 491 16.2.3 correction address registers 0 to 3 (corad0 to corad3) coradn sets the start address of the instruction to be corrected (correction address) in the rom. up to four points of the program can be corrected at once since the v850/sc1, v850/sc2, and v850/sc3 have four correction address registers (coradn) (n = 0 to 3). set 00000000h to 0007fffeh since the v850/sc1, v850/sc2, and v850/sc3 incorporate a 512 kb rom. bits 0 and 18 to 31 should be fixed to 0. after reset: 00000000h r/w address: corad0: fffff370h corad2: fffff378h corad1: fffff374h corad3: fffff37ch 31 18 17 1 0 coradn fixed to 0 correction address 0 (n = 0 to 3)
chapter 16 rom correction function 492 user?s manual u15109ej3v0ud figure 16-2. rom correction operation and program flow start(reset vector) correction address? corenn = 1? corrqn = 0? yes no data for rom correction setting is loaded from an external memory into the internal ram to initialize rom correction function. if there is a correction code, it is loaded in the internal ram. microcontroller initialization clears corrqn flag. jmp channel n correct code address executes internal rom program executes correction program code jumps to internal rom yes no yes no corrqn flag set jmp r0 the address of the internal ram that stores the correction code of channel n should be preset before the instruction that makes the program jump to this address is stored in the internal rom. : executed by a program stored in the internal rom : executed by a program stored in the internal ram : executed by the rom correction function caution check the rom correction generation from a vector table with a high interrupt level when executing rom correction during a vector interrupt routine. if an interrupt conflicts with rom correction, processing is branched to an interrupt vector, where, if rom correction is being re- executed, corrqn is set (1) again and multiple corrqn flags are set (1). the channel for which rom correction is to be executed is determined by the interrupt level. remark n = 0 to 3
user?s manual u15109ej3v0ud 493 chapter 17 flash memory ( pd70f3089y) the pd70f3089y is the flash memory version of the v850/sc1, v850/sc2, and v850/sc3 and incorporates a 512 kb flash memory. caution there are differences in the amount of noise tolerance and noise radiation between flash memory versions and mask rom versions. when considering changing from a flash memory version to a mask rom version during the process from experimental manufacturing to mass production, make sure to sufficiently evaluate commercial samples (cs) (not engineering samples (es)) of the mask rom versions. in the instruction fetch to this flash memory, 4 bytes can be accessed by a single clock as well as the mask rom version. writing to flash memory can be performed with memory mounted on the target system (on board). a dedicated flash programmer is connected to the target system to perform writing. the following can be considered as the development environment and the applications using flash memory. ? software can be altered after the v850/sc1, v850/sc2, and v850/sc3 are solder-mounted on the target system. ? small scale production of various models is made easier by differentiating software. ? data adjustment in starting mass production is made easier. 17.1 features ? 4-byte/1-clock access (in instruction fetch access) ? all area batch erase/area unit erase ? communication via serial interface with the dedicated flash programmer ? erase/write voltage: v pp = 7.8 v ? on-board programming ? flash memory programming by self rewriting in area (128 kb) units is possible 17.1.1 erasing unit this product has the following two erasure units. (a) all area batch erase the area of xx000000h to xx07ffffh can be erased at the same time. the erasure time is 8.0 s. (b) area erase erasure can be performed in area units (there are four 128 kb unit areas). the erasure time is 2.0 s for each area. area 0: the area of xx000000h to xx01ffffh (128 kb) is erased area 1: the area of xx020000h to xx03ffffh (128 kb) is erased area 2: the area of xx040000h to xx05ffffh (128 kb) is erased area 3: the area of xx060000h to xx07ffffh (128 kb) is erased
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 494 17.1.2 write/read time the write/read time is shown below. write time: 50 s/byte read time: 50 ns (cycle time) 17.2 writing with flash programmer writing can be performed either on-board or off-board with the dedicated flash programmer. (1) on-board programming the contents of the flash memory is rewritten after the v850/sc1, v850/sc2, and v850/sc3 are mounted on the target system. mount connectors, etc., on the target system to connect the dedicated flash programmer. (2) off-board programming writing to a flash memory is performed by the dedicated program adapter (fa series), etc., before mounting the v850/sc1, v850/sc2, and v850/sc3 on the target system. remark the fa series is a product of naito densei machida mfg. co., ltd.
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 495 figure 17-1. example of wiring of adapter for flash programming (fa-144gj-uen) pd70f3089y so sck si x1 /reset v pp reserve/hs x2 vdd gnd gnd vdd gnd vdd vdd gnd 128 143 5 1 22 131 144 102 75 74 73 92 37 72 38 41 40 42 43 48 1 f 44 39 60 connect to gnd. connect to vdd. note note the pd70f3089y cannot be supplied with the clock from the clk pin of the flash programmer (pg- fp3). supply the clock by creating an oscillator on the flash writing adapter (broken-line portion). an example of the oscillator is shown below. example x1 x2
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 496 remarks 1. handle the pins not described above in accordance with the recommended connection of unused pins (refer to 2.4 pin i/o circuit types, i/o buffer power supply and connection of unused pins ). when connecting via a resistor, use of a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is for a 144-pin plastic lqfp package. 3. this diagram shows the wiring when using csi supporting handshake. table 17-1. table for wiring of adapter for pd70f3089y flash programming (fa-144gj-uen) flash programmer (pg-fp3) when using csi0 + hs when using csi0 when using uart0 pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal p11/so0 43 p11/so0 43 p14/so4/txd0 47 so/txd output transmit signal p10/si0/sda0 42 p10/si0/sda0 42 p13/si4/rxd0 46 sck output transfer clock p12/sck0/scl0 44 p12/sck0/scl0 44 unnecessary unnecessary clk note ? unused unnecessary unnecessary unnecessary unnecessary unnecessary unnecessary /reset output reset signal reset 40 reset 40 reset 40 vpp output writing voltage mode/v pp 41 mode/v pp 41 mode/v pp 41 hs input handshake signal of csi0 + hs communication p15/sck4/asck0 48 unnecessary unnecessary unnecessary unnecessary v dd0 39 v dd0 39 v dd0 39 v dd1 128 v dd1 128 v dd1 128 portv dd0 22 portv dd0 22 portv dd0 22 portv dd1 60 portv dd1 60 portv dd1 60 vdd ? vdd voltage generation/power supply monitoring portv dd2 102 portv dd2 102 portv dd2 102 gnd0 37 gnd0 37 gnd0 37 gnd1 131 gnd1 131 gnd1 131 gnd2 72 gnd2 72 gnd2 72 portgnd0 5 portgnd0 5 portgnd0 5 portgnd1 92 portgnd1 92 portgnd1 92 gnd ? ground p00/nmi 75 p00/nmi 75 p00/nmi 75 note the pd70f3089y cannot be supplied with the clock from the clk pin of the flash programmer (pg- fp3). supply the clock by creating an oscillator on the flash writing adapter (fa-144gj-uen). for an example of the oscillator, refer to figure 17-1 example of wiring of adapter for flash programming (fa-144gj-uen) .
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 497 17.3 programming environment the following shows the environment required for writing programs to the flash memory of the v850/sc1, v850/sc2, and v850/sc3. figure 17-2. environment required for writing programs to flash memory host machine rs-232c dedicated flash programmer v850/sc1, v850/sc2, v850/sc3 v pp v pp v dd v dd0 , v dd1 , portv dd0 to portv dd2 gnd0 to gnd2, portgnd0, portgnd1 gnd reset uart/csi a host machine is required for controlling the dedicated flash programmer. uart0 or csi0 is used for the interface between the dedicated flash programmer and the v850/sc1, v850/sc2, and v850/sc3 to perform writing, erasing, etc. a dedicated program adapter (fa series) is required for off-board writing. 17.4 communication mode communication between the dedicated flash programmer and the v850/sc1, v850/sc2, and v850/sc3 is serial communication performed using uart0 or csi0 of the v850/sc1, v850/sc2, and v850/sc3. (1) uart0 transfer rate: 4800 to 76800 bps figure 17-3. communication with dedicated flash programmer (uart0) dedicated flash programmer v850/sc1, v850/sc2, v850/sc3 v pp v dd0, v dd1 , portv dd0 to portv dd2 gnd0 to gnd2, portgnd0, portgnd1 reset txd0 rxd0 v pp v dd gnd reset rxd txd
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 498 (2) csi0 serial clock: up to 1 mhz (msb first) figure 17-4. communication with dedicated flash programmer (csi0) v pp v dd0 , v dd1 , portv dd0 to portv dd2 gnd0 to gnd2, portgnd0, portgnd1 reset so0 si0 sck0 v pp v dd gnd reset si so sck dedicated flash programmer v850/sc1, v850/sc2, v850/sc3 (3) csi0 + + + + hs serial clock: up to 1 mhz (msb first) figure 17-5. communication with dedicated flash programmer (csi0 + + + + hs) v pp v dd0 , v dd1 , portv dd0 to portv dd2 gnd0 to gnd2, portgnd0, portgnd1 reset so0 si0 sck0 p15 v pp v dd gnd reset si so sck hs dedicated flash programmer v850/sc1, v850/sc2, v850/sc3 the dedicated flash programmer outputs the transfer clock, and the v850/sc1, v850/sc2, and v850/sc3 operate as a slave. when the pg-fp3 is used as the dedicated flash programmer, it generates the following signals to the v850/sc1, v850/sc2, and v850/sc3. for the details, refer to the pg-fp3 user?s manual .
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 499 table 17-2. signal generation of dedicated flash programmer (pg-fp3) pg-fp3 v850/scx connection signal name i/o pin function pin name csi0 uart0 csi0 + hs v pp output writing voltage v pp v dd i/o v dd voltage generation/ voltage monitoring v dd0 , v dd1 , portv dd0 to portv dd2 gnd ? ground gnd0 to gnd2, portgnd0, portgnd1 clk note ? unused x1 reset output reset signal reset si/rxd input receive signal so0/txd0 so/txd output transmit signal si0/rxd0 sck output transfer clock sck0 hs input handshake signal of csi0 + hs p15 note the pd70f3089y cannot be supplied with the clock from the clk pin of the flash programmer (pg- fp3). supply the clock by creating an oscillator on the flash writing adapter (fa-144gj-uen). for an example of the oscillator, refer to figure 17-1 example of wiring of adapter for flash programming (fa-144gj-uen) . remarks 1. : always connected : does not need to be connected 2. v850/scx: v850/sc1, v850/sc2, v850/sc3
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 500 17.5 pin connection when performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. also, install a function on-board to switch from the normal operating mode to the flash memory programming mode. when switched to the flash memory programming mode, all the pins not used for the flash memory programming become the same status as that immediately after reset. therefore, all the ports become output high-impedance status, so that pin handling is required when the external device does not acknowledge the output high-impedance status. 17.5.1 v pp pin in the normal operating mode, 0 v is input to v pp pin. in the flash memory programming mode, a 7.8 v writing voltage is supplied to v pp pin. the following shows an example of the connection of the v pp pin. figure 17-6. v pp pin connection example v pp dedicated flash programmer connection pin pull-down resistor ( r vpp ) v850/sc1, v850/sc2, v850/sc3
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 501 17.5.2 serial interface pin the following shows the pins used by each serial interface. table 17-3. pins used by serial interfaces serial interface pins used csi0 so0, si0, sck0 csi0 + hs so0, si0, sck0, p15 uart0 txd0, rxd0 when connecting a dedicated flash programmer to a serial interface pin that is connected to other devices on- board, care should be taken to avoid the conflict of signals and the malfunction of other devices, etc. (1) conflict of signals when connecting a dedicated flash programmer (output) to a serial interface pin (input) that is connected to another device (output), conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. figure 17-7. conflict of signals (serial interface input pin) v850/sc1, v850/sc2, v850/sc3 other device output pin conflict of signals input pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs. therefore, isolate the signals on the other device side. dedicated flash programmer connection pins
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 502 (2) malfunction of other device when connecting a dedicated flash programmer (output or input) to a serial interface pin (input or output) that is connected to another device (input), the signal output to the other device may cause the device to malfunction. to avoid this, isolate the connection to the other device or set so that the input signal to the other device is ignored. figure 17-8. malfunction of other device v850/sc1, v850/sc2, v850/sc3 pin in the flash memory programming mode, if the signal the v850/sc1, v850/sc2, and v850/sc3 outputs affects the other device, isolate the signal on the other device side. other device input pin dedicated flash programmer connection pin v850/sc1, v850/sc2, v850/sc3 pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. other device input pin dedicated flash programmer connection pin
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 503 17.5.3 reset pin when connecting the reset signals of the dedicated flash programmer to the reset pin that is connected to the reset signal generator on-board, conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, programming operations will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 17-9. conflict of signals (reset pin) reset v850/sc1, v850/sc2, v850/sc3 reset signal generator output pin conflict of signals in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. dedicated flash programmer connection pin 17.5.4 port pins (including nmi) when the flash memory programming mode is set, all the port pins except the pins that communicate with the dedicated flash programmer become output high-impedance status. if problems such as disabling output high- impedance status should occur to the external devices connected to the port, connect them to v dd0 , v dd1 , portv dd0 to portv dd2 , adcv dd , gnd0 to gnd2, portgnd0, portgnd1, or adcgnd via resistors. 17.5.5 other signal pins connect x1, x2, xt1, and xt2 in the same status as that in the normal operating mode. 17.5.6 power supply supply the power supply as follows: v dd0 = portv dd1 supply the power (v dd1 , portv dd0 , portv dd2 , adcv dd , adcgnd, gnd0 to gnd2, portgnd0, and portgnd1) the same as when in normal operating mode.
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 504 17.6 programming method 17.6.1 flash memory control the following shows the procedure for manipulating the flash memory. figure 17-10. procedure for manipulating flash memory supplies reset pulse switch to flash memory programming mode select communication mode manipulate flash memory end? no yes end start 17.6.2 flash memory programming mode when rewriting the contents of flash memory using the dedicated flash programmer, set the v850/sc1, v850/sc2, and v850/sc3 in the flash memory programming mode. when switching modes, set the v pp pin before canceling reset. when performing on-board writing, switch modes using a jumper, etc. figure 17-11. flash memory programming mode reset flash memory programming mode 7.8 v v pp 3 v 0 v 12 ? n v pp operation mode 0 v normal operation mode 7.8 v flash memory programming mode
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 505 17.6.3 selection of communication mode in the v850/sc1, v850/sc2, and v850/sc3, the communication mode is selected by inputting pulses (16 pulses max.) to v pp pin after switching to the flash memory programming mode. the v pp pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. table 17-4. list of communication modes v pp pulses communication mode remarks 0 csi0 v850/sc1, v850/sc2, and v850/sc3 perform slave operation, msb first 3csi0 + hs v850/sc1, v850/sc2, and v850/sc3 perform slave operation, msb first 8 uart0 communication rate: 9600 bps (at reset), lsb first other rfu setting prohibited caution when uart0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the v pp pulse. 17.6.4 communication command the v850/sc1, v850/sc2, and v850/sc3 communicate with the dedicated flash programmer by means of commands. the command sent from the dedicated flash programmer to the v850/sc1, v850/sc2, and v850/sc3 is called the ? command ? . the response signal sent from the v850/sc1, v850/sc2, and v850/sc3 to the dedicated flash programmer is called the ? response command ? . figure 17-12. communication command v850/sc1, v850/sc2, v850/sc3 command dedicated flash programmer response command
chapter 17 flash memory ( pd70f3089y) user ? s manual u15109ej3v0ud 506 the following shows the commands for flash memory control of the v850/sc1, v850/sc2, and v850/sc3. all of these commands are issued from the dedicated flash programmer, and the v850/sc1, v850/sc2, and v850/sc3 perform the various processings corresponding to the commands. table 17-5. flash memory control commands category command name function verify batch verify command compares the contents of the entire memory and the input data. batch erase command erases the contents of the entire memory. erase write back command writes back the contents which is overerased. blank check batch blank check command checks the erase state of the entire memory. high-speed write command writes data by the specification of the write address and the number of bytes to be written, and executes verify check. data write continuous write command writes data from the address following the high- speed write command executed immediately before, and executes verify check. status read out command acquires the status of operations. oscillating frequency setting command sets the oscillating frequency. erasure time setting command sets the erasing time of batch erase. write time setting command sets the writing time of data write. write back time setting command sets the write back time. baud rate setting command sets the baud rate when using uart. silicon signature command reads outs the silicon signature information. system setting and control reset command escapes from each state. the v850/sc1, v850/sc2, and v850/sc3 send back response commands to the commands issued from the dedicated flash programmer. the following shows the response commands the v850/sc1, v850/sc2, and v850/sc3 send out. table 17-6. response commands response command name function ack (acknowledge) acknowledges command/data, etc. nak (not acknowledge) acknowledges illegal command/data, etc.
user?s manual u15109ej3v0ud 507 chapter 18 iebus controller (v850/sc2) the iebus (inter equipment bus) is a small-scale digital data transfer system that transfers data between units. to implement the iebus with the v850/sc2, an external iebus driver and receiver are necessary because they are not provided. the internal iebus controller of the v850/sc2 is of negative logic. 18.1 iebus controller function 18.1.1 communication protocol of iebus the communication protocol of the iebus is as follows: (1) multi-task mode all the units connected to the iebus can transfer data to the other units. (2) broadcast communication function communication between one unit and plural units can be performed as follows: ? group-unit broadcast communication: broadcast communication to group units ? all-unit broadcast communication: broadcast communication to all units. (3) effective transfer rate the effective transfer rate is in mode 1 (the v850/sc2 does not support modes 0 and 2 of effective transfer rate). ? mode 1: approx. 17 kbps caution different modes must not be mixed on one iebus. (4) communication mode data transfer is executed in a half-duplex asynchronous communication mode. (5) access control: csma/cd (carrier sense multiple access with collision detection) the priority of the iebus is as follows: <1> broadcast communication takes precedence over individual communication (communication from one unit to another). <2> the lower master address takes precedence. (6) communication scale the communication scale of iebus is as follows: ? number of units: 50 max. ? cable length: 150 m max. (when twisted pair cable is used) caution the communication scale in an actual system differs depending on the characteristics of the cables, etc., constituting the iebus driver/receiver and iebus.
chapter 18 iebus controller (v850/sc2) 508 user?s manual u15109ej3v0ud 18.1.2 determination of bus mastership (arbitration) an operation to occupy the bus is performed when a unit connected to the iebus controls the other units. this operation is called arbitration. when two or more units simultaneously start transmission, arbitration grants one of the units the permission to occupy the bus. because only one unit is granted the bus mastership as a result of arbitration, the priority condition of the bus is predetermined as follows: caution the bus mastership is released if communication is aborted. (1) priority by communication type broadcast communication (communication from one unit to plural units) takes precedence over normal communication (communication from one unit to another). (2) priority by master address if the communication type is the same, communication with the lower master address takes precedence. a master address consists of 12 bits, with unit 000h having the highest priority and unit fffh having the lowest priority. 18.1.3 communication mode although the iebus has three communication modes each having a different transfer rate, the v850/sc2 supports only communication mode 1. the transfer rate and the maximum number of transfer bytes in one communication frame in communication mode 1 are as shown in table 18-1. table 18-1. transfer rate and maximum number of transfer bytes in communication mode 1 communication mode maximum number of transfer bytes (bytes/frame) effective transfer rate (kbps) note 1 32 approx. 17 note the effective transfer rate when the maximum number of transfer bytes is transmitted. select the communication mode (mode 1) for each unit connected to the iebus before starting communication. if the communication mode of the master unit and that of the mating unit (slave unit) are not the same, communication is not correctly executed. 18.1.4 communication address with the iebus, each unit is assigned a specific 12-bit address. this communication address consists of the following identification numbers: ? higher 4 bits: group number (number to identify the group to which each unit belongs) ? lower 8 bits: unit number (number to identify each unit in a group)
chapter 18 iebus controller (v850/sc2) user?s manual u15109ej3v0ud 509 18.1.5 broadcast communication normally, transmission or reception is performed between the master unit and its mating slave unit on a one-to-one basis. during broadcast communication, however, two or more slave units exist and the master unit executes transmission to these slave units. because plural slave units exist, the slave units do not return an acknowledge signal during communication. whether broadcast communication or normal communication is to be executed is selected by the broadcast bit (for this bit, refer to 18.1.6 (2) broadcast bit ). broadcast communication can be classified into the two types; group-unit broadcast communication and all-unit broadcast communication. group-unit broadcast communication and all-unit broadcast communication are identified by the value of the slave address (for the slave address, refer to 18.1.6 (4) slave address field ). (1) group-unit broadcast communication broadcast communication is performed to the units in a group identified by the group number indicated by the higher 4 bits of the communication address. (2) all-unit broadcast communication broadcast communication is performed to all the units, regardless of the value of the group number. 18.1.6 transfer format of iebus figure 18-1 shows the transfer signal format of the iebus. figure 18-1. iebus transfer signal format header master address field slave address field control field telegraph length field data field start bit broad- casting bit master address bit p frame format slave address bit pa control bit pa tele- graph length bit pa data bit pa data bit pa remarks 1. p: parity bit, a: ack/nack bit 2. the master station ignores the acknowledge bit during broadcast communication. (1) start bit the start bit is a signal that informs the other units of the start of data transfer. the unit that is to start data transfer outputs a high-level signal (start bit) from the ietx0 pin for a specific time, and then starts outputting the broadcast bit. if another unit has already output its start bit when one unit attempts to output the start bit, this unit does not output the start bit but waits for completion of output of the start bit by the other unit. when the output of the start bit by the other unit is complete, the unit starts outputting the broadcast bit in synchronization with the completion of the start bit output by the other unit. the units other than the one that has started communication detect this start bit, and enter the reception status.
chapter 18 iebus controller (v850/sc2) 510 user ? s manual u15109ej3v0ud (2) broadcast bit this bit indicates whether the master selects one slave (individual communication) or plural slaves (broadcast communication) as the other party of communication. when the broadcast bit is 0, it indicates broadcast communication; when it is 1, individual communication is indicated. broadcast communication is classified into two types: group-unit communication and all-unit communication. these communication types are identified by the value of the slave address (for the slave address, refer to 18.1.6 (4) slave address field ). because two or more slave units exist in the case of broadcast communication, the acknowledge bit in each field subsequent to the master address field is not returned. if two or more units start transmitting a communication frame at the same time, broadcast communication takes precedence over individual communication, and wins in arbitration. if one station occupies the bus as the master, the value set to the broadcast request bit (allrq) of the iebus control register (bcr) is output. (3) master address field the master address field is output by the master to inform a slave of the master ? s address. the configuration of the master address field is as shown in figure 18-2. if two or more units start transmitting the broadcast bit at the same time, the master address field makes a judgment of arbitration. the master address field compares the data it outputs with the data on the bus each time it has output one bit. if the master address output by the master address field is found to be different from the data on the bus as a result of comparison, it is assumed that the master has lost in arbitration. as a result, the master stops transmission and enters the reception status. because the iebus is configured of wired and, the unit having the minimum master address of the units participating in arbitration (arbitration masters) wins in arbitration. after a 12-bit master address has been output, only one unit remains in the transmission status as one master unit. next, this master unit outputs a parity bit, determines the master address of the other unit, and starts outputting a slave address field. if one unit occupies the bus as the master, the address set by the iebus unit address register (uar) is output. figure 18-2. master address field master address field master address (12 bits) msb lsb parity
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 511 (4) slave address field the master outputs the address of the unit with which it is to communicate. figure 18-3 shows the configuration of the slave address field. a parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake. next, the master unit detects an acknowledge signal from the slave unit to confirm that the slave unit exists on the bus. when the master has detected the acknowledge signal, it starts outputting the control field. during broadcast communication, however, the master does not detect the acknowledge bit but starts outputting the control field. the slave unit outputs the acknowledge signal if its slave address matches and if the slave detects that the parities of both the master address and slave address are even. the slave unit judges that the master address or slave address has not been correctly received and does not output the acknowledge signal if the parities are odd. at this time, the master unit is in the standby (monitor) status, and communication ends. during broadcast communication, the slave address is used to identify group-unit broadcast or all-unit broadcast, as follows: if slave address is fffh: all-unit broadcast communication if slave address is other than fffh: group-unit broadcast communication remark the group no. during group-unit broadcast communication is the value of the higher 4 bits of the slave address. if one unit occupies the bus as the master, the address set by the slave address register (sar) is output. figure 18-3. slave address field slave address field unit no. msb lsb ack parity slave address (12 bits) group no.
chapter 18 iebus controller (v850/sc2) 512 user ? s manual u15109ej3v0ud (5) control field the master outputs the operation it requires the slave to perform, by using this field. the configuration of the control field is as shown in figure 18-4. if the parity following the control bit is even and if the slave unit can execute the function required by the master unit, the slave unit outputs an acknowledge signal and starts outputting the telegraph length field. if the slave unit cannot execute the function required by the master unit even if the parity is even, or if the parity is odd, the slave unit does not output the acknowledge signal, and returns to the standby (monitor) status. the master unit starts outputting the telegraph length field after confirming the acknowledge signal. if the master cannot confirm the acknowledge signal, the master unit enters the standby status, and communication ends. during broadcast communication, however, the master unit does not confirm the acknowledge signal, and starts outputting the telegraph length field. table 18-2 shows the contents of the control bits. table 18-2. contents of control bits bit 3 note 1 bit 2 bit 1 bit 0 function 0 0 0 0 reads slave status 0 0 0 1 undefined 0 0 1 0 undefined 0 0 1 1 reads data and locks note 2 0 1 0 0 reads lock address (lower 8 bits) note 3 0 1 0 1 reads lock address (higher 4 bits) note 3 0 1 1 0 reads slave status and unlocks note 2 0 1 1 1 reads data 1 0 0 0 undefined 1 0 0 1 undefined 1 0 1 0 writes command and locks note 2 1 0 1 1 writes data and locks note 2 1 1 0 0 undefined 1 1 0 1 undefined 1110writes command 1111writes data notes 1. the telegraph length bit of the telegraph length field and data transfer direction of the data field change as follows depending on the value of bit 3 (msb). if bit 3 is ? 1 ? : transfer from master unit to slave unit if bit 3 is ? 0 ? : transfer from slave unit to master unit 2. this is a control bit that specifies locking or unlocking (refer to 18.1.7 (4) locking and unlocking ). 3. the lock address is transferred in 1-byte (8-bit) units and is configured as follows: msb lower 8 bits undefined higher 4 bits control bit: 4h control bit: 5h lsb
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 513 if the control bit received from the master unit is not as shown in table 18-3, the unit locked by the master unit reject accepting the control bit, and does not output the acknowledge bit. table 18-3. control field for locked slave unit bit 3 note 1 bit 2 bit 1 bit 0 function 0 0 0 0 reads slave status 0 1 0 0 reads lock address (lower 8 bits) 0 0 0 1 reads lock address (higher 4 bits) moreover, units for which lock is not set by the master unit reject acknowledgement and do not output an acknowledge bit when the control data shown in table 18-4 is acknowledged. table 18-4. control field for unlocked slave unit bit 3 bit 2 bit 1 bit 0 function 0 1 0 0 lock address read (lower 8 bits) 0 1 0 1 lock address read (higher 4 bits) if one unit occupies the bus as the master, the value set to the iebus control register (cdr) is output. figure 18-4. control field msb lsb ack parity control bit (4 bits) control field
chapter 18 iebus controller (v850/sc2) 514 user ? s manual u15109ej3v0ud table 18-5. control field acknowledge signal output conditions (a) when received control data is ah, bh, eh, fh received control data communication type (all trans) individual communication = 1 broadcast communication = 1 communication tar g et (slvrq) slave specification = 1 no specification = 0 lock status (lock) locked = 1 unlocked = 0 master unit judgment (match with par) lock request unit = 1 other = 0 slave transmission enable (enslvtx) slave reception enable (enslvrx) ah bh eh fh 0 1 0 don ? t care don ? t care 1 11 other than above (b) when received control data is 0h, 3h, 4h, 5h, 6h, 7h received control data communication type (all trans) individual communication = 1 broadcast communication = 1 communication tar g et (slvrq) slave specification = 1 no specification = 0 lock status (lock) locked = 1 unlocked = 0 master unit judgment (match with par) lock request unit = 1 other = 0 slave transmission enable (enslvtx) slave reception enable (enslvrx) 0h 3h 4h 5h 6h 7h 0 1 0 don ? t care 0 don ? t care 1 1 don ? t care 1 1 other than above caution if the received control data is other than as shown in table 18-5, it becomes unconditionally (ack is not returned). remarks 1. : ack returned : ack not returned 2. enslvtx: bit 4 of iebus unit control register (bcr) enslvrx: bit 3 of iebus unit control register (bcr) slvrq: bit 6 of iebus unit status register (usr) lock: bit 2 of iebus unit status register (usr) par: iebus partner address register
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 515 (6) telegraph length field this field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. the configuration of the telegraph length field is as shown in figure 18-5. table 18-6 shows the relationship between the telegraph length bit and the number of transmit data. figure 18-5. telegraph length field msb lsb telegraph length field telegraph length bit (8 bits) parity ack table 18-6. contents of telegraph length bit telegraph length bit (hex) number of transmit data bytes 01h 02h | ffh 00h 1 byte 2 bytes | 255 bytes 256 bytes the operation of the telegraph length field differs depending on whether the master transmits (when control bit 3 is 1) or receives (when control bit 3 is 0) data. (a) when master transmits data the telegraph length bit and parity bit are output by the master unit. when the slave unit detects that the parity is even, it outputs the acknowledge signal, and starts outputting the data field. during broadcast communication, however, the slave unit does not output the acknowledge signal. if the parity is odd, the slave unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby (monitor) status. at this time, the master unit also returns to the standby status, and communication ends. (b) when master receives data the telegraph length bit and parity bit are output by the slave unit and the synchronization signals of bits are output by the master unit. if the master unit detects that the parity bit is even, it outputs the acknowledge signal. if the parity bit is odd, the master unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby status. at this time, the slave unit also returns to the standby status, and communication ends.
chapter 18 iebus controller (v850/sc2) 516 user ? s manual u15109ej3v0ud (7) data field this is data output by the transmission side. the master unit transmits or receives data to or from a slave unit by using the data field. the configuration of the data field is as shown below. figure 18-6. data field data field (number specified by telegraph length field) msb lsb one data ack parity control bit (8 bits) ack parity following the data bit, the parity bit and acknowledge bit are respectively output by the master unit and slave unit. use broadcast communication only for when the master unit transmits data. at this time, the acknowledge bit is ignored. the operation differs as follows depending on whether the master transmits or receives data. (a) when master transmits data when the master units writes data to a slave unit, the master unit transmits the data bit and parity bit to the slave unit. if the parity is even and the receive data is not stored in the iebus data register (dr) when the slave unit has received the data bit and parity bit, the slave unit outputs an acknowledge signal. if the parity is odd or if the receive data is stored in the iebus data register (dr), the slave unit rejects receiving the data, and does not output the acknowledge signal. if the slave unit does not output the acknowledge signal, the master unit transmits the same data again. this operation continues until the master detects the acknowledge signal from the slave unit, or the data exceeds the maximum number of transmit bytes. if the data has continuation and the maximum number of transmit bytes is not exceeded when the parity is even and when the slave unit outputs the acknowledge signal, the master unit transmits the next data. during broadcast communication, the slave unit does not output the acknowledge signal, and the master unit transfers 1 byte of data at a time. if the parity is odd or the dr register is storing receive data after the slave unit has received the data bit and parity bit during broadcast communication, the slave unit judges that reception has not been performed correctly, and stops reception. (b) when master receives data when the master unit reads data from a slave unit, the master unit outputs a sync signal corresponding to all the read bits. the slave unit outputs the contents of the data and parity bits to the bus in response to the sync signal from the master unit. the master unit reads the data and parity bits output by the slave unit, and checks the parity. if the parity is odd, or if the dr register is storing a receive data, the master unit rejects accepting the data, and does not output the acknowledge signal. if the maximum number of transmit bytes is within the value that can be transmitted in one communication frame, the master unit repeats reading the same data. if the parity is even and the dr register is not storing a receive data, the master unit accepts the data and returns the acknowledge signal. if the maximum number of transmit bytes is within the value that can be transmitted in one frame, the master unit reads the next data.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 517 caution do not operate a master reception in broadcast communication, because the slave unit cannot be defined and a data transfer cannot be performed correctly. (8) parity bit the parity bit is used to check to see if the transmit data has no error. the parity bit is appended to each data of the master address, slave address, control, telegraph length, and data bits. the parity is an even parity. if the number of bits in data that are ? 1 ? is odd, the parity bit is ? 1 ? . if the number of bits in the data that are ? 1 ? is even, the parity bit is ? 0 ? . (9) acknowledge bit during normal communication (communication from one unit to another), an acknowledge bit is appended to the following locations to check to see if the data has been correctly received. ? end of slave address field ? end of control field ? end of telegraph length field ? end of data field the definition of the acknowledge bit is as follows: ? 0: indicates that the transmit data is recognized (ack). ? 1: indicates that the transmit data is not recognized (nack). during broadcast communication, however, the content of the acknowledge bit is ignored. (a) last acknowledge bit of slave field the last acknowledge bit of the slave field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the master address bit or slave address bit is incorrect ? if a timing error (error in bit format) occurs ? if a slave unit does not exist (b) last acknowledge bit of control field the last acknowledge bit of the control field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the control bit is incorrect ? if control bit 3 is ? 1 ? (write operation) when the slave reception enable flag (enslvrx) is not set (1) (refer to 18.3.2 (1) iebus control register (bcr) ) ? if the control bit indicates reading of data (3h or 7h) when the slave transmission enable flag (enslvtx) is not set (1) (refer to 18.3.2 (1) iebus control register (bcr) ) ? if a unit other than that has set locking requests 3h, 6h, 7h, ah, bh, eh, or fh of the control bit when locking is set ? if the control bit indicates reading of lock addresses (4h, 5h) even when locking is not set ? if a timing error occurs ? if the control bit is undefined
chapter 18 iebus controller (v850/sc2) 518 user ? s manual u15109ej3v0ud cautions 1. even when the slave transmission enable flag (enslvtx) is not set (1), ack is always returned if slave status request control data is received. 2. even when slave reception enable flag (enslvrx) is not set (1), nack is always returned by the acknowledge bit in the control field if data/command writing control data is acknowledged. slave reception can be disabled (communication stopped) by enslvrx flag only in the case of independent communication. in the case of broadcast communication, communication is maintained and the data request interrupt (intie1) or iebus end interrupt (intie2) is generated. (c) last acknowledge bit of telegraph length field the last acknowledge bit of the telegraph length field serves nack in any of the following cases, and transmission is stopped. ? if the parity of the telegraph length bit is incorrect ? if a timing error occurs (d) last acknowledge bit of data field the last acknowledge bit of the data field serves nack in any of the following cases, and transmission is stopped. ? if the parity of the data bit is incorrect note ? if a timing error occurs after the proceeding acknowledge bit has been transmitted ? if the receive data is stored in the iebus data register (dr) and no more data can be received note note in this case, when the communication executed is individual communication, if the maximum number of transmit bytes is within the value that can be transmitted in one frame, the transmission side executes transmission of that data field again. for broadcast communication, the transmission side does not execute transmission again, a communication error occurs on the reception side and reception stops. 18.1.7 transfer data (1) slave status the master unit can ascertain why the slave unit did not return the acknowledge bit (ack) by reading the slave status. the slave status is determined depending on the result of the last communication the slave unit has executed. all the slave units can supply information on the slave status. the configuration of the slave status is shown below.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 519 figure 18-7. bit configuration of slave status msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 note 1 meaning 0 transmit data is not written in iebus data register (dr) 1 transmit data is written in iebus data register (dr) bit 1 note 2 meaning 0 receive data is not stored in iebus data register (dr) 1 receive data is stored in iebus data register (dr) bit 2 meaning 0 unit is not locked 1 unit is locked bit 3 meaning 0 fixed to 0 bit 4 note 3 meaning 0 slave transmission is stopped 1 slave transmission is ready bit 5 meaning 0 fixed to 0 bit 7 bit 6 meaning 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 not used indicates the highest mode supported by unit note 4 . notes 1. after reset: bit 0 is set to 1. 2. the receive buffer size is 1 byte. 3. when the v850/sc2 serves as a slave unit, this bit corresponds to the status indicated by bit 4 (enslvtx) of the iebus control register (bcr). 4. when the v850/sc2 serves as a slave unit, bits 7 and 6 are both fixed to mode 1 (bits 7, 6 = 0, 1).
chapter 18 iebus controller (v850/sc2) 520 user ? s manual u15109ej3v0ud (2) lock address when the lock address is read (control bit: 4h or 5h), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. figure 18-8. configuration of lock address msb lower 8 bits undefined higher 4 bits control bit: 4h control bit: 5h lsb (3) data if the control bit indicates reading of data (3h or 7h), the data in the data buffer of the slave unit is read by the master unit. if the control bit indicates writing of data (bh or fh), the data received by the slave unit is processed according to the operation rule of that slave unit. (4) locking and unlocking the lock function is used when a message is transferred in two or more communication frames. the unit that is locked does not receive data from units other than the one that has locked the unit (does not receive broadcast communication). a unit is locked or unlocked as follows: (a) locking if the communication frame is completed without succeeding in transmission or reception of the data of the number of bytes specified by the telegraph length bit after the telegraph length field has been transmitted or received (ack = 0) by the control bit that specifies locking (3h, ah, or bh), the slave unit is locked by the master unit. at this time, the bit (bit 2) in the byte indicating the slave status is set to 1. (b) unlocking after transmitting or receiving data of the number of data bytes specified by the telegraph length bit in one communication frame by the control bit that has specified locking (3h, ah, or bh), or the control bit that has specified unlocking (6h), the slave unit is unlocked by the master unit. at this time, the bit related to locking (bit 2) in the byte indicating the slave status is reset to 0. locking or unlocking is not performed during broadcast communication. locking and unlocking conditions are shown below.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 521 (c) lock setting conditions broadcast communication individual communication control data communication end frame end communication end frame end 3h, 6h note cannot be locked lock set ah, bh cannot be locked cannot be locked cannot be locked lock set 0h, 4h, 5h, eh, fh cannot be locked cannot be locked cannot be locked cannot be locked (d) lock release conditions (while locked) broadcast communication from lock request unit individual communication from lock request unit control data communication end frame end communication end frame end 3h, 6h note unlocked remains locked ah, bh unlocked unlocked unlocked remains locked 0h, 4h, 5h, eh, fh remains locked remains locked remains locked remains locked note the frame end of control data 6h (slave status read/unlock) occurs when the parity in the data field is odd, and when the acknowledge signal from the iebus unit is repeated up to the maximum number of transfer bytes without being output. 18.1.8 bit format the format of the bits constituting the communication frame of the iebus is shown below. figure 18-9. bit format of iebus logic ? 1 ? logic ? 0 ? preparation period synchronization period data period stop period preparation period: first low-level (logic ? 1 ? ) period synchronization period: next high-level (logic ? 0 ? ) period data period: period indicating value of bit stop period: last low-level (logic ? 1 ? ) period the synchronization period and data period are almost equal to each other in length. the iebus synchronizes each bit. the specifications on the time of the entire bit and the time related to the period allocated to that bit differ depending on the type of the transmit bit, or whether the unit is the master unit or a slave unit. during communication, the master and slave units detect whether each period (preparation period, synchronization period, data period, and stop period) is output for the specified time. if not, the master and slave units regard it as a timing error, and immediately stop communication and return to the wait status.
chapter 18 iebus controller (v850/sc2) 522 user ? s manual u15109ej3v0ud 18.2 iebus controller configuration the block diagram of the iebus controller is shown below. figure 18-10. iebus controller block diagram bcr(8 ) uar ( 12 ) sar ( 12 ) par ( 12 ) cdr ( 8) dlr ( 8) dr ( 8 ) usr(8 ) isr ( 8 ) ssr(8 ) scr(8 ) ccr(8 ) 81212 8 8 8 8 12 8 8 8 888 888 88 8 nf ierx ietx mpx mpx 12-bit latch comparator conflict detection ack generation parity generation error detection tx/rx interrupt controller interrupt control block int request ? ? ? ? ? ? ? cpu interface block internal registers (handler, dma transfer) iebus interface block clk bit processing block field processing block internal bus r/w psr (8 bits) 8 5 8 12 12 12 internal bus 8 12 (1) hardware configuration and function the iebus mainly consists of the following six internal blocks. ? cpu interface block ? interrupt control block ? internal registers ? bit processing block ? field processing block ? iebus interface block
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 523 (a) cpu interface block this is a control block that interfaces between the cpu (v850/sc2) and the iebus. (b) interrupt control block this control block transfers interrupt request signals from the iebus to the cpu. (c) internal registers these registers set data to the control registers and fields that control the iebus (for the internal registers, refer to 18.3 internal registers of iebus controller ). (d) bit processing block this block generates and disassembles bit timing, and mainly consists of a bit sequence rom, 8-bit preset timer, and comparator. (e) field processing block this block generates each field in the communication frame, and mainly consists of a field sequence rom, 4-bit down counter, and comparator. (f) iebus interface block this is the interface block for an external driver/receiver, and mainly consists of a noise filter, shift register, conflict detector, parity detector, parity generator, and ack/nack generator.
chapter 18 iebus controller (v850/sc2) 524 user ? s manual u15109ej3v0ud 18.3 internal registers of iebus controller 18.3.1 internal register list table 18-7. internal registers of iebus controller bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff3e0h iebus control register bcr ? ? 00h fffff3e2h iebus unit address register uar ?? fffff3e4h iebus slave address register sar r/w ?? fffff3e6h iebus partner address register par r ?? 0000h fffff3e8h iebus control data register cdr ? ? fffff3eah iebus telegraph length register dlr ? ? 01h fffff3ech iebus data register dr r/w ? ? fffff3eeh iebus unit status register usr r ? ? fffff3f0h iebus interrupt status register isr r/w ? ? 00h fffff3f2h iebus slave status register ssr ? ? 41h fffff3f4h iebus communication success counter scr ? ? 01h fffff3f6h iebus transmit counter ccr r ? ? 20h fffff3f8h iebus clock select register ieclk r/w ? ? 00h
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 525 18.3.2 internal registers the internal registers incorporated in the iebus controller are described below. (1) iebus control register (bcr) after reset: 00h rw address: fffff3e0h <7> <6> <5> <4> <3> 2 1 0 bcr eniebus mstrq allrq enslvtx enslvrx 0 0 0 eniebus communication enable flag 0 iebus unit stopped 1 iebus unit active mstrq master request flag 0 iebus unit not requested as master 1 iebus unit requested as master allrq broadcast request flag 0 individual communication requested 1 broadcast communication requested enslvtx slave transmission enable flag 0 slave transmission disabled 1 slave transmission enabled enslvrx slave reception enable flag 0 slave reception disabled 1 slave reception enabled cautions 1. while the iebus is operating as the master, writing to the bcr register (including bit manipulation instructions) is disabled until either the end of that communication or frame, or until communication is stopped by the occurrence of an arbitration-loss communication error. master requests cannot therefore be multiplexed. however, if the iebus is specified as a slave while a master request is being held pending, the bcr can be written to at the end of communication to clear the communication end/frame end flag. this is also the case when communication has been forcibly stopped (eniebus flag = 0). 2. if a bit manipulation instruction for the bcr register conflicts with a hardware reset of the mstrq flag, the bcr register may not operate normally. the following countermeasures are recommended in this case. ? ? ? ? because the hardware reset is instigated in the acknowledgement period of the slave address field, be sure to observe caution 1 of (b) master request flag (mstrq) below. ? ? ? ? be sure to observe the caution above regarding writing to the bcr register.
chapter 18 iebus controller (v850/sc2) 526 user ? s manual u15109ej3v0ud (a) communication enable flag (eniebus)...bit 7 set: by software reset: by software caution make both of the following settings before setting the eniebus flag. ? ? ? ? set the interrupt enable (ei) status and enable interrupt servicing of intie2 (iebmk = 2). ? ? ? ? set the iebus unit address register (uar) (b) master request flag (mstrq)...bit 6 set: by software reset: by hardware, at the end of the arbitration period. because the reset signal is generated in the ack period of the slave address field, if a mstrq flag setting instruction is sent in this period, it will be invalid. cautions 1. the master request should be resent by software following a loss in arbitration. when resending the master request in this case, set (1) the mstrq flag after securing the required wait period. this flag is unable to be set (1) before the end of this wait period. intie2 interrupt signal start interrupt generation forcible reset period wait period (61.7 s max) mstrq flag reset signal 2. when a master request has been sent and bus mastership acquired, do not set the mstrq, enslvtx, or enslvrx flag until the end of communication (i.e. the isr register?s communication end/frame end flag is set (1)) as setting these flags disables interrupt request generation. however, these flags can be set if communication has been aborted. (c) broadcast request flag (allrq)...bit 5 set: by software reset: by software caution when requesting broadcast communication, always set the allrq flag, then the mstrq flag.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 527 (d) slave transmission enable flag (enslvtx)...bit 4 set: by software reset: by software cautions 1. clear the enslvtx flag before setting the mstrq flag when making a master request. if a slave transmission request is sent in slave mode while the enslvtx flag is unset, nack in the control field will be returned. moreover, when returning to an enabled state from a disabled state, transmission becomes valid from the next frame. 2. if the controller receives control data for data/control writing (3h, 7h) while the enslvtx flag is unset, nack will be returned via the acknowledge bit of the control field. 3. the status interrupt (intie2) will be generated and communication continued when the control data of a slave status request is returned, even if the enslvtx flag is in the reset status. (e) slave reception enable flag (enslvrx)...bit 3 set: by software reset: by software caution if the enslvrx flag is reset when the iebus is busy with other cpu processing, nack will be returned via the acknowledge bit of the control field, making it possible to disable slave reception. note that resetting this flag only disables individual communication, not broadcast communication. in individual communication, however, when the received slave address matches the local address, the start interrupt is generated. if cpu processing has priority (neither reception nor transmission occurs), be sure to stop the iebus unit by resetting the eniebus flag. note also that when returning to an enabled state from a disabled state, transmission becomes valid from the next frame.
chapter 18 iebus controller (v850/sc2) 528 user ? s manual u15109ej3v0ud (2) iebus unit address register (uar) this register sets the unit address of the iebus unit. this register must always be set before starting communication. sets the unit address (12 bits) to bits 11 to 0. 15 0 14 0 13 0 12 0 uar 11 10 9 8 7 6 5 4 3 2 1 0 address fffff3e2h after reset 0000h r/w r/w (3) iebus slave address register (sar) during master request, the value of this register is reflected in the value of the transmit data in the slave address field. this register must always be set before starting communication. sets the slave address (12 bits) to bits 11 to 0. 15 0 14 0 13 0 12 0 sar 11 10 9 8 7 6 5 4 3 2 1 0 address fffff3e4h after reset 0000h r/w r/w (4) iebus partner address register (par) (a) when slave unit the value of the receive data in the master address field (address of the master unit) is written to this register. if a request ? 4h ? to read the lock address (lower 8 bits) is received from the master, the cpu must read the value of this register, and write it to the lower 8 bits iebus data register (dr). if a request ? 5h ? to read the lock address (higher 4 bits) is received from the master, the cpu must read the value of this register and write the data of the higher 4 bits to dr. sets the partner address (12 bits) to bits 11 to 0. 15 0 14 0 13 0 12 0 par 11 10 9 8 7 6 5 4 3 2 1 0 address fffff3e6h after reset 0000h r/w r (5) iebus control data register (cdr) (a) when master unit the data of the lower 4 bits is reflected in the data transmitted in the control field. during master request, this register must be set in advance before starting communication. (b) when slave unit the data received in the control field is written to the lower 4 bits. when the status transmission flag (status) of the iebus interrupt status register (isr) is set, an interrupt (intie2) is issued, and each processing should be performed by software, according to the value of the lower 4 bits of cdr.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 529 after reset: 01h r/w address: fffff3e8h 76543210 cdr0000modselcl2selcl1selcl0 mod selcl2 selcl1 selcl0 function 0 0 0 0 reads slave status 0 0 0 1 undefined 0 0 1 0 undefined 0 0 1 1 reads data and locks 0 1 0 0 reads lock address (lower 8 bits) 0 1 0 1 reads lock address (lower 4 bits) 0 1 1 0 reads slave status and unlocks 0 1 1 1 reads data 1 0 0 0 undefined 1 0 0 1 undefined 1 0 1 0 writes command and locks 1 0 1 1 writes data and locks 1 1 0 0 undefined 1 1 0 1 undefined 1 1 1 0 writes command 1 1 1 1 writes data cautions 1. because the slave unit must judge whether the received data is a ?command? or ?data?, it must read the value of this register after completing communication. 2. if the master unit sets an undefined value, nack is returned from the slave unit, and communication is aborted. during broadcast communication, however, the master unit continues communication without recognizing ack/nack; therefore, make sure not to set an undefined value to this register during broadcast communication. 3. in the case of defeat in a bus conflict and a slave status request is received from the unit that won, the telegraph length register (dlr) is fixed to ?01h?. therefore, when a re-request of the master follows, the appointed telegraph length must be set to dlr.
chapter 18 iebus controller (v850/sc2) 530 user ? s manual u15109ej3v0ud (c) slave status return operation when the iebus receives a request to transfer from master to slave status (control data: 0h, 6h) or a lock address request (4h, 5h), whether ack in the control field is returned or not depends on the status of the iebus unit. (1) if 0h or 6h control data was received in the unlocked state ack returned (2) if 4h or 5h control data was received in the unlocked state ack not returned (3) if 0h, 4h, 5h or 6h control data was received in the locked state from the unit that sent the lock request ack returned (4) if 0h, 4h, or 5h control data was received in the locked state from other than the unit that sent the lock request ack returned (5) if 6h control data was received in the locked state from other than the unit that sent the lock request ack not returned in all of the above cases, the acknowledgement of a slave status or lock request will cause the statusf flag (bit 4 of the isr register) to be set and the status interrupt (intie2) to be generated. the generation timing is at the end of the control field parity bit (at the start of the ack bit). however, if ack is not returned, a nack error is generated after the ack bit, and communication is terminated. figure 18-11. interrupt generation timing (for (1), (3), and (4)) intie2 flag set by reception of 0h, 4h, 5h, 6h iebus sequence flag reset by cpu processing control field telegraph length field statusf flag internal nack flag control bits (4 bits) parity bit (1 bit) ack bit (1 bit) telegraph length bits (8 bits)
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 531 figure 18-12. interrupt generation timing (for (2) and (5)) intie2 flag set by reception of 0h, 4h, 5h, 6h iebus sequence flag reset by cpu processing error generated by detection of nack control field statusf flag internal nack flag control bits (4 bits) parity bit (1 bit) ack bit (1 bit) terminated by communication error because in (4) and (5) the communication was from other than the unit that sent the lock request while the iebus was in the locked state, the start or communication complete interrupt (intie2) is not generated, even if the iebus unit is the communication target. the statusf flag (bit 4 of the isr register) is set and the status interrupt (intie2) generated, however, if a slave status or lock address request is acknowledged. note that even if the same control data is received while the iebus is in the locked state, the interrupt generation timing for intie2 differs depending on whether the master unit (3) or another unit (4) is requesting the locked state. figure 18-13. timing of intie2 interrupt generation in locked state (for (4) and (5)) intie2 iebus sequence status interrupt start master address (12 + p) broadcast slave address (12 + p + a) control (4 + p + a) telegraph length note (8 + p + a) data note (8 + p + a) note for (5), there is no ack return and therefore no transition to telegraph length and data. remark p: parity bit, a: ack/nack bit figure 18-14. timing of intie2 interrupt generation in locked state (for (3)) intie2 iebus sequence status interrupt start master address (12 + p) broadcast slave address (12 + p + a) control (4 + p + a) telegraph length (8 + p + a) communication complete interrupt data (8 + p + a) start interrupt remark p: parity bit, a: ack/nack bit
chapter 18 iebus controller (v850/sc2) 532 user ? s manual u15109ej3v0ud (6) iebus telegraph length register (dlr) (a) when transmission unit ... master transmission, slave transmission the data of this register is reflected in the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data. this register must be set in advance before transmission. (b) when reception unit ... master reception, slave reception the receive data in the telegraph length field transmitted from the transmission unit is written to this register. remark the iebus telegraph length register is divided into a writing side and a reading side, making it impossible for the written data to be readout as is. only data received via iebus communication can be readout. after reset: 01h r/w address: fffff3eah 76543210 dlr bit 76543210 setting value number of communication data bytes 00000001 01h 1 byte 00000010 02h 2 bytes :::::::: : : 00100000 20h 32 bytes :::::::: : : 11111111 ffh 255 bytes 00000000 00h 256 bytes cautions 1. if the master issues a request ? 0h, 4h, 5h, or 6h ? to transmit a slave status and lock address (higher 4 bits, lower 8 bits), the contents of this register are set to ? 01h ? by hardware; therefore, the cpu does not have to set this register. 2. in the case of defeat in a bus conflict and a slave status request is received from the unit that won, dlr is fixed to ? 01h ? . therefore, if a re-request of the master follows, the appointed telegraph length must be set to dlr.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 533 (7) iebus data register (dr) the iebus data register (dr) sets the communication data (8 bits) to bits 7 to 0. remark the iebus telegraph length register is divided into a writing side and a reading side, making it impossible for the written data to be readout as is. only data received via iebus communication can be readout. (a) when transmission unit the data (1 byte) written to the iebus data register (dr) is stored in the iebus interface shift register of the iebus. it is then output from the most significant bit, and an interrupt (intie1) is issued to the cpu each time 1 byte has been transmitted. in individual communication, however, if nack is received after 1-byte data transmission, the transfer from dr to the shift register is not performed and the same data is transmitted again. in this case, intie1 is not generated. intie1 is issued when the iebus interface shift register stores the iebus data register value. however, when the last byte and 32nd byte (the last byte of 1 communication frame) is stored in the shift register, intie1 is not issued. (b) when reception unit one byte of the data received by the shift register of the iebus interface block is stored to this register. each time 1 byte has been correctly received, an interrupt (intie1) is issued. when transmit/receive data is transferred to and from the iebus data register, using dma can reduce the cpu processing load. after reset: 00h r/w address: fffff3ech 76543210 dr cautions 1. if the next data is not in time while the transmission unit is set, an underrun occurs, and a communication error interrupt (intie2) occurs to stop transmission. 2. when the iebus is a receiving unit, if the reading of the data is too late for the next data reception timing, the unit will enter the overrun state. at this time, during individual communication reception, nack will be returned at the acknowledge bit of the data field, and the master unit will be requested to retransmit the data. if an overrun error occurs during broadcast communication, the communication error interrupt (intie2) is generated.
chapter 18 iebus controller (v850/sc2) 534 user ? s manual u15109ej3v0ud (8) iebus unit status register (usr) after reset: 00h r address: fffff3eeh 7 <6> <5> <4> <3> <2> 1 0 usr 0 slvrq arbit alltrns ack lock 0 0 slvrq slave request flag 0 no request from master to slave 1 request from master to slave arbit arbitration result flag 0 arbitration win 1 arbitration loss alltrns broadcast communication flag 0 individual communication status 1 broadcast communication status ack ack transmission flag 0 nack transmitted 1 ack transmitted lock lock status flag 0 unit unlocked 1 unit locked (a) slave request flag (slvrq)...bit 6 this flag indicates whether there was a slave request from the master. set: when the iebus unit has been sent a slave request (during individual communication reception, when the received slave address and local uar match; during broadcast reception, when the higher 4 bits of the received slave address match, or the received slave address is fffh), the flag is set by hardware at the start of the acknowledge period for the slave address field. reset: when the iebus unit is not sent a slave request, the flag is reset by hardware. the timing is the same as for set. however, if immediately following normal reception of a communication (slvrq bit is set), the iebus unit is sent a slave request and a parity error occurs in the slave address field for that communication, the flag is not reset.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 535 (b) contention result flag (arbit)...bit 5 this flag shows the contention result. set: this flag is set if, following a master request, the data output by the iebus unit during the arbitration period and the bus line data do not match. reset: this flag is reset at the start bit timing. cautions 1. the reset timing of the contention result flag (arbit) differs depending on whether the iebus unit outputs or does not output a start bit. ? ? ? ? start bit output: reset at output start timing ? ? ? ? start bit not output: reset at start bit detection timing (approx. 160 s from output) 2. if, after a master request has been made, the start bit of another unit is output first and the iebus unit does not output a start bit, the flag is reset at the start bit detection timing. (c) broadcast communication flag (alltrns)...bit 4 a flag indicating whether the unit is performing broadcast communication. the contents of the flag are updated in the broadcast field of each frame. except for initialization (reset) by system reset, the set/reset conditions vary depending on the receive data of the broadcast field bit. set: when ? broadcast ? is received by the broadcast field reset: when ? individual ? is received by the broadcast field, or upon the input of a system reset. caution the broadcast flag is updated regardless of whether the iebus is the communication target or not. figure 18-15. example of broadcast communication flag operation broadcast communication flag reset set not reset by start bit iebus sequence start m11 broadcast m10 m11 narrowcast m10 start (d) ack transmission flag (ack)...bit 3 a flag that indicates whether ack has been transmitted in the ack period of the ack field when the iebus is a receiving unit. the contents of the flag are updated in the ack period of each frame. however, if the internal circuit is initialized by the occurrence of a parity error, etc., the contents are not updated in the ack period of that field.
chapter 18 iebus controller (v850/sc2) 536 user ? s manual u15109ej3v0ud (e) lock status flag (lock)...bit 2 a flag that indicates whether the unit is locked. set: when the communication end flag goes low level and the frame end flag goes high level after receipt of a lock specification (3h, 6h, ah, bh) in the control field. reset: when the communication enable flag is cleared. when the communication end flag is set after receipt of a lock release (3h, 6h, ah, bh) in the control field. caution lock specification/release is not possible in broadcast communication. also, in locked status, individual communication from a unit other than the unit which has requested to be locked is not acknowledged. however, even communication from a unit which has not requested to be locked can be acknowledged as long as the communication is a slave status request. (9) iebus interrupt status register (isr) this register indicates the status when the iebus issues an interrupt. the isr is read to generate an interrupt, after which the specified interrupt servicing is carried out. reset the isr register after reading it. until it is reset, the intie2 interrupt signal is not generated (nor held pending). to reset the isr register, reset each flag, satisfying the reset conditions in table 18-8. table 18-8. reset conditions of flags in isr register flag name reset condition processing example ieerr, startf, statusf byte write operation of isr register. any value can be written. isr = 00h, etc. endtrns, endfram set mstrq, enslvtx, or enslvrx flag. bcr register = 88h or enslvtx = 1, etc. caution even if 0 is written to the endtrns or endfram flag by accessing the isr register, these flags are not reset. reset them as described above. remark mstrq: bit 6 of the iebus control register (bcr) enslvtx: bit 4 of the iebus control register (bcr) enslvrx: bit 3 of the iebus control register (bcr)
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 537 after reset: 00h r/w address: fffff3f0h 7 <6> <5> <4> <3> <2> 1 0 isr 0 ieerr startf statusf endtrns endfram 00 ieerr communication error flag (during communication) 0 no communication error 1 communication error startf start interrupt flag 0 start interrupt not generated 1 start interrupt generated statusf status transmission flag (slave) 0 no slave status/lock address (higher 4 bits, lower 8 bits) transmission request 1 slave status/lock address (higher 4 bits, lower 8 bits) transmission request endtrns communication end flag 0 communication does not end after the number of bytes set in the telegraph length field have been transferred 1 communication ends after the number of bytes set in the telegraph length field have been transferred endfram frame end flag 0 the frame (transfer of the maximum number of bytes (32 bytes) prescribed by mode 1) does not end 1 the frame (transfer of the maximum number of bytes (32 bytes) prescribed by mode 1) ends caution each of ieerr, startf, statusf, endtrns, and endfram are generation triggers for the interrupt request signal (intie2) (see figure 18-16). because of this, if any one of these interrupt triggers have been set, no new interrupt will be generated by a subsequent trigger. clear the source flag of the generated interrupt before the next interrupt generation timing using an interrupt servicing program.
chapter 18 iebus controller (v850/sc2) 538 user ? s manual u15109ej3v0ud (a) communication error flag (ieerr)...bit 6 a flag that indicates the detection of an error during communication. set: when a timing error, parity error (except in the data field), nack reception (except for data field), underrun error, or overrun error (which occurs in broadcast communication) occurs. reset: by software (b) start interrupt flag (startf)...bit 5 a flag that indicates whether the interrupt was in the ack period of the slave address field. set: in the slave address field, upon a master request. when the iebus is a slave unit, this flag is set upon a request from the master (only if it was a slave request in the locked state from the unit requesting a lock). reset: by software (c) status transmission flag (statusf)...bit 4 a flag indicating that the transmission status is either the master to slave status, or the lock address (higher 4 bits, lower 8 bits), when the iebus is a slave unit. set: when 0h, 4h, 5h, or 6h is received in the control field from the master when the iebus is a slave unit. reset: by software (d) communication end flag (endtrans)...bit 3 a flag that indicates whether communication ends after the number of bytes set in the telegraph length field have been transferred. set: when the value of the scr counter is 0. reset: when the mstrq, enslvtx, or enslvrx flag is set. (e) frame end flag (endfram)...bit 2 a flag that indicates whether communication ends after the maximum number of bytes (32 bytes) prescribed by mode 1 have been transferred. set: when the value of the ccr counter is 0. reset: when the mstrq, enslvtx, or enslvrx flag is set.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 539 (f) communication error triggers ? ? ? ? timing error occurrence conditions: occurs if the high/low level width of the communication bit has shifted from the prescribed value. remark: the respective prescribed values are set in the bit processing block and monitored by the internal 8-bit timer. an interrupt is generated when a timing error occurs. ? ? ? ? parity error occurrence conditions: occurs if the generated parity and the received parity in each field do not match when the iebus is a receiving unit. remark: during individual communication, an interrupt is generated if a parity error occurs in a field other than the data field. during broadcast communication, an interrupt is generated even if a parity error occurs in the data field. restriction: if there is a slave request that has lost in arbitration to a broadcast request, no interrupt is generated, even if a parity error occurs. ? ? ? ? nack reception error occurrence conditions: occurs when nack is received in the ack period in the slave address, control, or telegraph length field, during individual communication regardless of master or slave unit. a nack reception error only occurs in individual communication. ack and nack are not discriminated in broadcast communication. remark: an interrupt is generated if nack is received in a field other than the data field. ? ? ? ? underrun occurrence conditions: occurs during data transmission if there was insufficient time to write the next transmit data to the iebus data register (dr) before ack reception. remark: an interrupt is generated if an underrun occurs. ? ? ? ? overrun occurrence conditions: when the iebus is a receiving unit, the iebus data register (dr) is read by dma or software after the generation of the interrupt (intie1) that causes data to be stored in 1-byte units in this register. an overrun error occurs if this reading processing is late and its timing becomes that of the next data reception. remark: in individual communication reception, an acknowledgement is not returned in the ack period of this data, resulting in the retransmission of the data by the transmit unit. consequently, the iebus transfer counter (ccr) is decremented, whereas the iebus communication success counter (scr) is not. in broadcast communication reception, reception is stopped by the occurrence of a communication error (intie2), at which time the dr register is not updated. the statrx flag (bit 1 of the ssr register) also remains set (1) without generating intie1. the overrun state is released at the timing of the next data reception following the reading of dr.
chapter 18 iebus controller (v850/sc2) 540 user ? s manual u15109ej3v0ud (g) overrun error - supplementary details (i) when the frame ends in the overrun state during individual communication reception if the dr register is not read after entering the overrun state and the retransmitted data reaches the maximum number of bytes (32 bytes), the frame end interrupt (intie2) is generated. the overrun state is maintained until the dr register is read after the end of the frame. (ii) if the next reception is started in the case of (i) above, or if the next reception is started without the dr register being read after the final data has been received, regardless of whether the communication is broadcast or individual even if communication to the iebus unit starts in the overrun state, the cause of the overrun, nack, is not returned in the ack period of the slave address, control, or telegraph length field (the dr register is not updated). if the next communication is not to the iebus unit, the dr register is not updated until it is read. because the iebus unit is not a communication target, the data interrupt (intie1) and communication error interrupt (intie2) are not generated. (iii) if the next transmission occurs in the overrun state the data to be transmitted next in the overrun state can be no more than 2 bytes long. because the data request interrupt (intie1) is not generated, the transmit data cannot be set, resulting in an underrun error. therefore, transmit after releasing the overrun status. (iv) overrun state release the overrun state can only be released by reading the dr register or by a system reset. therefore, be sure to read dr during execution of a communication error interrupt servicing program, etc.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 541 (10) iebus slave status register (ssr) this register indicates the communication status of the slave unit. after receiving a slave status transmission request from the master, the cpu reads this register, and writes a slave status to the iebus data register (dr) to transmit the slave status. at this time, because the telegraph length is automatically set to ? 01h ? , setting of the iebus telegraph length register (dlr) is not required (because it is preset by hardware). bits 6 and 7 indicate the highest mode supported by the unit, and are fixed to ? 01 ? (mode 1). after reset: 41h r address: fffff3f2h 7 6 5 <4> 3 <2> <1> <0> ssr 0 1 0 statslv 0 statlock statrx stattx statslv slave transmission status flag 0 slave transmission stops 1 slave transmission enabled statlock lock status flag 0 unlock status 1 lock status statrx dr receive status 0 receiving data not stored in dr 1 receiving data stored in dr stattx dr transmit status 0 transmission data not stored in dr 1 transmission data stored in dr (a) slave transmission status flag (statslv)...bit 4 this flag reflects the contents of the slave transmission enable flag. (b) lock status flag (statlock)...bit 2 this flag reflects the contents of the locked flag. (c) dr reception status (statrx)...bit 1 this flag indicates the dr reception state. (d) dr transmission status (stattx)...bit 0 this flag indicates the dr transmission state.
chapter 18 iebus controller (v850/sc2) 542 user ? s manual u15109ej3v0ud (11) iebus success count register (scr) the iebus success count register (scr) indicates the number of remaining communication bytes. this register reads the count value of the counter that decrements the value set by the telegraph length register by ack in the data field. when the count value has reached ? 00h ? , the communication end flag (endtrns) of the iebus interrupt status register (isr) is set. after reset: 01h r address: fffff3f4h 76543210 scr bit 76543210 setting value remaining number of communication data bytes 00000001 01h 1 byte 00000010 02h 2 bytes :::::::: : : 00100000 20h 32 bytes :::::::: : : 11111111 ffh 255 bytes 00000000 00h 0 bytes ( end of communication) or 256 bytes note note the bit length of the actual hard counter consists of 9 bits. when ? 00h ? is read, it cannot be judged whether the remaining number of communication data bytes is 0 (end of communication) or 256. therefore, either the communication end flag is used, or if ? 00h ? is read when the first interrupt occurs at the beginning of communication, the remaining number of communication data bytes is judged to be 256.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 543 (12) iebus communication count register (ccr) the iebus communication count register (ccr) indicates the number of remaining bytes in the communication byte number specified in the communication mode. bits 7 to 0 of the iebus communication count register (ccr) indicate the number of transfer bytes. this register reads the count value of the counter that is preset to the maximum number of transmitted bytes (32 bytes) per frame specified in mode 1 and is decremented during the ack period of the data field regardless of ack/nack. while scr (iebus success count register) is decremented upon normal communication (ack), ccr is decremented upon each 1-byte communication regardless of ack/nack. when the count value has reached ? 00h ? , the frame end flag (endfram) of the iebus interrupt status register (isr) is set. the maximum number of transfer bytes of the preset value of mode 1 per frame is 20h (32 bytes). after reset: 20h r address: fffff3f6h 76543210 ccr (13) iebus clock select register (ieclk) this register selects the clock of the iebus. the main clock frequencies that can be used are shown below. main clock frequencies other than the following cannot be used. ? 6.0 mhz/6.291 mhz ? 12.0 mhz/12.582 mhz ? 18.0 mhz/18.874 mhz after reset: 00h r/w address: fffff3f8h 76543210 ieclk000000iecs1iecs0 iecs1 iecs0 iebus clock selection 00@ f xx = 6.0 mhz or f xx = 6.291 mhz 01@ f xx = 12.0 mhz or f xx = 12.582 mhz 1 @ f xx = 18.0 mhz or f xx = 18.874 mhz remark : don ? t care
chapter 18 iebus controller (v850/sc2) 544 user ? s manual u15109ej3v0ud 18.4 interrupt operations of iebus controller 18.4.1 interrupt control block interrupt request signal <1> communication error (ieerr) <2> start interrupt (startf) <3> status communication (statusf) <4> end of communication (endtrns) <5> end of frame (endfram) <6> transmit data write request (stattx) <7> receive data read request (statrx) 1 through 5 of the above interrupt requests are assigned to the interrupt status register (isr). for details, refer to table 18-9 interrupt source list . the configuration of the interrupt control block is illustrated below. figure 18-16. configuration of interrupt control block ieerr startf statusf endtrns endfram stattx statrx iebus macro interrupt control block v850/sc2 cpu intie1 intie2 cautions 1. or output of statrx and stattx is treated as a dma transfer start signal (intie1). 2. or output of ieerr, startf, statusf, endtrns, and endfram is treated as a vector interrupt request signal (intie2) for the v850/sc2.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 545 18.4.2 interrupt source list the interrupt request signals of the internal iebus controller in the v850/sc2 can be classified into vector interrupts and dma transfer interrupts. these interrupt request signals can be specified through software manipulation. the interrupt sources are listed below. table 18-9. interrupt source list condition of generation interrupt source unit field cpu processing after generation of interrupt remark timing error master/slave all fields other than data (individual) parity error reception all fields (broadcast) nack reception reception (transmission) other than data (individual) underrun error transmission data communication error overrun error reception data (broadcast) undo communication processing communication error is or output of timing error, parity error, nack reception, underrun error, and overrun error master slave/address slave request judgment contention judgment (if loses, remaster processing) communication preparation processing interrupt always occurs if loss in contention occurs for master request start interrupt slave slave/address slave request judgment communication preparation processing generated only for slave request status transmission slave control refer to transmission processing example such as slave status. interrupt occurs regardless of slave transmission enable flag. also occurs upon nack return in the control field. transmission data dma transfer end processing end of communication reception data dma transfer end processing receive data processing set if scr is cleared to 0 transmission data retransmission preparation processing end of frame reception data re-reception preparation processing set if ccr is cleared to 0 transmit data write transmission data transmission data read note set after transfer transmission data to internal shift register. interrupt does not occur at the last data transfer. receive data read reception data receive data read note set after normal data reception note when not using dma transfer or software manipulation
chapter 18 iebus controller (v850/sc2) 546 user ? s manual u15109ej3v0ud 18.4.3 communication error cause processing list the occurrence conditions for communication errors (timing errors, nack reception errors, overrun errors, underrun errors, and parity errors), the internal iebus controller error processing contents, and an example of processing by software are described below. table 18-10. communication error cause processing list (1/2) timing error local node status during reception during transmission occurrence condition when bit timing is off occurrence condition occurrence location other than data field data field other than data field data field hardware processing ? reception stopped ? intie2 generated ? to start bit wait status remark communication between other nodes does not stop. ? transmission stopped ? intie2 generated ? to start bit wait status during broadcast communication software processing ? error processing (resend request, etc.) ? error processing (resend request, etc.) hardware processing ? reception stopped ? intie2 generated ? nack returned ? to start bit wait status ? transmission stopped ? intie2 generated ? to start bit wait status during individual communication software processing ? error processing (resend request, etc.) ? error processing (resend request, etc.) nack reception error local node status during reception during transmission occurrence condition local node nack transmission nack reception occurrence condition occurrence location other than data field data field other than data field data field nack reception for 32nd byte data hardware processing ????? during broadcast communication software processing ????? hardware processing ? reception stopped ? intie2 generated ? to start bit wait status ? intie2 not generated ? receive data resent by other node ? transmission stopped ? intie2 generated ? to start bit wait status ? intie2 not generated ? resend processing ? intie2 generated note ? to start bit wait status during individual communication software processing ? error processing (resend request, etc.) ?? error processing (resend request, etc.) ?? error processing (resend request, etc.) note both the ieerr and endfram bits of the isr register are set (1). to reset these bits, follow the conditions specified in table 18-8.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 547 table 18-10. communication error cause processing list (2/2) overrun error underrun error local node status during reception during transmission occurrence condition dr read is not executed by next data reception timing dr write is not executed by next data transmission timing occurrence condition occurrence location other than data field data field other than data field data field hardware processing ? ? reception stopped ? intie2 generated ? to start bit wait status remarks 1. communication between other nodes does not stop. 2. data reception is not possible until the overrun status is cancelled. ? ? transmission stopped ? intie2 generated ? to start bit wait status during broadcast communication software processing ? ? execute dr read to cancel overrun status ? error processing (resend request, etc.) ? ? error processing (resend request, etc.) hardware processing ? ? intie2 not generated ? nack returned ? data reset from other node remark data reception is not possible until the overrun status is cancelled. ? ? transmission stopped ? intie2 generated ? to start bit wait status during individual communication software processing ?? execute dr read to cancel overrun status ? error processing (resend request, etc.) ?? error processing (resend request, etc.) parity error local node status during reception during transmission occurrence condition receive data and receive parity don ? t match ? occurrence condition occurrence location other than data field data field other than data field data field hardware processing ? reception stopped ? intie2 generated ? to start bit wait status remark communication between other nodes does not stop. ?? during broadcast communication software processing ? error processing (resend request, etc.) ?? hardware processing ? reception stopped ? intie2 generated ? to start bit wait status ? reception not stopped ? intie2 not generated ? nack returned ? receive data sent from other nodes ?? during individual communication software processing ? error processing (resend request, etc.) ???
chapter 18 iebus controller (v850/sc2) 548 user ? s manual u15109ej3v0ud 18.5 interrupt generation timing and main cpu processing 18.5.1 master transmission initial preparation processing: sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. communication start processing: sets the bus control register (enables communication, master request, and slave reception). figure 18-17. master transmission start broad- casting m address p s address p a control p a telegraph length p a data 1 pa data 1 data 2 p a data n ? 1pa data n p a <1> <2> approx. 624 s (mode 1) approx. 390 s (mode 1) <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request slave reception processing (see 18.5.1 (1) slave reception processing ) judgment of contention result remaster request processing <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame re-communication processing (see 18.5.1 (3) re-communication processing ) remarks 1. : interrupt (intie1) occurrence (see 18.5.1 (2) interrupt (intie1) occurrence ) the transmit data of the second byte and those that follow are written to the iebus data register (dr) by dma transfer. at this time, the data transfer direction is ram (memory) sfr (peripheral) 2. : an interrupt (intie1) does not occur. 3. n = final number of data bytes
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 549 (1) slave reception processing if a slave reception request is confirmed during vector interrupt servicing, the data transfer direction of the macro service must change from ram (memory) ? sfr (peripheral) to sfr (peripheral) ? ram (memory) by the time the first data is received. the maximum pending period of this data transfer direction changing processing is about 1040 s in communication mode 1. (2) interrupt (intie1) occurrence if nack is received from the slave in the data field, an interrupt (intie1) is not issued to the cpu, but the same data is retransmitted by hardware. if the transmit data is not written within the period of writing the next data, a communication error interrupt occurs due to the occurrence of an underrun, and communication ends midway. (3) re-communication processing the vector interrupt servicing in <2> in figure 18-17 judges whether the data has been correctly transmitted within one frame. if the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remainder of the data must be transmitted.
chapter 18 iebus controller (v850/sc2) 550 user ? s manual u15109ej3v0ud 18.5.2 master reception before performing master reception, it is necessary to notify the slave unit of slave transmission. therefore, more than two communication frames are necessary for master reception. the slave unit prepares the transmit data, set (1) the slave transmission enable flag (enslvtx), and waits. initial preparation processing: sets a unit address, slave address, and control data. communication start processing: sets the bus control register (enables communication and master request). figure 18-18. master reception approx. 1014 s (mode 1) start broad- casting m address p s address p a control a p telegraph length a p data 1 approx. 390 s (mode 1) data 1 p a data 2 p a data n ? 1 p a data n p a <2> <1> <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request slave processing judgment of collision result remaster request processing <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 18.5.2 (2) frame end processing ) remarks 1. : interrupt (intie1) occurrence (see 18.5.2 (1) interrupt (intie1) occurrence ) the receive data stored in the iebus data register (dr) is read by dma transfer. at this time, the data transfer direction is sfr (peripheral) ram (memory). 2. n = final number of data bytes
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 551 (1) interrupt (intie1) occurrence if nack is transmitted (hardware processing) in the data field, an interrupt (intie1) is not issued to the cpu, but the same data is retransmitted from the slave. if the receive data is not read by the time the next data is received, the hardware automatically transmits nack. (2) frame end processing the vector interrupt servicing in <2> in figure 18-18 judges whether the data has been correctly received within one frame. if the data has not been correctly received (if the number of data to be received in one frame could not be received), a request to retransmit the data must be made to the slave in the next communication frame.
chapter 18 iebus controller (v850/sc2) 552 user ? s manual u15109ej3v0ud 18.5.3 slave transmission initial preparation processing: sets a unit address, telegraph length, and the first byte of the transmit data. communication start processing: sets the bus control register (enables communication, slave transmission, and slave reception). figure 18-19. slave transmission start m address p s address p a control p a data 1 pa data 1 data 2 p a data n ? 1pa data n p a <1> <2> pa approx. 390 s (mode 1) approx. 624 s (mode 1) broad- casting telegraph length <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 18.5.3 (2) frame end processing ) remarks 1. : interrupt (intie1) occurrence (see 18.5.3 (1) interrupt (intie1) occurrence ). the transmit data of the second byte and those that follow are written to the iebus data register (dr) by dma transfer. at this time, the data transfer direction is ram (memory) sfr (peripheral). 2. : an interrupt (intie1) does not occur. 3. : interrupt (intie2) occurrence an interrupt occurs only when 0h, 4h, 5h, or 6h is received in the control field in the slave status (for the slave status response operation during the locked state, refer to 18.3.2 (5) iebus control data register (cdr) ). 4. n = final number of data bytes
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 553 (1) interrupt (intie1) occurrence if nack is received from the master in the data field, an interrupt (intie1) is not issued to the cpu, but the same data is retransmitted by hardware. if the transmit data is not written within the period of writing the next data, a communication error interrupt occurs due to the occurrence of an underrun, and communication ends abnormally. (2) frame end processing the vector interrupt processing in <2> in figure 18-19 judges whether the data has been correctly transmitted within one frame. if the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remainder of the data must be transmitted.
chapter 18 iebus controller (v850/sc2) 554 user ? s manual u15109ej3v0ud 18.5.4 slave reception initial preparation processing: sets a unit address. communication start processing: sets the bus control register (enables communication, disables slave transmission, and enables slave reception). figure 18-20. slave reception start m address p s address p a control p a data 1 pa data 1 data 2 p a data n ? 1pa data n p a <1> pa <2> approx. 390 s (mode 1) approx. 1014 s (mode 1) broad- casting telegraph length <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request slave processing <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 18.5.4 (2) frame end processing ). remarks 1. : interrupt (intie1) occurrence (see 18.5.4 (1) interrupt (intie1) occurrence ). the receive data stored in the iebus data register (dr) is read by dma transfer. at this time, the data transfer direction is sfr (peripheral) ram (memory). 2. n = final number of data bytes (1) interrupt (intie1) occurrence if nack is transmitted in the data field, an interrupt (intie1) is not issued to the cpu, but the same data is retransmitted from the master. if the receive data is not read in by the time the next data is received, nack is automatically transmitted. (2) frame end processing the vector interrupt processing in <2> in figure 18-20 judges whether the data has been correctly received within one frame.
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 555 18.5.5 interval of occurrence of interrupt for iebus control each control interrupt must occur at each point of communication and perform the necessary processing by the time the next interrupt occurs. therefore, the cpu must control the iebus control block, taking the shortest time of this interrupt into consideration. the locations at which the following interrupts may occur are indicated by in the field where it may occur. does not mean that the interrupt occurs at each of the points indicated by . if an error interrupt (timing error, parity error, or ack error) occurs, the iebus internal circuit is initialized. as a result, the following interrupt does not occur in that communication frame. (1) master transmission figure 18-21. master transmission (interval of interrupt occurrence) start bit t t1 t broad- casting master address t t2 p slave address t pa at t t3 control p a a t4 tat telegraph length p a data p a communication starts communication start interrupt pa data data a p data tt t4 end of communication end of frame u u t5 a remarks 1. t: timing error a: ack error u: underrun error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: at 6.29 mhz) item symbol min. unit communication starts ? timing error t1 approx. 93 s communication starts ? communication start interrupt t2 approx. 1282 s communication start interrupt ? timing error t3 approx. 15 s communication start interrupt ? end of communication t4 approx. 1012 s transmission data request interrupt interval t5 approx. 375 s
chapter 18 iebus controller (v850/sc2) 556 user ? s manual u15109ej3v0ud (2) master reception figure 18-22. master reception (interval of interrupt occurrence) start bit broad- casting telegraph length data master address slave address control pa pa pa pa pa p a p t1 t tt data data data tt t t t at t4 t4 t5 t2 a p t a t3 end of communication end of frame communication start communication start interrupt a remarks 1. t: timing error p: parity error a: ack error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: at 6.29 mhz) item symbol min. unit communication starts ? timing error t1 approx. 93 s communication starts ? communication start interrupt t2 approx. 1282 s communication start interrupt ? timing error t3 approx. 15 s communication start interrupt ? end of communication t4 approx. 1012 s receive data read interval t5 approx. 375 s
chapter 18 iebus controller (v850/sc2) user ? s manual u15109ej3v0ud 557 (3) slave transmission figure 18-23. slave transmission (interval of interrupt occurrence) start bit broad- casting telegraph length data master address slave address control pa pa pa pa pa pa p t1 t tt u data data data u tt t p p t t tt at t5 t4 t3 t6 t7 t7 t2 a p end of communication end of frame communication start communication start interrupt status request a remarks 1. t: timing error p: parity error a: ack error u: underrun error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: at 6.29 mhz) item symbol min. unit communication starts ? timing error t1 approx. 96 s communication starts ? communication start interrupt t2 approx. 1192 s communication start interrupt ? timing error t3 approx. 15 s communication start interrupt ? status request t4 approx. 225 s transmission data request interrupt interval t5 approx. 375 s status request ? timing error t6 approx. 15 s status request ? end of communication t7 approx. 787 s
chapter 18 iebus controller (v850/sc2) 558 user ? s manual u15109ej3v0ud (4) slave reception figure 18-24. slave reception (interval of interrupt occurrence) start bit broad- casting telegraph length data master address slave address control pa pa pa pa pa p a p t1 t tt data data data tt t p p tt at t4 t4 t5 t2 p pt a t3 end of communication end of frame communication start communication start interrupt p o a p o p a remarks 1. t: timing error p: parity error a: ack error o: overrun error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: at 6.29 mhz) item symbol min. unit communication starts ? timing error t1 approx. 96 s communication starts ? communication start interrupt t2 approx. 1192 s communication start interrupt ? timing error t3 approx. 15 s communication start interrupt ? end of communication t4 approx. 1012 s receive data read interval t5 approx. 375 s
user?s manual u15109ej3v0ud 559 chapter 19 fcan controller (v850/sc3) the v850/sc3 features an on-chip fcan (full controller area network) controller that complies with can specification ver. 2.0 partb active. (the v850/sc3 product line includes the pd703089y and pd70f3089y as two-channel devices and the pd703088y as a single-channel device.) 19.1 features ? can specification ver.2.0 partb active ? standard frame and expanded frame transmission/reception enabled ? remote frame automatic transmission enabled ? transfer rate: 1 mbps max. ? 32 message buffers 19.2 overview of functions table 19-1 presents an overview of fcan controller functions. table 19-1. overview of functions function description protocol can protocol ver. 2.0, partb active (standard and extended frame transmission/reception) baud rate maximum 1 mbps data storage ? allocated to common access-enabled ram area ? ram that is mapped to an unused message buffer can be used for cpu processing or other processing mask functions ? mask setting of four patterns is possible for each can module ? global ma sks and local ma sks can be used in common message configuration can be declared as transmit message or receive message no. of messages 32 messages message storage method ? storage in message buffer with unique id ? storage in buffer specified by receive mask function remote reception ? remote frames can be received in either the receive message buffer or the transmit message buffer ? if a remote frame is received by a transmit message buffer, there is a choice between having the remote request processed by the cpu or starting the auto transmit function. remote transmission the remote frame can be sent either by setting the transmit message?s rtr bit (m_ctrln register) or by setting the receive message?s send request. time stamp function a time stamp function can be set for receive messages and transmit messages. diagnostic functions ? read-enabled error counter ? ?valid protocol operation flag? for verification of bus connections ? receive-only mode (with auto baud rate detection) ? diagnostic processing mode low-power mode ? can sleep mode (wakeup function using can bus enabled) ? can stop mode (wakeup function using can bus disabled) remark n = 00 to 31
chapter 19 fcan controller (v850/sc3) user?s manual u15109ej3v0ud 560 19.3 configuration fcan is composed of the following four blocks. (1) npb interface this functional block provides an npb (nec peripheral i/o bus) interface and a means of transmitting and receiving signals. (2) mac (memory access controller) this functional block controls access to the can module within the fcan and to the can ram. (3) can module this functional block is involved in the operation of the can protocol layer and its related settings. (4) can ram this is the can memory functional block, which is used to store message ids, message data, etc.
chapter 19 fcan controller (v850/sc3) user?s manual u15109ej3v0ud 561 figure 19-1. block diagram of fcan cantx1 canrx1 cantx2 note canrx2 note cpu fcan controller can ram npb (nec peripheral i/o bus) mac (memory access controller) npb interface can module 1 interrupt request intcen intcrn intctn intcme can module 2 can transceiver 1 can transceiver 2 message buffer 0 message buffer 1 message buffer 2 message buffer 3 message buffer 31 c1mask0 c1mask1 c1mask2 c1mask3 c2mask0 c2mask1 c2mask2 c2mask3 ... can_h can_l can_h can_l can bus note pd703089y and 70f3089y only cautions 1. when p114/cantx1, p115/canrx1, p116/cantx2, p117/canrx2 are used during fcan transmission/reception, they can be used as fcan pin functions (cantx1, canrx1, cantx2, canrx2) by setting the port alternate function control register (pac) (refer to 5.2.10 (2) (b) port alternate-function control register (pac)). 2. when the p114/cantx1 and p116/cantx2 pins are used as cantx1, cantx2, set both the p11 and pm11 registers to 0 (refer to 5.3 using port pins as alternate-function pins). 3. when the p115/canrx1 and p117/canrx2 pins are used as canrx1 and canrx2, set the p11 register to 0 and the pm11 register to 1. 4. if the fcan register is read/written when the external bus interface function is used, an address/data control signal is output to the external expansion pins (ports 4, 5, 6, 9), so read/write of xx3ff800h to xx3fffffh, which is the fcan address area, should not be performed for the external devices connected to the external expansion pins. 5. if the wait function and idle function are set when the external bus interface function is used, these functions are enabled even reading/writing the fcan register. 6. since no clock is supplied from the subclock to fcan, when stopping the main clock and setting the subclock operation, do not read/write the fcan register. remark n = 1, 2
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 562 19.4 internal registers of fcan controller 19.4.1 configuration of messages and buffers table 19-2. configuration of messages and buffers address register name xx3ff800h to xx3ff81fh message buffer 0 field xx3ff820h to xx3ff83fh message buffer 1 field xx3ff840h to xx3ff85fh message buffer 2 field xx3ff860h to xx3ff87fh message buffer 3 field xx3ff880h to xx3ff89fh message buffer 4 field xx3ff8a0h to xx3ff8bfh message buffer 5 field xx3ff8c0h to xx3ff8dfh message buffer 6 field xx3ff8e0h to xx3ff8ffh message buffer 7 field xx3ff900h to xx3ff91fh message buffer 8 field xx3ff920h to xx3ff93fh message buffer 9 field xx3ff940h to xx3ff95fh message buffer 10 field xx3ff960h to xx3ff97fh message buffer 11 field xx3ff980h to xx3ff99fh message buffer 12 field xx3ff9a0h to xx3ff9bfh message buffer 13 field xx3ff9c0h to xx3ff9dfh message buffer 14 field xx3ff9e0h to xx3ff9ffh message buffer 15 field xx3ffa00h to xx3ffa1fh message buffer 16 field xx3ffa20h to xx3ffa3fh message buffer 17 field xx3ffa40h to xx3ffa5fh message buffer 18 field xx3ffa60h to xx3ffa7fh message buffer 19 field xx3ffa80h to xx3ffa9fh message buffer 20 field xx3ffaa0h to xx3ffabfh message buffer 21 field xx3ffac0h to xx3ffadfh message buffer 22 field xx3ffae0h to xx3ffaffh message buffer 23 field xx3ffb00h to xx3ffb1fh message buffer 24 field xx3ffb20h to xx3ffb3fh message buffer 25 field xx3ffb40h to xx3ffb5fh message buffer 26 field xx3ffb60h to xx3ffb7fh message buffer 27 field xx3ffb80h to xx3ffb9fh message buffer 28 field xx3ffba0h to xx3ffbbfh message buffer 29 field xx3ffbc0h to xx3ffbdfh message buffer 30 field xx3ffbe0h to xx3ffbffh message buffer 31 field caution the addresses xx3ff800h to xx3fffffh are specified as a physical fcan address area, whose image is visible in addresses xxnff800h to xxnfffffh (n = 7, b). accessing addresses from xxnff800h to xxnfffffh is prohibited. remark for details of message buffers, see 19.4.2 list of fcan registers .
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 563 19.4.2 list of fcan registers (1/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ff804h can message data length register 00 m_dlc00 xx3ff805h can message control register 00 m_ctrl00 xx3ff806h can message time stamp register 00 m_time00 xx3ff808h can message data register 000 m_data000 xx3ff809h can message data register 001 m_data001 xx3ff80ah can message data register 002 m_data002 xx3ff80bh can message data register 003 m_data003 xx3ff80ch can message data register 004 m_data004 xx3ff80dh can message data register 005 m_data005 xx3ff80eh can message data register 006 m_data006 xx3ff80fh can message data register 007 m_data007 xx3ff810h can message id register l00 m_idl00 xx3ff812h can message id register h00 m_idh00 xx3ff814h can message configuration register 00 m_conf00 r/w xx3ff815h can message status register 00 m_stat00 r undefined xx3ff816h can status set/clear register 00 sc_stat00 w 0000h xx3ff824h can message data length register 01 m_dlc01 xx3ff825h can message control register 01 m_ctrl01 xx3ff826h can message time stamp register 01 m_time01 xx3ff828h can message data register 010 m_data010 xx3ff829h can message data register 011 m_data011 xx3ff82ah can message data register 012 m_data012 xx3ff82bh can message data register 013 m_data013 xx3ff82ch can message data register 014 m_data014 xx3ff82dh can message data register 015 m_data015 xx3ff82eh can message data register 016 m_data016 xx3ff82fh can message data register 017 m_data017 xx3ff830h can message id register l01 m_idl01 xx3ff832h can message id register h01 m_idh01 xx3ff834h can message configuration register 01 m_conf01 r/w xx3ff835h can message status register 01 m_stat01 r undefined xx3ff836h can status set/clear register 01 sc_stat01 w 0000h xx3ff844h can message data length register 02 m_dlc02 xx3ff845h can message control register 02 m_ctrl02 xx3ff846h can message time stamp register 02 m_time02 xx3ff848h can message data register 020 m_data020 xx3ff849h can message data register 021 m_data021 xx3ff84ah can message data register 022 m_data022 xx3ff84bh can message data register 023 m_data023 xx3ff84ch can message data register 024 m_data024 xx3ff84dh can message data register 025 m_data025 r/w undefined
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 564 (2/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ff84eh can message data register 026 m_data026 xx3ff84fh can message data register 027 m_data027 xx3ff850h can message id register l02 m_idl02 xx3ff852h can message id register h02 m_idh02 xx3ff854h can message configuration register 02 m_conf02 r/w xx3ff855h can message status register 02 m_stat02 r undefined xx3ff856h can status set/clear register 02 sc_stat02 w 0000h xx3ff864h can message data length register 03 m_dlc03 xx3ff865h can message control register 03 m_ctrl03 xx3ff866h can message time stamp register 03 m_time03 xx3ff868h can message data register 030 m_data030 xx3ff869h can message data register 031 m_data031 xx3ff86ah can message data register 032 m_data032 xx3ff86bh can message data register 033 m_data033 xx3ff86ch can message data register 034 m_data034 xx3ff86dh can message data register 035 m_data035 xx3ff86eh can message data register 036 m_data036 xx3ff86fh can message data register 037 m_data037 xx3ff870h can message id register l03 m_idl03 xx3ff872h can message id register h03 m_idh03 xx3ff874h can message configuration register 03 m_conf03 r/w xx3ff875h can message status register 03 m_stat03 r undefined xx3ff876h can status set/clear register 03 sc_stat03 w 0000h xx3ff884h can message data length register 04 m_dlc04 xx3ff885h can message control register 04 m_ctrl04 xx3ff886h can message time stamp register 04 m_time04 xx3ff888h can message data register 040 m_data040 xx3ff889h can message data register 041 m_data041 xx3ff88ah can message data register 042 m_data042 xx3ff88bh can message data register 043 m_data043 xx3ff88ch can message data register 044 m_data044 xx3ff88dh can message data register 045 m_data045 xx3ff88eh can message data register 046 m_data046 xx3ff88fh can message data register 047 m_data047 xx3ff890h can message id register l04 m_idl04 xx3ff892h can message id register h04 m_idh04 xx3ff894h can message configuration register 04 m_conf04 r/w xx3ff895h can message status register 04 m_stat04 r undefined xx3ff896h can status set/clear register 04 sc_stat04 w 0000h xx3ff8a4h can message data length register 05 m_dlc05 xx3ff8a5h can message control register 05 m_ctrl05 xx3ff8a6h can message time stamp register 05 m_time05 xx3ff8a8h can message data register 050 m_data050 xx3ff8a9h can message data register 051 m_data051 r/w undefined
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 565 (3/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ff8aah can message data register 052 m_data052 xx3ff8abh can message data register 053 m_data053 xx3ff8ach can message data register 054 m_data054 xx3ff8adh can message data register 055 m_data055 xx3ff8aeh can message data register 056 m_data056 xx3ff8afh can message data register 057 m_data057 xx3ff8b0h can message id register l05 m_idl05 xx3ff8b2h can message id register h05 m_idh05 xx3ff8b4h can message configuration register 05 m_conf05 r/w xx3ff8b5h can message status register 05 m_stat05 r undefined xx3ff8b6h can status set/clear register 05 sc_stat05 w 0000h xx3ff8c4h can message data length register 06 m_dlc06 xx3ff8c5h can message control register 06 m_ctrl06 xx3ff8c6h can message time stamp register 06 m_time06 xx3ff8c8h can message data register 060 m_data060 xx3ff8c9h can message data register 061 m_data061 xx3ff8cah can message data register 062 m_data062 xx3ff8cbh can message data register 063 m_data063 xx3ff8cch can message data register 064 m_data064 xx3ff8cdh can message data register 065 m_data065 xx3ff8ceh can message data register 066 m_data066 xx3ff8cfh can message data register 067 m_data067 xx3ff8d0h can message id register l06 m_idl06 xx3ff8d2h can message id register h06 m_idh06 xx3ff8d4h can message configuration register 06 m_conf06 r/w xx3ff8d5h can message status register 06 m_stat06 r undefined xx3ff8d6h can status set/clear register 06 sc_stat06 w 0000h xx3ff8e4h can message data length register 07 m_dlc07 xx3ff8e5h can message control register 07 m_ctrl07 xx3ff8e6h can message time stamp register 07 m_time07 xx3ff8e8h can message data register 070 m_data070 xx3ff8e9h can message data register 071 m_data071 xx3ff8eah can message data register 072 m_data072 xx3ff8ebh can message data register 073 m_data073 xx3ff8ech can message data register 074 m_data074 xx3ff8edh can message data register 075 m_data075 xx3ff8eeh can message data register 076 m_data076 xx3ff8efh can message data register 077 m_data077 xx3ff8f0h can message id register l07 m_idl07 xx3ff8f2h can message id register h07 m_idh07 xx3ff8f4h can message configuration register 07 m_conf07 r/w xx3ff8f5h can message status register 07 m_stat07 r undefined xx3ff8f6h can status set/clear register 07 sc_stat07 w 0000h xx3ff904h can message data length register 08 m_dlc08 r/w undefined
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 566 (4/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ff905h can message control register 08 m_ctrl08 xx3ff906h can message time stamp register 08 m_time08 xx3ff908h can message data register 080 m_data080 xx3ff909h can message data register 081 m_data081 xx3ff90ah can message data register 082 m_data082 xx3ff90bh can message data register 083 m_data083 xx3ff90ch can message data register 084 m_data084 xx3ff90dh can message data register 085 m_data085 xx3ff90eh can message data register 086 m_data086 xx3ff90fh can message data register 087 m_data087 xx3ff910h can message id register l08 m_idl08 xx3ff912h can message id register h08 m_idh08 xx3ff914h can message configuration register 08 m_conf08 r/w xx3ff915h can message status register 08 m_stat08 r undefined xx3ff916h can status set/clear register 08 sc_stat08 w 0000h xx3ff924h can message data length register 09 m_dlc09 xx3ff925h can message control register 09 m_ctrl09 xx3ff926h can message time stamp register 09 m_time09 xx3ff928h can message data register 090 m_data090 xx3ff929h can message data register 091 m_data091 xx3ff92ah can message data register 092 m_data092 xx3ff92bh can message data register 093 m_data093 xx3ff92ch can message data register 094 m_data094 xx3ff92dh can message data register 095 m_data095 xx3ff92eh can message data register 096 m_data096 xx3ff92fh can message data register 097 m_data097 xx3ff930h can message id register l09 m_idl09 xx3ff932h can message id register h09 m_idh09 xx3ff934h can message configuration register 09 m_conf09 r/w xx3ff935h can message status register 09 m_stat09 r undefined xx3ff936h can status set/clear register 09 sc_stat09 w 0000h xx3ff944h can message data length register 10 m_dlc10 xx3ff945h can message control register 10 m_ctrl10 xx3ff946h can message time stamp register 10 m_time10 xx3ff948h can message data register 100 m_data100 xx3ff949h can message data register 101 m_data101 xx3ff94ah can message data register 102 m_data102 xx3ff94bh can message data register 103 m_data103 xx3ff94ch can message data register 104 m_data104 xx3ff94dh can message data register 105 m_data105 xx3ff94eh can message data register 106 m_data106 xx3ff94fh can message data register 107 m_data107 xx3ff950h can message id register l10 m_idl10 xx3ff952h can message id register h10 m_idh10 r/w undefined
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 567 (5/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ff954h can message configuration register 10 m_conf10 r/w xx3ff955h can message status register 10 m_stat10 r undefined xx3ff956h can status set/clear register 10 sc_stat10 w 0000h xx3ff964h can message data length register 11 m_dlc11 xx3ff965h can message control register 11 m_ctrl11 xx3ff966h can message time stamp register 11 m_time11 xx3ff968h can message data register 110 m_data110 xx3ff969h can message data register 111 m_data111 xx3ff96ah can message data register 112 m_data112 xx3ff96bh can message data register 113 m_data113 xx3ff96ch can message data register 114 m_data114 xx3ff96dh can message data register 115 m_data115 xx3ff96eh can message data register 116 m_data116 xx3ff96fh can message data register 117 m_data117 xx3ff970h can message id register l11 m_idl11 xx3ff972h can message id register h11 m_idh11 xx3ff974h can message configuration register 11 m_conf11 r/w xx3ff975h can message status register 11 m_stat11 r undefined xx3ff976h can status set/clear register 11 sc_stat11 w 0000h xx3ff984h can message data length register 12 m_dlc12 xx3ff985h can message control register 12 m_ctrl12 xx3ff986h can message time stamp register 12 m_time12 xx3ff988h can message data register 120 m_data120 xx3ff989h can message data register 121 m_data121 xx3ff98ah can message data register 122 m_data122 xx3ff98bh can message data register 123 m_data123 xx3ff98ch can message data register 124 m_data124 xx3ff98dh can message data register 125 m_data125 xx3ff98eh can message data register 126 m_data126 xx3ff98fh can message data register 127 m_data127 xx3ff990h can message id register l12 m_idl12 xx3ff992h can message id register h12 m_idh12 xx3ff994h can message configuration register 12 m_conf12 r/w xx3ff995h can message status register 12 m_stat12 r undefined xx3ff996h can status set/clear register 12 sc_stat12 w 0000h xx3ff9a4h can message data length register 13 m_dlc13 xx3ff9a5h can message control register 13 m_ctrl13 xx3ff9a6h can message time stamp register 13 m_time13 xx3ff9a8h can message data register 130 m_data130 xx3ff9a9h can message data register 131 m_data131 xx3ff9aah can message data register 132 m_data132 xx3ff9abh can message data register 133 m_data133 xx3ff9ach can message data register 134 m_data134 xx3ff9adh can message data register 135 m_data135 r/w undefined
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 568 (6/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ff9aeh can message data register 136 m_data136 xx3ff9afh can message data register 137 m_data137 xx3ff9b0h can message id register l13 m_idl13 xx3ff9b2h can message id register h13 m_idh13 xx3ff9b4h can message configuration register 13 m_conf13 r/w xx3ff9b5h can message status register 13 m_stat13 r undefined xx3ff9b6h can status set/clear register 13 sc_stat13 w 0000h xx3ff9c4h can message data length register 14 m_dlc14 xx3ff9c5h can message control register 14 m_ctrl14 xx3ff9c6h can message time stamp register 14 m_time14 xx3ff9c8h can message data register 140 m_data140 xx3ff9c9h can message data register 141 m_data141 xx3ff9cah can message data register 142 m_data142 xx3ff9cbh can message data register 143 m_data143 xx3ff9cch can message data register 144 m_data144 xx3ff9cdh can message data register 145 m_data145 xx3ff9ceh can message data register 146 m_data146 xx3ff9cfh can message data register 147 m_data147 xx3ff9d0h can message id register l14 m_idl14 xx3ff9d2h can message id register h14 m_idh14 xx3ff9d4h can message configuration register 14 m_conf14 r/w xx3ff9d5h can message status register 14 m_stat14 r undefined xx3ff9d6h can status set/clear register 14 sc_stat14 w 0000h xx3ff9e4h can message data length register 15 m_dlc15 xx3ff9e5h can message control register 15 m_ctrl15 xx3ff9e6h can message time stamp register 15 m_time15 xx3ff9e8h can message data register 150 m_data150 xx3ff9e9h can message data register 151 m_data151 xx3ff9eah can message data register 152 m_data152 xx3ff9ebh can message data register 153 m_data153 xx3ff9ech can message data register 154 m_data154 xx3ff9edh can message data register 155 m_data155 xx3ff9eeh can message data register 156 m_data156 xx3ff9efh can message data register 157 m_data157 xx3ff9f0h can message id register l15 m_idl15 xx3ff9f2h can message id register h15 m_idh15 xx3ff9f4h can message configuration register 15 m_conf15 r/w xx3ff9f5h can message status register 15 m_stat15 r undefined xx3ff9f6h can status set/clear register 15 sc_stat15 w 0000h xx3ffa04h can message data length register 16 m_dlc16 xx3ffa05h can message control register 16 m_ctrl16 xx3ffa06h can message time stamp register 16 m_time16 xx3ffa08h can message data register 160 m_data160 xx3ffa09h can message data register 161 m_data161 r/w undefined
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 569 (7/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ffa0ah can message data register 162 m_data162 xx3ffa0bh can message data register 163 m_data163 xx3ffa0ch can message data register 164 m_data164 xx3ffa0dh can message data register 165 m_data165 xx3ffa0eh can message data register 166 m_data166 xx3ffa0fh can message data register 167 m_data167 xx3ffa10h can message id register l16 m_idl16 xx3ffa12h can message id register h16 m_idh16 xx3ffa14h can message configuration register 16 m_conf16 r/w xx3ffa15h can message status register 16 m_stat16 r undefined xx3ffa16h can status set/clear register 16 sc_stat16 w 0000h xx3ffa24h can message data length register 17 m_dlc17 xx3ffa25h can message control register 17 m_ctrl17 xx3ffa26h can message time stamp register 17 m_time17 xx3ffa28h can message data register 170 m_data170 xx3ffa29h can message data register 171 m_data171 xx3ffa2ah can message data register 172 m_data172 xx3ffa2bh can message data register 173 m_data173 xx3ffa2ch can message data register 174 m_data174 xx3ffa2dh can message data register 175 m_data175 xx3ffa2eh can message data register 176 m_data176 xx3ffa2fh can message data register 177 m_data177 xx3ffa30h can message id register l17 m_idl17 xx3ffa32h can message id register h17 m_idh17 xx3ffa34h can message configuration register 17 m_conf17 r/w xx3ffa35h can message status register 17 m_stat17 r undefined xx3ffa36h can status set/clear register 17 sc_stat17 w 0000h xx3ffa44h can message data length register 18 m_dlc18 xx3ffa45h can message control register 18 m_ctrl18 xx3ffa46h can message time stamp register 18 m_time18 xx3ffa48h can message data register 180 m_data180 xx3ffa49h can message data register 181 m_data181 xx3ffa4ah can message data register 182 m_data182 xx3ffa4bh can message data register 183 m_data183 xx3ffa4ch can message data register 184 m_data184 xx3ffa4dh can message data register 185 m_data185 xx3ffa4eh can message data register 186 m_data186 xx3ffa4fh can message data register 187 m_data187 xx3ffa50h can message id register l18 m_idl18 xx3ffa52h can message id register h18 m_idh18 xx3ffa54h can message configuration register 18 m_conf18 r/w xx3ffa55h can message status register 18 m_stat18 r undefined xx3ffa56h can status set/clear register 18 sc_stat18 w 0000h xx3ffa64h can message data length register 19 m_dlc19 r/w undefined
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 570 (8/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ffa65h can message control register 19 m_ctrl19 xx3ffa66h can message time stamp register 19 m_time19 xx3ffa68h can message data register 190 m_data190 xx3ffa69h can message data register 191 m_data191 xx3ffa6ah can message data register 192 m_data192 xx3ffa6bh can message data register 193 m_data193 xx3ffa6ch can message data register 194 m_data194 xx3ffa6dh can message data register 195 m_data195 xx3ffa6eh can message data register 196 m_data196 xx3ffa6fh can message data register 197 m_data197 xx3ffa70h can message id register l19 m_idl19 xx3ffa72h can message id register h19 m_idh19 xx3ffa74h can message configuration register 19 m_conf19 r/w xx3ffa75h can message status register 19 m_stat19 r undefined xx3ffa76h can status set/clear register 19 sc_stat19 w 0000h xx3ffa84h can message data length register 20 m_dlc20 xx3ffa85h can message control register 20 m_ctrl20 xx3ffa86h can message time stamp register 20 m_time20 xx3ffa88h can message data register 200 m_data200 xx3ffa89h can message data register 201 m_data201 xx3ffa8ah can message data register 202 m_data202 xx3ffa8bh can message data register 203 m_data203 xx3ffa8ch can message data register 204 m_data204 xx3ffa8dh can message data register 205 m_data205 xx3ffa8eh can message data register 206 m_data206 xx3ffa8fh can message data register 207 m_data207 xx3ffa90h can message id register l20 m_idl20 xx3ffa92h can message id register h20 m_idh20 xx3ffa94h can message configuration register 20 m_conf20 r/w xx3ffa95h can message status register 20 m_stat20 r undefined xx3ffa96h can status set/clear register 20 sc_stat20 w 0000h xx3ffaa4h can message data length register 21 m_dlc21 xx3ffaa5h can message control register 21 m_ctrl21 xx3ffaa6h can message time stamp register 21 m_time21 xx3ffaa8h can message data register 210 m_data210 xx3ffaa9h can message data register 211 m_data211 xx3ffaaah can message data register 212 m_data212 xx3ffaabh can message data register 213 m_data213 xx3ffaach can message data register 214 m_data214 xx3ffaadh can message data register 215 m_data215 xx3ffaaeh can message data register 216 m_data216 xx3ffaafh can message data register 217 m_data217 xx3ffab0h can message id register l21 m_idl21 xx3ffab2h can message id register h21 m_idh21 r/w undefined
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 571 (9/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ffab4h can message configuration register 21 m_conf21 r/w xx3ffab5h can message status register 21 m_stat21 r undefined xx3ffab6h can status set/clear register 21 sc_stat21 w 0000h xx3ffac4h can message data length register 22 m_dlc22 xx3ffac5h can message control register 22 m_ctrl22 xx3ffac6h can message time stamp register 22 m_time22 xx3ffac8h can message data register 220 m_data220 xx3ffac9h can message data register 221 m_data221 xx3ffacah can message data register 222 m_data222 xx3ffacbh can message data register 223 m_data223 xx3ffacch can message data register 224 m_data224 xx3ffacdh can message data register 225 m_data225 xx3ffaceh can message data register 226 m_data226 xx3ffacfh can message data register 227 m_data227 xx3ffad0h can message id register l22 m_idl22 xx3ffad2h can message id register h22 m_idh22 xx3ffad4h can message configuration register 22 m_conf22 r/w xx3ffad5h can message status register 22 m_stat22 r undefined xx3ffad6h can status set/clear register 22 sc_stat22 w 0000h xx3ffae4h can message data length register 23 m_dlc23 xx3ffae5h can message control register 23 m_ctrl23 xx3ffae6h can message time stamp register 23 m_time23 xx3ffae8h can message data register 230 m_data230 xx3ffae9h can message data register 231 m_data231 xx3ffaeah can message data register 232 m_data232 xx3ffaebh can message data register 233 m_data233 xx3ffaech can message data register 234 m_data234 xx3ffaedh can message data register 235 m_data235 xx3ffaeeh can message data register 236 m_data236 xx3ffaefh can message data register 237 m_data237 xx3ffaf0h can message id register l23 m_idl23 xx3ffaf2h can message id register h23 m_idh23 xx3ffaf4h can message configuration register 23 m_conf23 r/w xx3ffaf5h can message status register 23 m_stat23 r undefined xx3ffaf6h can status set/clear register 23 sc_stat23 w 0000h xx3ffb04h can message data length register 24 m_dlc24 xx3ffb05h can message control register 24 m_ctrl24 xx3ffb06h can message time stamp register 24 m_time24 xx3ffb08h can message data register 240 m_data240 xx3ffb09h can message data register 241 m_data241 xx3ffb0ah can message data register 242 m_data242 xx3ffb0bh can message data register 243 m_data243 xx3ffb0ch can message data register 244 m_data244 xx3ffb0dh can message data register 245 m_data245 r/w undefined
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 572 (10/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ffb0eh can message data register 246 m_data246 xx3ffb0fh can message data register 247 m_data247 xx3ffb10h can message id register l24 m_idl24 xx3ffb12h can message id register h24 m_idh24 xx3ffb14h can message configuration register 24 m_conf24 r/w xx3ffb15h can message status register 24 m_stat24 r undefined xx3ffb16h can status set/clear register 24 sc_stat24 w 0000h xx3ffb24h can message data length register 25 m_dlc25 xx3ffb25h can message control register 25 m_ctrl25 xx3ffb26h can message time stamp register 25 m_time25 xx3ffb28h can message data register 250 m_data250 xx3ffb29h can message data register 251 m_data251 xx3ffb2ah can message data register 252 m_data252 xx3ffb2bh can message data register 253 m_data253 xx3ffb2ch can message data register 254 m_data254 xx3ffb2dh can message data register 255 m_data255 xx3ffb2eh can message data register 256 m_data256 xx3ffb2fh can message data register 257 m_data257 xx3ffb30h can message id register l25 m_idl25 xx3ffb32h can message id register h25 m_idh25 xx3ffb34h can message configuration register 25 m_conf25 r/w xx3ffb35h can message status register 25 m_stat25 r undefined xx3ffb36h can status set/clear register 25 sc_stat25 w 0000h xx3ffb44h can message data length register 26 m_dlc26 xx3ffb45h can message control register 26 m_ctrl26 xx3ffb46h can message time stamp register 26 m_time26 xx3ffb48h can message data register 260 m_data260 xx3ffb49h can message data register 261 m_data261 xx3ffb4ah can message data register 262 m_data262 xx3ffb4bh can message data register 263 m_data263 xx3ffb4ch can message data register 264 m_data264 xx3ffb4dh can message data register 265 m_data265 xx3ffb4eh can message data register 266 m_data266 xx3ffb4fh can message data register 267 m_data267 xx3ffb50h can message id register l26 m_idl26 xx3ffb52h can message id register h26 m_idh26 xx3ffb54h can message configuration register 26 m_conf26 r/w xx3ffb55h can message status register 26 m_stat26 r undefined xx3ffb56h can status set/clear register 26 sc_stat26 w 0000h xx3ffb64h can message data length register 27 m_dlc27 xx3ffb65h can message control register 27 m_ctrl27 xx3ffb66h can message time stamp register 27 m_time27 xx3ffb68h can message data register 270 m_data270 xx3ffb69h can message data register 271 m_data271 r/w undefined
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 573 (11/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ffb6ah can message data register 272 m_data272 xx3ffb6bh can message data register 273 m_data273 xx3ffb6ch can message data register 274 m_data274 xx3ffb6dh can message data register 275 m_data275 xx3ffb6eh can message data register 276 m_data276 xx3ffb6fh can message data register 277 m_data277 xx3ffb70h can message id register l27 m_idl27 xx3ffb72h can message id register h27 m_idh27 xx3ffb74h can message configuration register 27 m_conf27 r/w xx3ffb75h can message status register 27 m_stat27 r undefined xx3ffb76h can status set/clear register 27 sc_stat27 w 0000h xx3ffb84h can message data length register 28 m_dlc28 xx3ffb85h can message control register 28 m_ctrl28 xx3ffb86h can message time stamp register 28 m_time28 xx3ffb88h can message data register 280 m_data280 xx3ffb89h can message data register 281 m_data281 xx3ffb8ah can message data register 282 m_data282 xx3ffb8bh can message data register 283 m_data283 xx3ffb8ch can message data register 284 m_data284 xx3ffb8dh can message data register 285 m_data285 xx3ffb8eh can message data register 286 m_data286 xx3ffb8fh can message data register 287 m_data287 xx3ffb90h can message id register l28 m_idl28 xx3ffb92h can message id register h28 m_idh28 xx3ffb94h can message configuration register 28 m_conf28 r/w xx3ffb95h can message status register 28 m_stat28 r undefined xx3ffb96h can status set/clear register 28 sc_stat28 w 0000h xx3ffba4h can message data length register 29 m_dlc29 xx3ffba5h can message control register 29 m_ctrl29 xx3ffba6h can message time stamp register 29 m_time29 xx3ffba8h can message data register 290 m_data290 xx3ffba9h can message data register 291 m_data291 xx3ffbaah can message data register 292 m_data292 xx3ffbabh can message data register 293 m_data293 xx3ffbach can message data register 294 m_data294 xx3ffbadh can message data register 295 m_data295 xx3ffbaeh can message data register 296 m_data296 xx3ffbafh can message data register 297 m_data297 xx3ffbb0h can message id register l29 m_idl29 xx3ffbb2h can message id register h29 m_idh29 xx3ffbb4h can message configuration register 29 m_conf29 r/w xx3ffbb5h can message status register 29 m_stat29 r undefined xx3ffbb6h can status set/clear register 29 sc_stat29 w 0000h xx3ffbc4h can message data length register 30 m_dlc30 r/w undefined
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 574 (12/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ffbc5h can message control register 30 m_ctrl30 xx3ffbc6h can message time stamp register 30 m_time30 xx3ffbc8h can message data register 300 m_data300 xx3ffbc9h can message data register 301 m_data301 xx3ffbcah can message data register 302 m_data302 xx3ffbcbh can message data register 303 m_data303 xx3ffbcch can message data register 304 m_data304 xx3ffbcdh can message data register 305 m_data305 xx3ffbceh can message data register 306 m_data306 xx3ffbcfh can message data register 307 m_data307 xx3ffbd0h can message id register l30 m_idl30 xx3ffbd2h can message id register h30 m_idh30 xx3ffbd4h can message configuration register 30 m_conf30 r/w xx3ffbd5h can message status register 30 m_stat30 r undefined xx3ffbd6h can status set/clear register 30 sc_stat30 w 0000h xx3ffbe4h can message data length register 31 m_dlc31 xx3ffbe5h can message control register 31 m_ctrl31 xx3ffbe6h can message time stamp register 31 m_time31 xx3ffbe8h can message data register 310 m_data310 xx3ffbe9h can message data register 311 m_data311 xx3ffbeah can message data register 312 m_data312 xx3ffbebh can message data register 313 m_data313 xx3ffbech can message data register 314 m_data314 xx3ffbedh can message data register 315 m_data315 xx3ffbeeh can message data register 316 m_data316 xx3ffbefh can message data register 317 m_data317 xx3ffbf0h can message id register l31 m_idl31 xx3ffbf2h can message id register h31 m_idh31 xx3ffbf4h can message configuration register 31 m_conf31 r/w xx3ffbf5h can message status register 31 m_stat31 r undefined xx3ffbf6h can status set/clear register 31 sc_stat31 w xx3ffc00h can stop register cstop r/w xx3ffc04h can interrupt pending register ccintp r xx3ffc10h can global status register cgst xx3ffc12h can global interrupt enable register cgie 0000h xx3ffc14h can main clock select register cgcs r/w 7f05h xx3ffc18h can time stamp count register cgtsc r can message search start register cgmss w xx3ffc1ah can message search result register cgmsr r 0000h xx3ffc20h can global interrupt pending register cgintp ? xx3ffc22h can1 interrupt pending register c1intp ? xx3ffc24h can2 interrupt pending register note c2intp r/w ? 0000h note pd703089y and 70f3089y only
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 575 (13/13) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset xx3ffc40h can1 address mask 0 register l c1maskl0 xx3ffc42h can1 address mask 0 register h c1maskh0 xx3ffc44h can1 address mask 1 register l c1maskl1 xx3ffc46h can1 address mask 1 register h c1maskh1 xx3ffc48h can1 address mask 2 register l c1maskl2 xx3ffc4ah can1 address mask 2 register h c1maskh2 xx3ffc4ch can1 address mask 3 register l c1maskl3 xx3ffc4eh can1 address mask 3 register h c1maskh3 undefined xx3ffc50h can1 control register c1ctrl 0101h xx3ffc52h can1 definition register c1def r/w 0000h xx3ffc54h can1 information register c1last 00ffh xx3ffc56h can1 error count register c1erc r xx3ffc58h can1 interrupt enable register c1ie r/w 0000h xx3ffc5ah can1 bus active register c1ba r 00ffh can1 bit rate prescaler register c1brp r/w 0000h xx3ffc5ch can1 bus diagnostic information register c1dinf r xx3ffc5eh can1 synchronization control register c1sync 0218h xx3ffc80h can2 address mask 0 register l note c2maskl0 xx3ffc82h can2 address mask 0 register h note c2maskh0 xx3ffc84h can2 address mask 1 register l note c2maskl1 xx3ffc86h can2 address mask 1 register h note c2maskh1 xx3ffc88h can2 address mask 2 register l note c2maskl2 xx3ffc8ah can2 address mask 2 register h note c2maskh2 xx3ffc8ch can2 address mask 3 register l note c2maskl3 xx3ffc8eh can2 address mask 3 register h note c2maskh3 undefined xx3ffc90h can2 control register note c2ctrl 0101h xx3ffc92h can2 definition register note c2def r/w 0000h xx3ffc94h can2 information register note c2last 00ffh xx3ffc96h can2 error count register note c2erc r xx3ffc98h can2 interrupt enable register note c2ie r/w 0000h xx3ffc9ah can2 bus active register note c2ba r 00ffh can2 bit rate prescaler register note c2brp r/w 0000h xx3ffc9ch can2 bus diagnostic information register note c2dinf r xx3ffc9eh can2 synchronization control register note c2sync r/w 0218h note pd703089y and 70f3089y only
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 576 19.5 control registers 19.5.1 can message data length registers 00 to 31 (m_dlc00 to m_dlc31) the m_dlcn register sets the byte count in the data field of can message buffer n (n = 00 to 31). when receiving, the receive data field ? s byte count is set (1). these registers can be read/written in 8-bit units. after reset: undefined r/w address: see table 19-3 76543210 m_dlcn rfu note rfu note rfu note rfu note dlc3 dlc2 dlc1 dlc0 (n = 00 to 31) dlc3 dlc2 dlc1 dlc0 data length code of transmit/receive message 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes other than above 8 bytes regardless of dlc value note rfu (reserved for future use) indicates a reserved bit. always set this bit to 0 when writing the m_dlcn register. table 19-3. addresses of m_dlcn (n = 00 to 31) register name address register name address m_dlc00 xx3ff804h m_dlc16 xx3ffa04h m_dlc01 xx3ff824h m_dlc17 xx3ffa24h m_dlc02 xx3ff844h m_dlc18 xx3ffa44h m_dlc03 xx3ff864h m_dlc19 xx3ffa64h m_dlc04 xx3ff884h m_dlc20 xx3ffa84h m_dlc05 xx3ff8a4h m_dlc21 xx3ffaa4h m_dlc06 xx3ff8c4h m_dlc22 xx3ffac4h m_dlc07 xx3ff8e4h m_dlc23 xx3ffae4h m_dlc08 xx3ff904h m_dlc24 xx3ffb04h m_dlc09 xx3ff924h m_dlc25 xx3ffb24h m_dlc10 xx3ff944h m_dlc26 xx3ffb44h m_dlc11 xx3ff964h m_dlc27 xx3ffb64h m_dlc12 xx3ff984h m_dlc28 xx3ffb84h m_dlc13 xx3ff9a4h m_dlc29 xx3ffba4h m_dlc14 xx3ff9c4h m_dlc30 xx3ffbc4h m_dlc15 xx3ff9e4h m_dlc31 xx3ffbe4h
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 577 19.5.2 can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) the m_ctrln register is used to control operation of can message buffer n (n = 00 to 31). these registers can be read/written in 8-bit units. (1/2) after reset: undefined r/w address: see table 19-4 76543210 m_ctrln rmde1 rmde0 ats ie movr rfu notes1, 2 rfu notes1, 3 rtr (n = 00 to 31) rmde1 specifies operation of dn flag when remote frame is received on a transmit message buffer 0 dn flag not set (1) when remote frame is received 1 dn flag set (1) when remote frame is received ? when the rmde1 bit is set, the setting of the rmde0 bit is irrelevant. ? if a remote frame is received on the transmit message buffer when the rmde1 and rmde0 bits have not been set (1), the cpu is not notified, nor are other operations performed. rmde0 specification of set/clear status of remote frame auto acknowledge function 0 remote frame auto acknowledge function cleared 1 remote frame auto acknowledge function set ? the rmde0 bit ? s setting is used only for transmit message buffers. ? when the rtr bit has been set (1) (when the receive message or transmit message has a remote frame), the rmde0 bit is processed as rmde0 = 0. this prevents transmission of the same remote frame during remote frame reception. if the same remote frame is transmitted under the worst conditions, the bus load reaches 100%. ats specifies whether or not to add a time stamp when transmitting 0 time stamp not added when transmitting 1 time stamp added when transmitting ? the ats bit is used only for transmit messages. ? when the ats bit has been set (1) and the data length code specifies at least two bytes, the last two bytes are replaced by a time stamp (see table 19-12 ). the added time stamp counter value is sent to the bus via the message ? s sof. when this occurs, the last two bytes (which are defined as a data field) are ignored. notes 1. rfu (reserved for future use) indicates a reserved bit. always set this bit to 0 when writing. 2. the value of the r1 bit on the can bus is set during reception. 3. the value of the r0 bit on the can bus is set during reception. remark dn: bit 2 of m_statm (see 19.5.7 can message status registers 00 to 31 (m_stat00 to m_stat31) .)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 578 (2/2) ie specifies the enable/disable setting for interrupt requests 0 interrupt requests disabled 1 interrupt requests enabled ? an interrupt request occurs when the ie bit is 1 under the following conditions. ? when a message is sent from the transmit message buffer ? when a message is received by the receive message buffer ? when a remote frame has been transmitted from the receive message buffer ? when a remote frame is received by the transmit message buffer when the auto acknowledge function has not been set (rmde0 bit = 0). ? an interrupt request does not occur when the ie bit is 1 under the following conditions. ? when a remote frame is received by the transmit message buffer when the auto acknowledge function has been set (rmde0 bit = 1) ? an interrupt request occurs when the ie bit is 0 under the following conditions. ? when a remote frame is received by the receive message buffer when the auto acknowledge function has not been set (rmde0 bit = 0). movr message buffer overwrite 0 overwrite does not occur after dn bit is cleared 1 overwrite occurs at least once after dn bit is cleared ? an overwrite of the message buffer occurs when the can module writes new data to the message buffer or when the dn bit has already been set (1). the movr bit is updated each time new data is stored in the message buffer. rtr specification of frame type 0 data frame transmit/receive 1 remote frame transmit/receive ? when the rtr bit has been set (1) for a transmit message, a remote frame is transmitted instead of a data frame. remark dn: bit 2 of m_statm (see 19.5.7 can message status registers 00 to 31 (m_stat00 to m_stat31) .)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 579 table 19-4. addresses of m_ctrln (n = 00 to 31) register name address register name address m_ctrl00 xx3ff805h m_ctrl16 xx3ffa05h m_ctrl01 xx3ff825h m_ctrl17 xx3ffa25h m_ctrl02 xx3ff845h m_ctrl18 xx3ffa45h m_ctrl03 xx3ff865h m_ctrl19 xx3ffa65h m_ctrl04 xx3ff885h m_ctrl20 xx3ffa85h m_ctrl05 xx3ff8a5h m_ctrl21 xx3ffaa5h m_ctrl06 xx3ff8c5h m_ctrl22 xx3ffac5h m_ctrl07 xx3ff8e5h m_ctrl23 xx3ffae5h m_ctrl08 xx3ff905h m_ctrl24 xx3ffb05h m_ctrl09 xx3ff925h m_ctrl25 xx3ffb25h m_ctrl10 xx3ff945h m_ctrl26 xx3ffb45h m_ctrl11 xx3ff965h m_ctrl27 xx3ffb65h m_ctrl12 xx3ff985h m_ctrl28 xx3ffb85h m_ctrl13 xx3ff9a5h m_ctrl29 xx3ffba5h m_ctrl14 xx3ff9c5h m_ctrl30 xx3ffbc5h m_ctrl15 xx3ff9e5h m_ctrl31 xx3ffbe5h 19.5.3 can message time stamp registers 00 to 31 (m_time00 to m_time31) the m_timen register is the area where the time stamp counter value is written upon completion of data reception (n = 00 to 31). these registers can be read/written in 16-bit units. when a data frame or remote frame is received in the receive message buffer, the new data is stored in the message buffer and a 16-bit time tag (time stamp counter value) is stored in the m_timen register. this time tag is set according to the fcan ? s time stamp setting, which is either the time stamp counter value that was captured when the sof was sent on the can bus or the value captured when the can module writes data to the message buffer. after reset: undefined r/w address: see table 19-5 1514131211109876543210 m_timen (n = 00 to 31) ts 15 ts 14 ts 13 ts 12 ts 11 ts 10 ts 09 ts 08 ts 07 ts 06 ts 05 ts 04 ts 03 ts 02 ts 01 ts 00
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 580 table 19-5. addresses of m_timen (n = 00 to 31) register name address register name address m_time00 xx3ff806h m_time16 xx3ffa06h m_time01 xx3ff826h m_time17 xx3ffa26h m_time02 xx3ff846h m_time18 xx3ffa46h m_time03 xx3ff866h m_time19 xx3ffa66h m_time04 xx3ff886h m_time20 xx3ffa86h m_time05 xx3ff8a6h m_time21 xx3ffaa6h m_time06 xx3ff8c6h m_time22 xx3ffac6h m_time07 xx3ff8e6h m_time23 xx3ffae6h m_time08 xx3ff906h m_time24 xx3ffb06h m_time09 xx3ff926h m_time25 xx3ffb26h m_time10 xx3ff946h m_time26 xx3ffb46h m_time11 xx3ff966h m_time27 xx3ffb66h m_time12 xx3ff986h m_time28 xx3ffb86h m_time13 xx3ff9a6h m_time29 xx3ffba6h m_time14 xx3ff9c6h m_time30 xx3ffbc6h m_time15 xx3ff9e6h m_time31 xx3ffbe6h
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 581 19.5.4 can message data registers n0 to n7 (m_datan0 to m_datan7) the m_datan0 to m_datan7 registers are areas where up to 8 bytes of transmit or receive message data is stored. these registers can be read/written in 8-bit units. the m_datan0 to m_datan7 registers are used to hold receive message data and transmit message data. when data is transmitted, the number of messages defined by the dlc3 to dlc0 bits in the m_dlcn register are transmitted via the can bus. when the m_ctrln register ? s ats bit has been set (1) and the value of the dlc3 to dlc0 bits in the m_dlcn register is at least two bytes, the last two bytes that are sent normally via the can bus are ignored and the time stamp value is sent. when a new message is received, all data fields are updated, even when the value of the dlc3 to dlc0 bits in the m_dlcn register is less than 8 bytes. the values of data bytes that have not been received on the can bus may be updated, but they are ignored. remark n = 00 to 31, x = 0 to 7 76543210addressafter reset m_datan0 d07 d06 d05 d04 d03 d02 d01 d00 see table 19-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan1 d17 d16 d15 d14 d13 d12 d11 d10 see table 19-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan2 d27 d26 d25 d24 d23 d22 d21 d20 see table 19-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan3 d37 d36 d35 d34 d33 d32 d31 d30 see table 19-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan4 d47 d46 d45 d44 d43 d42 d41 d40 see table 19-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan5 d57 d56 d55 d54 d53 d52 d51 d50 see table 19-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan6 d67 d66 d65 d64 d63 d62 d61 d60 see table 19-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan7 d77 d76 d75 d74 d73 d72 d71 d70 see table 19-6 undefined (n = 00 to 31)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 582 table 19-6. addresses of m_datanx (n = 00 to 31, x = 0 to 7) register name n m_datan0 m_datan1 m_datan2 m_datan3 m_datan4 m_datan5 m_datan6 m_datan7 00 xx3ff808h xx3ff809h xx3ff80ah xx3ff80bh xx3ff80ch xx3ff80dh xx3ff80eh xx3ff80fh 01 xx3ff828h xx3ff829h xx3ff82ah xx3ff82bh xx3ff82ch xx3ff82dh xx3ff82eh xx3ff82fh 02 xx3ff848h xx3ff849h xx3ff84ah xx3ff84bh xx3ff84ch xx3ff84dh xx3ff84eh xx3ff84fh 03 xx3ff868h xx3ff869h xx3ff86ah xx3ff86bh xx3ff86ch xx3ff86dh xx3ff86eh xx3ff86fh 04 xx3ff888h xx3ff889h xx3ff88ah xx3ff88bh xx3ff88ch xx3ff88dh xx3ff88eh xx3ff88fh 05 xx3ff8a8h xx3ff8a9h xx3ff8aah xx3ff8abh xx3ff8ach xx3ff8adh xx3ff8aeh xx3ff8afh 06 xx3ff8c8h xx3ff8c9h xx3ff8cah xx3ff8cbh xx3ff8cch xx3ff8cdh xx3ff8ceh xx3ff8cfh 07 xx3ff8e8h xx3ff8e9h xx3ff8eah xx3ff8ebh xx3ff8ech xx3ff8edh xx3ff8eeh xx3ff8efh 08 xx3ff908h xx3ff909h xx3ff90ah xx3ff90bh xx3ff90ch xx3ff90dh xx3ff90eh xx3ff90fh 09 xx3ff928h xx3ff929h xx3ff92ah xx3ff92bh xx3ff92ch xx3ff92dh xx3ff92eh xx3ff92fh 10 xx3ff948h xx3ff949h xx3ff94ah xx3ff94bh xx3ff94ch xx3ff94dh xx3ff94eh xx3ff94fh 11 xx3ff968h xx3ff969h xx3ff96ah xx3ff96bh xx3ff96ch xx3ff96dh xx3ff96eh xx3ff96fh 12 xx3ff988h xx3ff989h xx3ff98ah xx3ff98bh xx3ff98ch xx3ff98dh xx3ff98eh xx3ff98fh 13 xx3ff9a8h xx3ff9a9h xx3ff9aah xx3ff9abh xx3ff9ach xx3ff9adh xx3ff9aeh xx3ff9afh 14 xx3ff9c8h xx3ff9c9h xx3ff9cah xx3ff9cbh xx3ff9cch xx3ff9cdh xx3ff9ceh xx3ff9cfh 15 xx3ff9e8h xx3ff9e9h xx3ff9eah xx3ff9ebh xx3ff9ech xx3ff9edh xx3ff9eeh xx3ff9efh 16 xx3ffa08h xx3ffa09h xx3ffa0ah xx3ffa0bh xx3ffa0ch xx3ffa0dh xx3ffa0eh xx3ffa0fh 17 xx3ffa28h xx3ffa29h xx3ffa2ah xx3ffa2bh xx3ffa2ch xx3ffa2dh xx3ffa2eh xx3ffa2fh 18 xx3ffa48h xx3ffa49h xx3ffa4ah xx3ffa4bh xx3ffa4ch xx3ffa4dh xx3ffa4eh xx3ffa4fh 19 xx3ffa68h xx3ffa69h xx3ffa6ah xx3ffa6bh xx3ffa6ch xx3ffa6dh xx3ffa6eh xx3ffa6fh 20 xx3ffa88h xx3ffa89h xx3ffa8ah xx3ffa8bh xx3ffa8ch xx3ffa8dh xx3ffa8eh xx3ffa8fh 21 xx3ffaa8h xx3ffaa9h xx3ffaaah xx3ffaabh xx3ffaach xx3ffaadh xx3ffaaeh xx3ffaafh 22 xx3ffac8h xx3ffac9h xx3ffacah xx3ffacbh xx3ffacch xx3ffacdh xx3ffaceh xx3ffacfh 23 xx3ffae8h xx3ffae9h xx3ffaeah xx3ffaebh xx3ffaech xx3ffaedh xx3ffaeeh xx3ffaefh 24 xx3ffb08h xx3ffb09h xx3ffb0ah xx3ffb0bh xx3ffb0ch xx3ffb0dh xx3ffb0eh xx3ffb0fh 25 xx3ffb28h xx3ffb29h xx3ffb2ah xx3ffb2bh xx3ffb2ch xx3ffb2dh xx3ffb2eh xx3ffb2fh 26 xx3ffb48h xx3ffb49h xx3ffb4ah xx3ffb4bh xx3ffb4ch xx3ffb4dh xx3ffb4eh xx3ffb4fh 27 xx3ffb68h xx3ffb69h xx3ffb6ah xx3ffb6bh xx3ffb6ch xx3ffb6dh xx3ffb6eh xx3ffb6fh 28 xx3ffb88h xx3ffb89h xx3ffb8ah xx3ffb8bh xx3ffb8ch xx3ffb8dh xx3ffb8eh xx3ffb8fh 29 xx3ffba8h xx3ffba9h xx3ffbaah xx3ffbabh xx3ffbach xx3ffbadh xx3ffbaeh xx3ffbafh 30 xx3ffbc8h xx3ffbc9h xx3ffbcah xx3ffbcbh xx3ffbcch xx3ffbcdh xx3ffbceh xx3ffbcfh 31 xx3ffbe8h xx3ffbe9h xx3ffbeah xx3ffbebh xx3ffbech xx3ffbedh xx3ffbeeh xx3ffbefh
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 583 19.5.5 can message id registers l00 to l31 and h00 to h31 (m_idl00 to m_idl31 and m_idh00 to m_idh31) the m_idln and m_idhn registers are areas used to set identifiers (n = 00 to 31). these registers can be read/written in 16-bit units. when in standard format mode, any data can be stored in the following areas. id17 to id10: first byte of receive data note is stored. id9 to id12: second byte of receive data note is stored. id1, id0: third byte (higher two bits) of receive data note is stored. note see 19.5.4 can message data registers n0 to n7 (m_datan0 to m_datan7) . after reset: undefined r/w address: see table 19-7 1514131211109876543210 m_idhn (n = 00 to 31) ide 0 0 id 28 id 27 id 26 id 25 id 24 id 23 id 22 id 21 id 20 id 19 id 18 id 17 id 16 1514131211109876543210 m_idln (n = 00 to 31) id 15 id 14 id 13 id 12 id 11 id 10 id 9 id 8 id 7 id 6 id 5 id 4 id 3 id 2 id 1 id 0 ide specification of format setting mode 0 standard format mode (id28 to id18: 11 bits) 1 extended format mode (id28 to id0: 29 bits)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 584 table 19-7. addresses of m_idln and m_idhn (n = 00 to 31) register name address register name address m_idl00 xx3ff810h m_idl16 xx3ffa10h m_idh00 xx3ff812h m_idh16 xx3ffa12h m_idl01 xx3ff830h m_idl17 xx3ffa30h m_idh01 xx3ff832h m_idh17 xx3ffa32h m_idl02 xx3ff850h m_idl18 xx3ffa50h m_idh02 xx3ff852h m_idh18 xx3ffa52h m_idl03 xx3ff870h m_idl19 xx3ffa70h m_idh03 xx3ff872h m_idh19 xx3ffa72h m_idl04 xx3ff890h m_idl20 xx3ffa90h m_idh04 xx3ff892h m_idh20 xx3ffa92h m_idl05 xx3ff8b0h m_idl21 xx3ffab0h m_idh05 xx3ff8b2h m_idh21 xx3ffab2h m_idl06 xx3ff8d0h m_idl22 xx3ffad0h m_idh06 xx3ff8d2h m_idh22 xx3ffad2h m_idl07 xx3ff8f0h m_idl23 xx3ffaf0h m_idh07 xx3ff8f2h m_idh23 xx3ffaf2h m_idl08 xx3ff910h m_idl24 xx3ffb10h m_idh08 xx3ff912h m_idh24 xx3ffb12h m_idl09 xx3ff930h m_idl25 xx3ffb30h m_idh09 xx3ff932h m_idh25 xx3ffb32h m_idl10 xx3ff950h m_idl26 xx3ffb50h m_idh10 xx3ff952h m_idh26 xx3ffb52h m_idl11 xx3ff970h m_idl27 xx3ffb70h m_idh11 xx3ff972h m_idh27 xx3ffb72h m_idl12 xx3ff990h m_idl28 xx3ffb90h m_idh12 xx3ff992h m_idh28 xx3ffb92h m_idl13 xx3ff9b0h m_idl29 xx3ffbb0h m_idh13 xx3ff9b2h m_idh29 xx3ffbb2h m_idl14 xx3ff9d0h m_idl30 xx3ffbd0h m_idh14 xx3ff9d2h m_idh30 xx3ffbd2h m_idl15 xx3ff9f0h m_idl31 xx3ffbf0h m_idh15 xx3ff9f2h m_idh31 xx3ffbf2h
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 585 19.5.6 can message configuration registers 00 to 31 (m_conf00 to m_conf31) the m_confn register is used to specify the message buffer type and mask setting (n = 00 to 31). these registers can be read/written in 8-bit units. after reset: undefined r/w address: see table 19-8 76543210 m_confn 0 0 mt2 mt1 mt0 ma2 ma1 ma0 (n = 00 to 31) mt2 mt1 mt0 specification of message type and mask setting 0 0 0 transmit message 0 0 1 receive message (no mask setting) 0 1 0 receive message (mask 0 is set) 0 1 1 receive message (mask 1 is set) 1 0 0 receive message (mask 2 is set) 1 0 1 receive message (mask 3 is set) 1 1 0 setting prohibited 1 1 1 receive message (used in diagnostic processing mode) ? when bits mt2 to mt0 have been set as ? 111 ? , processing can be performed only when the fcan has been set to diagnostic processing mode. in such cases, all messages received are stored regardless of the following conditions. ? storage to other message buffer ? identifier type (standard frame or extended frame) ? data frame or remote frame ma2 ma1 ma0 link settings of message buffer and can module 0 0 0 message buffer is not used 0 0 1 used as can1 module ? s message buffer 0 1 0 used as can2 module ? s message buffer note other than above setting prohibited ? when bits ma2, ma1, and ma0 have been set to ? 000 ? , message buffer area is used for application ram or for event processing as a temporary buffer. ? in the unused message buffers, always set the ma2, ma1, and ma0 bits to 000. note pd703089y and 70f3089y only
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 586 table 19-8. addresses of m_confn (n = 00 to 31) register name address register name address m_conf00 xx3ff814h m_conf16 xx3ffa14h m_conf01 xx3ff834h m_conf17 xx3ffa34h m_conf02 xx3ff854h m_conf18 xx3ffa54h m_conf03 xx3ff874h m_conf19 xx3ffa74h m_conf04 xx3ff894h m_conf20 xx3ffa94h m_conf05 xx3ff8b4h m_conf21 xx3ffab4h m_conf06 xx3ff8d4h m_conf22 xx3ffad4h m_conf07 xx3ff8f4h m_conf23 xx3ffaf4h m_conf08 xx3ff914h m_conf24 xx3ffb14h m_conf09 xx3ff934h m_conf25 xx3ffb34h m_conf10 xx3ff954h m_conf26 xx3ffb54h m_conf11 xx3ff974h m_conf27 xx3ffb74h m_conf12 xx3ff994h m_conf28 xx3ffb94h m_conf13 xx3ff9b4h m_conf29 xx3ffbb4h m_conf14 xx3ff9d4h m_conf30 xx3ffbd4h m_conf15 xx3ff9f4h m_conf31 xx3ffbf4h
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 587 19.5.7 can message status registers 00 to 31 (m_stat00 to m_stat31) the m_statn register indicates the transmit/receive status information of each message buffer (n = 00 to 31). these registers are read-only, in 8-bit units. cautions 1. writing directly to m_statn register is not possible. use can status set/clear register n (sc_statn). 2. messages are transmitted only when the m_statn registers? trq and rdy bits have been set (1). after reset: undefined r address: see table 19-9 76543210 m_statn 0 0 0 0 rfu note dn trq rdy (n = 00 to 31) dn message update flag 0 no message was received after dn bit was cleared 1 at least one message was received after dn bit was cleared ? when the dn bit has been set (1) by the transmit message buffer, it indicates that the message buffer has received a remote frame. when this message is sent, the dn bit is automatically cleared (0). ? when a frame is again received in the message buffer for which the dn bit has been set (1), an overwrite condition occurs and the m_ctrln register ? s movr bit is set (1). trq transmit request flag 0 message transmission prohibited 1 message transmission enabled ? a transmit request is processed as a can module only when the rdy bit is set to 1. ? a remote frame is transmitted to the receive message buffer in which the trq bit is set to 1. rdy message ready flag 0 message is not ready 1 message is ready ? a receive operation is performed only for a message buffer in which the rdy bit is set to 1 during reception. ? a transmit operation is performed only for a message buffer in which the rdy bit is set to 1 and the trq bit is set to 1 during transmission. note rfu (reserved for future use) indicates a reserved bit. 0 or 1 is read from this bit regardless of the message buffer setting.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 588 table 19-9. addresses of m_statn (n = 00 to 31) register name address register name address m_stat00 xx3ff815h m_stat16 xx3ffa15h m_stat01 xx3ff835h m_stat17 xx3ffa35h m_stat02 xx3ff855h m_stat18 xx3ffa55h m_stat03 xx3ff875h m_stat19 xx3ffa75h m_stat04 xx3ff895h m_stat20 xx3ffa95h m_stat05 xx3ff8b5h m_stat21 xx3ffab5h m_stat06 xx3ff8d5h m_stat22 xx3ffad5h m_stat07 xx3ff8f5h m_stat23 xx3ffaf5h m_stat08 xx3ff915h m_stat24 xx3ffb15h m_stat09 xx3ff935h m_stat25 xx3ffb35h m_stat10 xx3ff955h m_stat26 xx3ffb55h m_stat11 xx3ff975h m_stat27 xx3ffb75h m_stat12 xx3ff995h m_stat28 xx3ffb95h m_stat13 xx3ff9b5h m_stat29 xx3ffbb5h m_stat14 xx3ff9d5h m_stat30 xx3ffbd5h m_stat15 xx3ff9f5h m_stat31 xx3ffbf5h
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 589 19.5.8 can status set/clear registers 00 to 31 (sc_stat00 to sc_stat31) the sc_statn register is used to set/clear the transmit/receive status information (n = 00 to 31). these registers are write-only, in 16-bit units. after reset: 0000h w address: see table 19-10 15 14 13 12 11 10 9 8 sc_statn 0 0 0 0 0 set dn set trq set rdy (n = 00 to 31) 76543210 0 0 0 0 0 clear dn clear trq clear rdy set dn clear dn message update flag setting 0 1 clear (clear (0) dn bit) 1 0 set (set (1) dn bit) other than above no change in dn bit value set trq clear trq transmit request flag setting 0 1 clear (clear (0) trq bit) 1 0 set (set (1) trq bit) other than above no change in trq bit value set rdy clear rdy message ready flag setting 0 1 clear (clear (0) rdy bit) 1 0 set (set (1) rdy bit) other than above no change in rdy bit value remark dn: bit 2 of can message status register n (m_statn) trq: bit 1 of can message status register n (m_statn) rdy: bit 0 of can message status register n (m_statn)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 590 table 19-10. addresses of sc_statn (n = 00 to 31) register name address register name address sc_stat00 xx3ff816h sc_stat16 xx3ffa16h sc_stat01 xx3ff836h sc_stat17 xx3ffa36h sc_stat02 xx3ff856h sc_stat18 xx3ffa56h sc_stat03 xx3ff876h sc_stat19 xx3ffa76h sc_stat04 xx3ff896h sc_stat20 xx3ffa96h sc_stat05 xx3ff8b6h sc_stat21 xx3ffab6h sc_stat06 xx3ff8d6h sc_stat22 xx3ffad6h sc_stat07 xx3ff8f6h sc_stat23 xx3ffaf6h sc_stat08 xx3ff916h sc_stat24 xx3ffb16h sc_stat09 xx3ff936h sc_stat25 xx3ffb36h sc_stat10 xx3ff956h sc_stat26 xx3ffb56h sc_stat11 xx3ff976h sc_stat27 xx3ffb76h sc_stat12 xx3ff996h sc_stat28 xx3ffb96h sc_stat13 xx3ff9b6h sc_stat29 xx3ffbb6h sc_stat14 xx3ff9d6h sc_stat30 xx3ffbd6h sc_stat15 xx3ff9f6h sc_stat31 xx3ffbf6h
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 591 19.5.9 can interrupt pending register (ccintp) the ccintp register is used to confirm the pending status of various interrupts. this register is read-only in 16-bit units. after reset: 0000h r address: xx3ffc04h 15 14 13 12 11 10 9 8 ccintp 0 intmac 0 0 0 0 0 0 76543210 0 0 can2err can2rec can2trx can1err can1rec can1trx intmac pending status of mac error note 1 interrupts (gint2, gint1) 0 not pending 1 pending can2err note 2 pending status of can2 access error interrupt (c2int6 to c2int2) 0 not pending 1 pending can2rec note 2 pending status of can2 receive completion interrupt (c2int1) 0 not pending 1 pending can2trx note 2 pending status of can2 transmit completion interrupt (c2int0) 0 not pending 1 pending can1err pending status of can1 access error interrupt (c1int6 to c1int2) 0 not pending 1 pending can1rec pending status of can1 receive completion interrupt (c1int1) 0 not pending 1 pending can1trx pending status of can1 transmit completion interrupt (c1int0) 0 not pending 1 pending
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 592 notes 1. mac (memory access control) errors are errors that are set only when an interrupt source has occurred for the can global interrupt pending register (cgintp). 2. pd703089y and 70f3089y only remark gint2, gint1: bits 2 and 1 of the can global interrupt pending register (cgintp) cnint6 to cnint0: bits 6 to 0 of the cann interrupt pending register (cnintp) (n=1, 2)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 593 19.5.10 can global interrupt pending register (cgintp) the cgintp register is used to confirm the pending status of mac access error interrupts. this register can be read/written in 8-bit or 16-bit units. cautions 1. when ?1? is written to a bit in the cgintp register, that bit is cleared (0). when ?0? is written to it, the bit?s value does not change. 2. an interrupt occurs when the corresponding interrupt request is enabled and when no interrupt pending bit has been set (1) for a new interrupt. the interrupt pending bit can be set (1) only when the interrupt enable bit has been set (1) by the can global interrupt enable register (cgie). however, the interrupt pending bit is not automatically cleared (0) just because the interrupt enable bit has been cleared (0). use software processing to clear the interrupt pending bit (0). whether the interrupt pending bit (1) is cleared (0) at the appropriate timing or not is controlled by an interrupt service routine. the earlier the interrupt service routine clears (0) the interrupt pending bit, the more quickly the interrupt occurs without losing any new interrupts of the same type. remark for details of interrupt sources generated at gint1 and gint2, see 19.15.2 interrupts that occur for global can interface . after reset: 0000h r/w address: xx3ffc20h 15 14 13 12 11 10 9 8 cgintp00000000 76543210 0000gint3gint2gint10 gint3 pending status of wakeup interrupt from can sleep mode with clock supply to fcan stopped 0 not pending 1 pending gint2 pending status of can module register note write access error interrupt when gom bit is 0 or pending status of temporary buffer write access error interrupt when gom bit is 1 0 not pending 1 pending gint1 pending status of invalid global macro shutdown occurrence interrupt or pending status of unusable memory address access error interrupt 0 not pending 1 pending note register with a name starting with ? cn ? (n = 1, 2) remark gom: bit 0 of can global status register (cgst)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 594 19.5.11 cann interrupt pending register (cnintp) the cnintp register is used to confirm the pending status of interrupts issued to the fcan. this register can be read/written in 8-bit or 16-bit units. the can2 interrupt pending register (c2intp) is valid only in models pd703089y and 70f3089y. cautions 1. when ?1? is written to a bit in the cnintp register, that bit is cleared (0). when ?0? is written to it, the bit?s value does not change. 2. an interrupt occurs when the corresponding interrupt request is enabled and when no interrupt pending bit has been set (1) for a new interrupt. the interrupt pending bit can be set (1) only when the interrupt ready bit has been set (1) by the cann interrupt enable register (cnie). however, the interrupt pending bit is not automatically cleared (0) just because the interrupt enable bit has been cleared (0). use software processing to clear the interrupt pending bit (0). whether the interrupt pending bit (1) is cleared (0) at the appropriate timing or not is controlled by an interrupt service routine. the earlier the interrupt service routine clears (0) the interrupt pending bit, the more quickly the interrupt occurs without losing any new interrupts of the same type. remark n = 1, 2
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 595 after reset: 0000h r/w addresses: c1intp: xx3ffc22h c2intp: xx3ffc24h 15 14 13 12 11 10 9 8 cnintp00000000 (n = 1, 2)76543210 0 cnint6 cnint5 cnint4 cnint3 cnint2 cnint1 cnint0 cnint6 pending status of can module error interrupt 0 not pending 1 pending cnint5 pending status of can bus error interrupt 0 not pending 1 pending cnint4 pending status of wakeup interrupt (from can sleep mode) 0 not pending 1 pending cnint3 pending status of can receive error passive status interrupt 0 not pending 1 pending cnint2 pending status of can transmit error passive or bus off status interrupt 0 not pending 1 pending cnint1 pending status of can receive completion interrupt 0 not pending 1 pending cnint0 pending status of can transmit completion interrupt 0 not pending 1 pending
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 596 19.5.12 can stop register (cstop) the cstop register controls clock supply to the entire can system. this register can be read/written in 16-bit units. cautions 1. be sure to set the cstp bit (1) if the fcan function will not be used. 2. when the cstp bit is set (1), access to fcan registers other than the cstop register is prohibited. access to fcan (other than the cstop register) is possible only when the cstp bit is cleared (0). if accessed while the cstp bit is set (1), undefined value is read and writing is not possible. 3. when the cstp bit is set (1), wakeup from the can sleep mode (sleep bit of cann control register (cnctrl) = 1) can be performed in accordance with a change on the can bus. 4. if the can main clock (f mem1 ) is stopped in other than can sleep mode, first set the can module to initial mode (init bit of cnctrl register = 1), clear (0) the gom bit of the cgst register, and then set (1) the cstp bit. after reset: 0000h r/w address: xx3ffc00h 1514131211109876543210 cstop cstp 000000000000000 cstp controls clock supply to fcan 0 fcan in operation (supplies clock to fcan blo cks) 1 fcan is stopped (access to fcan blo cks is not possible)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 597 19.5.13 can global status register (cgst) the cgst register indicates global status information. this register can be read/written in 16-bit units. cautions 1. both bitwise writing and direct writing to the cgst register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 19.6 cautions regarding bit set/clear function. 2. when writing to the cgst register, set or clear bits according to the register configuration shown in part (b) write of the following figure. (1/2) after reset: 0000h r/w address: xx3ffc10h (a) read 15 14 13 12 11 10 9 8 cgst00000000 76543210 merr 0 0 0 efsd tsm 0 gom (b) write151413121110 9 8 cgst 0 0 0 0 set efsd set tsm 0 set gom 76543210 clear merr 000 clear efsd clear tsm 0 clear gom (a) read merr mac error status flag 0 error does not occur after the merr bit has been cleared 1 error occurs at least once after merr bit has been cleared ? mac errors occur under the following conditions. ? when invalid address is accessed ? when access prohibited by mac is performed ? when the gom bit is cleared (0) before the init bit of the cnctrl register is set (1) efsd shutdown request 0 shutdown prohibited 1 shutdown enabled ? be sure to set the efsd bit (1) before clearing the gom bit (0) (must be accessed twice). the efsd bit will be cleared (0) automatically when the cgst register is accessed again. tsm operation status of time stamp counter note 0 time stamp counter is stopped 1 time stamp counter is operating note refer to 19.5.16 can time stamp count register (cgtsc) .
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 598 (2/2) (a) read gom status of global operation mode 0 can module is reset and access to can module register note 1 is prohibited 1 can module operation is enabled and access to can module register note 1 is enabled ? the gom bit controls the method the memory is accessed by the mac and can module operation status. ? when gom bit = 0 ? all can modules are reset ? access to can module register disabled (if accessed, a mac error interrupt occurs) note 2 ? access to temporary buffer enabled ? access to message buffer area enabled ? when gom bit = 1 ? access to can module register enabled note 3 ? access to temporary buffer prohibited (if accessed, a mac error interrupt occurs) ? access to message buffer area enabled ? the gom bit is cleared (0) only when all the can modules are in the initial mode (the init bit of the cnctrl register is 1). even if the gom bit is cleared when there is a can module not in the initial mode, the gom bit remains set (1). ? to clear (0) the gom bit, first set (1) the init bit of the cnctrl register, and then set (1) the efsd bit. do not manipulate the gom bit and efsd bit simultaneously. notes 1. register with a name starting with ? cn ? (n = 1, 2) 2. the cgcs register can be accessed. write accessing the cgmss register is prohibited. if the cgmss register is write- accessed, the wrong search result is reflected in the cgmsr register. 3. write accessing the cgcs register is prohibited. write accessing the cgmss register is possible.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 599 (b) write set efsd clear efsd efsd bit setting 0 1 efsd bit cleared (0) 1 0 efsd bit set (1) other than above no change in efsd bit ? s value set tsm clear tsm tsm bit setting 0 1 tsm bit cleared (0) 1 0 tsm bit set (1) other than above no change in tsm bit ? s value set gom clear gom gom bit setting 0 1 gom bit cleared (0) 1 0 gom bit set (1) other than above no change in gom bit ? s value clear merr merr bit setting 0 no change in merr bit ? s value 1 merr bit cleared (1)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 600 19.5.14 can global interrupt enable register (cgie) the cgie register is used to issue interrupt requests for global interrupts. this register can be read/written in 16-bit units. cautions 1. both bitwise writing and direct writing to the cgie register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 19.6 cautions regarding bit set/clear function. 2. when writing to the cgie register, set or clear bits according to the register configuration shown in part (b) write of the following figure. after reset: 0000h r/w address: xx3ffc12h (a) read 15 14 13 12 11 10 9 8 cgie00000000 76543210 00000g_ie2g_ie10 (b) write151413121110 9 8 cgie 0 0 0 0 0 set g_ie2 set g_ie1 0 76543210 0000 0 clear g_ie2 clear g_ie1 0 (a) read g_ie2 write access error interrupt enable status for can module register note when gom bit is 0 or write access error interrupt enable status for temporary buffer when the gom bit is 1 0 interrupt disabled 1 interrupt enabled g_ie1 invalid global macro shutdown occurrence interrupt enable status or unusable memory address access error interrupt enable status 0 interrupt disabled 1 interrupt enabled note register with a name starting with ? cn ? (n = 1, 2) (b) write set g_ien clear g_ien setting of g_ien bit 0 1 clear (0) g_ien bit 1 0 set (1) g_ien bit other than above no change remarks 1. n = 1, 2 2. gom: bit 0 of the can global status register (cgst)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 601 19.5.15 can main clock select register (cgcs) the cgcs register is used to select the can main clock. this register can be read/written in 16-bit units. caution when the gom bit of the cgst register is 1, write accessing the cgcs register is prohibited. after reset: 7f05h r/w address: xx3ffc14h 15 14 13 12 11 10 9 8 cgcs cgts7 cgts6 cgts5 cgts4 cgts3 cgts2 cgts1 cgts0 76543210 gtcs1 gtcs0 0 0 note 1 mcp3 mcp2 mcp1 mcp0 n cgts 7 cgts 6 cgts 5 cgts 4 cgts 3 cgts 2 cgts 1 cgts 0 system timer prescaler selection f gts = f gts1 /(n + 1) 000000000f gts = f gts1 /1 100000001f gts = f gts1 /2 :f gts = f gts1 /(n + 1) 12701111111f gts = f gts1 /128 (after reset) :f gts = f gts1 /(n + 1) 25411111110f gts = f gts1 /255 25511111111f gts = f gts1 /256 the global timer system clock (f gts ) is the source clock for the time stamp counter note 2 that is used for the time stamp function. gtcs1 gtcs0 global timer clock selection (f gts1 ) 00f mem /2 01f mem /4 10f mem /8 11f mem /16 n mcp3 mcp2 mcp1 mcp0 selection of clock to memory access controller (f mem ) 00000f mem1 10001f mem1 /2 20010f mem1 /3 :f mem1 /(n+1) 141110f mem1 /15 151111f mem1 /16 once the values of the mcp3 to mcp0 bits are set after reset is released, do not change these values. notes 1. when writing to this bit, always set it to 0. 2. see 19.5.16 can time stamp count register (cgtsc) .
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 602 figure 19-2. fcan clocks cgts7 cgts6 cgts5 cgts4 cgts3 cgts2 cgts1 cgts0 gtcs1 gtcs0 mcp 3 mcp2 prescaler data bit time cann bit rate prescaler register (cnbrp) can main clock select register (cgcs) global timer clock prescaler baud rate generator global timer system clock cann synchronization control register (cnsync) time stamp counter mcp1 mcp0 brp0 brp1 brp2 brp3 brp4 brp5 btype brp6 note brp7 note f mem1 f mem f gts1 f btl f gts note only when the tlm bit of the cann bit rate prescaler register (cnbrp) is 1. remarks 1. f mem1 = f xx = clock supply to can 2. n = 1, 2
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 603 19.5.16 can time stamp count register (cgtsc) the cgtsc register indicates the contents of the time stamp counter. this register can be read at any time. this register can be written to only when clearing bits. the clear function writes 0 to all bits in the cgtsc register. this register is read-only, in 16-bit units. after reset: 0000h r address: xx3ffc18h 15 14 13 12 11 10 9 8 cgtsc tsc15 tsc14 tsc13 tsc12 tsc11 tsc10 tsc9 tsc8 76543210 tsc7 tsc6 tsc5 tsc4 tsc3 tsc2 tsc1 tsc0
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 604 19.5.17 can message search start/result register (cgmss/cgmsr) the cgmss/cgmsr register indicates the message search start/result status. messages in the message buffer that match the specified search criteria can be searched quickly. these registers can be read/written in 16-bit units. cautions 1. execute the search by writing only once. 2. always set the smno2 bit of the cgmss register to 0. if 1 is set, operation is not guaranteed. (1/2) after reset: 0000h r/w address: xx3ffc1ah (a) read 15 14 13 12 11 10 9 8 cgmsr000000mmam 76543210 0 0 0 mfnd4 mfnd3 mfnd2 mfnd1 mfnd0 (b) write151413121110 9 8 cgmss cide 0 ctrq cmsk cdn smno2 smno1 smno0 76543210 0 0 0 strt4 strt3 strt2 strt1 strt0 (a) read mm confirmation of multiple hits from message search 0 no messages or only one message meets the search criteria 1 several messages meet the search criteria if several message buffers that meet the search criteria are detected, the mm bit is set. am confirmation of hits from message search 0 no messages meet the search criteria 1 at least one message meets the search criteria mfnd4 to mfnd0 searched message number this indicates the number (0 to 31) of the searched message. ? when multiple message buffer numbers match as a result of a search (mm = 1), the return value of bits mfnd4 to mfnd0 is the lowest message buffer number. when no message buffer numbers match (am = 0), the return value of bits mfnd4 to mfnd0 is ? message buffer number ? 1 ? . (b) write cide message identifier (id) format flag check 0 message identifier format flag not checked 1 message with standard format identifier checked
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 605 (2/2) (b) write ctrq transmit request and message ready flag check 0 transmit request and message ready flags not checked 1 transmit request and message ready flags checked cmsk message check 0 checked regardless of mask setting 1 only unmasked messages checked cdn status check of m_statn register ? s dn flag (n = 00 to 31) 0 status of m_statn register ? s dn flag not checked 1 status of m_statn register ? s dn flag checked smno2 smno1 smno0 search module setting 0 0 0 no search module setting 0 0 1 can module 1 is set as the searched target 0 1 0 can module 2 is set as the searched target other than above setting prohibited strtn message search start position (n = 0 to 4) 0 to 31 message search start position (message number) ? search starts from the message number defined by bits strt4 to strt0. search continues until it reaches the message buffer having the highest number among the usable message buffers. if the search results include several message buffer numbers among the matching messages, the message buffer with the lowest message buffer number is selected. to fetch the next message buffer number without changing the search criteria, ? (mfnd4 to mfnd0) + 1 ? must be set as the values of bits strt4 to strt0.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 606 19.5.18 cann address mask a registers l and h (cnmaskla and cnmaskha) the cnmaskla and cnmaskha registers are used to extend the number of receivable messages by masking part of the message ? s identifier (id) and then ignoring the masked parts (a = 0 to 3, n = 1, 2). these registers can be read/written in 16-bit units. the c2maskla and c2maskha registers are valid only in models pd703089y and 70f3089y. after reset: undefined r/w address: see table 19-11 15 14 13 12 11 10 9 8 cnmaskha cmide 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 (a = 0 to 3, n = 1, 2) 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 15 14 13 12 11 10 9 8 cnmaskla cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 (a = 0 to 3, n = 1, 2) 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 cmide mask setting for identifier (id) format 0 id format (standard or extended) checked 1 id format (standard or extended) not checked when the cmide bit is set (1), the higher 11 bits of id are compared. the receive message and id format stored in a message buffer are not compared. cmid0 to cmid28 mask setting for identifier (id) bits 0 id bit in message buffer linked to bits cmid28 to cmid0 compared with received id bit. 1 id bit in message buffer linked to bits cmid28 to cmid0 not compared with received id bit (i.e., masked). a mask is always defined by an id length of 29 bits. when a mask is assigned to the standard id, always set the cmid17 to cmid0 bits to 1. the received id is masked only by cmid28 to cmid18. the same mask can be used for standard and extended ids.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 607 table 19-11. addresses of cnmaskla and cnmaskha (a = 0 to 3, n = 1, 2) register name address register name address c1maskl0 xx3ffc40h c2maskl0 xx3ffc80h c1maskh0 xx3ffc42h c2maskh0 xx3ffc82h c1maskl1 xx3ffc44h c2maskl1 xx3ffc84h c1maskh1 xx3ffc46h c2maskh1 xx3ffc86h c1maskl2 xx3ffc48h c2maskl2 xx3ffc88h c1maskh2 xx3ffc4ah c2maskh2 xx3ffc8ah c1maskl3 xx3ffc4ch c2maskl3 xx3ffc8ch c1maskh3 xx3ffc4eh c2maskh3 xx3ffc8eh
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 608 19.5.19 cann control register (cnctrl) the cnctrl register is used to control the operation of the can module. this register can be read/written in 16-bit units. the c2ctrl register is valid only in models pd703089y and 70f3089y. cautions 1. both bitwise writing and direct writing to the cnctrl register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 19.6 cautions regarding bit set/clear function. 2. when writing to the cnctrl register, set or clear bits according to the register configuration shown in part (b) write of the following figure. 3. when canceling can stop mode, can sleep mode must be cancelled at the same time. (1/4) after reset: 0101h r/w addresses: c1ctrl: xx3ffc50h c2ctrl: xx3ffc90h (a) read 15 14 13 12 11 10 9 8 cnctrl tecs1 tecs0 recs1 recs0 boff tstat rstat istat (n = 1, 2)76543210 0 dlevr dlevt ovm tmr stop sleep init (b) write151413121110 9 8 cnctrl 0 set dlevr set dlevt set ovm set tmr set stop set sleep set init (n = 1, 2)76543210 0 clear dlevr clear dlevt clear ovm clear tmr clear stop clear sleep clear init (a) read tecs1 tecs0 status of transmit error counter 0 0 transmit error counter value < 96 0 1 transmit error counter value = 96 to 127 (warning level) 1 0 not used 1 1 transmit error counter value 128 (error passive) recs1 recs0 status of receive error counter 0 0 receive error counter value < 96 0 1 receive error counter value = 96 to 127 (warning level) 1 0 not used 1 1 receive error counter value 128 (error passive) boff bus off status flag 0 transmit error counter value < 256 (not bus off status) 1 transmit error counter value 256 (bus off status)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 609 (2/4) (a) read tstat transmit status flag 0 transmit stop status 1 transmit operating status rstat receive status flag 0 receive stop status 1 receive operating status istat initialization status flag 0 normal operating status 1 fcan is stopped and initialized ? the istat bit is set (1) when the can protocol layer acknowledges the setting of the init bit. the istat bit is automatically cleared (0) after the init bit is cleared (0). ? ? recessive ? is output via the cantxn pin in initialization mode. ? the cnsync and cnbrp registers can be written only in initialization mode. ? when shifting from the initialization status to the normal operating status, the error counter (see 19.5.22 cann error count register (cnerc) ) is cleared (0) and the error status (tecs1, tecs0, recs1, or recs0 bit) is reset. dlevr dominant level control bit for receive pin 0 a low level to a receive pin is acknowledged as dominant 1 a high level to a receive pin is acknowledged as dominant dlevt dominant level control bit for transmit pin 0 a low level is transmitted from transmit pin as dominant 1 a high level is transmitted from transmit pin as dominant ovm overwrite mode control bit 0 new messages stored in message buffer in which dn bit of m_stata register is set (a = 00 to 31) 1 new messages in message buffer in which dn bit is set (a = 00 to 31) discarded tmr time stamp control bit for reception 0 when the sof is detected on the can bus, the value of the time stamp counter is captured. 1 when the eof is detected on the can bus (a valid message is confirmed), the value of the time stamp counter is captured.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 610 (3/4) (a) read stop can stop mode control bit 0 normal can sleep mode 1 can stop mode (change in can bus does not cause wakeup) ? can stop mode can be selected only when the can module has been set to can sleep mode, i.e., when the sleep bit has been set (1). ? can stop mode can be canceled only by the cpu by clearing the stop bit (0). sleep can sleep mode control bit 0 normal operating mode 1 can sleep mode (change in can bus causes wakeup) ? can sleep mode can be set only when the can bus is in the idle state. ? can sleep mode is canceled under the following conditions. ? when the cpu has cleared the sleep bit (0) ? when the can bus changes (this occurs only when can stop mode has not been set) ? the wake bit note is set (1) only when can sleep mode is cancelled by the change of the can bus, and an error interrupt occurs. ? to check the settings of the sleep bit, read the cnctrl register. init initialization request bit 0 normal operation mode 1 initialization mode ? be sure to confirm that the can module has entered the initialization mode using the istat bit (istat bit = 1) after setting the init bit (1). ? if the init bit is set (1) when the can module is in the bus off status (boff bit = 1), the can module enters initialization mode (istat bit = 1) immediately. note see 19.5.20 cann definition register (cndef) .
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 611 (4/4) (b) write set dlevr clear dlevr dlevr bit setting 0 1 dlevr bit cleared (0) 1 0 dlevr bit set (1) other than above dlevr bit not changed set dlevt clear dlevt dlevt bit setting 0 1 dlevt bit cleared (0) 1 0 dlevt bit set (1) other than above dlevt bit not changed set ovm clear ovm ovm bit setting 0 1 ovm bit cleared (0) 1 0 ovm bit set (1) other than above ovm bit not changed set tmr clear tmr tmr bit setting 0 1 tmr bit cleared (0) 1 0 tmr bit set (1) other than above tmr bit not changed set stop clear stop stop bit setting 0 1 stop bit cleared (0) 1 0 stop bit set (1) other than above stop bit not changed set sleep clear sleep sleep bit setting 0 1 sleep bit cleared (0) 1 0 sleep bit set (1) other than above sleep bit not changed set init clear init init bit setting 0 1 init bit cleared (0) 1 0 init bit set (1) other than above init bit not changed
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 612 19.5.20 cann definition register (cndef) the cndef register is used to define the operation of the can module. this register can be read/written in 16-bit units. the c2def register is valid only in models pd703089y and 70f3089y. cautions 1. both bitwise writing and direct writing to the cndef register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 19.6 cautions regarding bit set/clear function. 2. when writing to the cndef register, set or clear bits according to the register configuration shown in part (b) write of the following figure. (1/4) after reset: 0000h r/w addresses: c1def: xx3ffc52h c2def: xx3ffc92h (a) read 15 14 13 12 11 10 9 8 cndef00000000 (n = 1, 2)76543210 dgm mom ssht pbb berr valid wake ovr (b) write151413121110 9 8 cndef set dgm set mom set ssht set pbb 0 0 0 0 (n = 1, 2)76543210 clear dgm clear mom clear ssht clear pbb clear berr clear valid clear wake clear ovr (a) read dgm specification of diagnostic processing mode 0 valid messages are stored in the message buffer used for diagnostic processing mode note (only when receiving) 1 valid messages are stored in the same way as in normal operating mode (only when receiving) ? the diagnostic processing mode (mom bit = 1) is used for can baud rate detection and for diagnostic purposes. when this mode is set, the following operations are performed. ? when the valid bit = 1, it indicates that the current receive operation is valid. ? setting the dgm bit confirms whether valid data has been stored in the message buffer used for diagnostic processing mode, or stored in the same way as in normal operating mode. note bits 5 to 3 (mt2 to mt0) of can message configuration register a (m_confa) are set as ? 111 ? (a = 00 to 31).
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 613 (2/4) (a) read mom specification of can module ? s operating mode 0 normal operating mode 1 diagnostic processing mode ? when in diagnostic processing mode (mom bit = 1), the cnbrp register can be accessed only when the can module has been set to initialization mode (i.e., when the cnctrl register ? s istat bit = init bit = 1). when the can module is operating (i.e., when the cnctrl register ? s istat bit = 0) the cnbrp register cannot be used, and the cann bus diagnostic information register (cndinf) register can be used instead. ? the can protocol layer does not sent ack, error frame, or transmit messages, nor does it operate an error counter. the internal transmit output is fed back to the internal input due to auto baud rate detection. ssht specification of single shot mode 0 normal operating mode 1 single shot mode ? in single shot mode, the can module can transmit a message only once. the m_stata (a = 00 to 31) register ? s trq bit is then cleared (0) regardless of whether or not there are any pending normal transmit operations. also, if a bus error has occurred due to a transmission, it is processed as a transmission error. ? in single shot mode, even if the can lost in the arbitration phase, it is handled as a completed message transmission. in this mode, the berr bit is set (1) but the error counter (see 19.5.22 cann error count register (cnerc) ) value does not change since there are no can bus errors. ? in single shot mode, even when transmission is stopped due to error detection or a loss in the arbitration phase, the transmission completion interrupt occurs. ? during the time when the can module is active, normal operating mode and single shot mode can be switched without causing any errors on the can bus. pbb specification of priority control for transmission 0 identifier (id) based priority control 1 message number based priority control ? ordinarily, priority for transmission is defined based on message ids, but when the pbb bit has been set (1) priority becomes based instead on the position of messages, so that messages with lower message numbers have higher priority. berr can bus error status 0 can bus error was not detected 1 can bus error was detected at least once after bit was cleared valid valid message detection status 0 valid message was not detected 1 valid message was detected at least once after bit was cleared
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 614 (3/4) (a) read wake can sleep mode cancellation status 0 normal operation 1 cancel can sleep mode ? the wake bit is set (1) only when the can sleep mode is released due to a change of can bus and an error interrupt occurs. ? while the wake bit is set (1), the error interrupt signal holds the active status. therefore, always clear (0) the wake bit after recognition. ovr overrun error status 0 normal operation 1 overwrite occurred during ram access ? when an overrun error has occurred, the ovr bit is set (1) and an error interrupt occurs at the same time. the source of the overrun error may be that the ram access clock is slower than the selected can baud rate.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 615 (4/4) (b) write set dgm clear dgm dgm bit setting 0 1 dgm bit cleared (0) 1 0 dgm bit set (1) other than above dgm bit not changed set mom clear mom mom bit setting 0 1 mom bit cleared (0) 1 0 mom bit set (1) other than above mom bit not changed set ssht clear ssht ssht bit setting 0 1 ssht bit cleared (0) 1 0 ssht bit set (1) other than above ssht bit not changed set pbb clear pbb pbb bit setting 0 1 pbb bit cleared (0) 1 0 pbb bit set (1) other than above pbb bit not changed clear berr berr bit setting 1 berr bit cleared (0) 0 berr bit not changed clear valid valid bit setting 1 valid bit cleared (0) 0 valid bit not changed clear wake wake bit setting 1 wake bit cleared (0) 0 wake bit not changed clear ovr ovr bit setting 1 ovr bit cleared (0) 0 ovr bit not changed
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 616 19.5.21 cann information register (cnlast) the cnlast register indicates the cann module ? s error information and the number of the message buffer received last. this register is read-only, in 16-bit units. the c2last register is valid only in models pd703089y and 70f3089y. after reset: 00ffh r addresses: c1last: xx3ffc54h c2last: xx3ffc94h 15 14 13 12 11 10 9 8 cnlast 0 0 0 0 lerr3 lerr2 lerr1 lerr0 (n = 1, 2)76543210 lrec7 lrec6 lrec5 lrec4 lrec3 lrec2 lrec1 lrec0 lerr3 lerr2 lerr1 lerr0 last error information 0 0 0 0 error not detected 0001bit error 0010stuff error 0 0 1 1 crc error 0 1 0 0 form error 0101ack error 0 1 1 0 arbitration lost (only during single shot mode) (cndef: ssht = 1) 0 1 1 1 can overwrite error 1 0 0 0 wakeup from can bus other than above setting prohibited ? since bits lerr3 to lerr0 cannot be cleared, the current status is retained until the next error occurs. lrec7 to lrec0 number of last receive message 0 to 31 message number of message last received 32 to 255 not used
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 617 19.5.22 cann error count register (cnerc) the cnerc register indicates the count values of the transmission/reception error counters. this register is read-only in 16-bit units. the c2erc register is valid only in models pd703089y and 70f3089y. after reset: 0000h r addresses: c1erc: xx3ffc56h c2erc: xx3ffc96h 15 14 13 12 11 10 9 8 cnerc rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 (n = 1, 2)76543210 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 rec7 to rec0 reception error counter 0 to 255 number of reception error counts ? this reflects the current status of the reception error counter. ? the count value is defined by the can protocol. tec7 to tec0 transmission error counter 0 to 255 number of transmission error counts ? this reflects the current status of the transmission error counter. ? the number of counts is defined by the can protocol.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 618 19.5.23 cann interrupt enable register (cnie) the cnie register is used to enable/disable the can module ? s interrupts. this register can be read/written in 16-bit units. the c2ie register is valid only in models pd703089y and 70f3089y. cautions 1. both bitwise writing and direct writing to the cnie register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 19.6 cautions regarding bit set/clear function. 2. when writing to the cnie register, set or clear bits according to the register configuration shown in part (b) write of the following figure. (1/3) after reset: 0000h r/w addresses: c1ie: xx3ffc58h c2ie: xx3ffc98h (a) read 15 14 13 12 11 10 9 8 cnie00000000 (n = 1, 2)76543210 0 e_int6 e_int5 e_int4 e_int3 e_int2 e_int1 e_int0 (b) write151413121110 9 8 cnie 0 set e_int6 set e_int5 set e_int4 set e_int3 set e_int2 set e_int1 set e_int0 (n = 1, 2)76543210 0 clear e_int6 clear e_int5 clear e_int4 clear e_int3 clear e_int2 clear e_int1 clear e_int0 (a) read e_int6 can module error interrupt enable flag 0 interrupt disabled 1 interrupt enabled e_int5 can bus error interrupt enable flag 0 interrupt disabled 1 interrupt enabled e_int4 wake up from can sleep mode interrupt enable flag 0 interrupt disabled 1 interrupt enabled e_int3 can receive error passive interrupt enable flag 0 interrupt disabled 1 interrupt enabled
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 619 (2/3) (a) read e_int2 can transmit error passive or bus off interrupt enable flag 0 interrupt disabled 1 interrupt enabled e_int1 can receive completion interrupt enable flag 0 interrupt disabled 1 interrupt enabled ? when ie bit of the m_ctrln register is 1, a reception completion interrupt occurs regardless of the setting of the e_int1 bit if the transmit message buffer receives a remote frame while the auto response function is not set (rmde0 bit of the m_ctrln register = 0). e_int0 can transmit completion interrupt enable flag 0 interrupt disabled 1 interrupt enabled
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 620 (3/3) (b) write set e_int6 clear e_int6 e_int6 bit setting 0 1 e_int6 interrupt cleared (0) 1 0 e_int6 interrupt set (1) other than above e_int6 interrupt not changed set e_int5 clear e_int5 e_int5 bit setting 0 1 e_int5 interrupt cleared (0) 1 0 e_int5 interrupt set (1) other than above e_int5 interrupt not changed set e_int4 clear e_int4 e_int4 bit setting 0 1 e_int4 interrupt cleared (0) 1 0 e_int4 interrupt set (1) other than above e_int4 interrupt not changed set e_int3 clear e_int3 e_int3 bit setting 0 1 e_int3 interrupt cleared (0) 1 0 e_int3 interrupt set (1) other than above e_int3 interrupt not changed set e_int2 clear e_int2 e_int2 bit setting 0 1 e_int2 interrupt cleared (0) 1 0 e_int2 interrupt set (1) other than above e_int2 interrupt not changed set e_int1 clear e_int1 e_int1 bit setting 0 1 e_int1 interrupt cleared (0) 1 0 e_int1 interrupt set (1) other than above e_int1 interrupt not changed set e_int0 clear e_int0 e_int0 bit setting 0 1 e_int0 interrupt cleared (0) 1 0 e_int0 interrupt set (1) other than above e_int0 interrupt not changed
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 621 19.5.24 cann bus active register (cnba) the cnba register indicates frame information output via the can bus. this register is read-only, in 16-bit units. the c2ba register is valid only in models pd703089y and 70f3089y. after reset: 00ffh r addresses: c1ba: xx3ffc5ah c2ba: xx3ffc9ah 15 14 13 12 11 10 9 8 cnba 0 0 0 cact4 cact3 cact2 cact1 cact0 (n = 1, 2)76543210 tmno7 tmno6 tmno5 tmno4 tmno3 tmno2 tmno1 tmno0 cact4 cact3 cact2 cact1 cact0 can module status 0 0 0 0 0 reset state 0 0 0 0 1 bus idle wait 0 0 0 1 0 bus idle state 0 0 0 1 1 start of frame 0 0 1 0 0 standard identifier area 0 0 1 0 1 data length code area 0 0 1 1 0 data field area 0 0 1 1 1 crc field area 0 1 0 0 0 crc delimiter 0 1 0 0 1 ack slot 0 1 0 1 0 ack delimiter 0 1 0 1 1 end of frame area 0 1 1 0 0 intermission state 0 1 1 0 1 suspend transmission 0 1 1 1 0 error frame 0 1 1 1 1 error delimiter wait 1 0 0 0 0 error delimiter 10001bus off error 1 0 0 1 0 extended identifier area other than above setting prohibited tmno7 to tmno0 transmission message counter 0 to 31 message number of message awaiting transmission or being transmitted 32 to 254 not used 255 no messages awaiting transmission or being transmitted
chapter 19 fcan controller (v850/sc3) user?s manual u15109ej3v0ud 622 19.5.25 cann bit rate prescaler register (cnbrp) the cnbrp register is used to set the transmission baud rate for the can module. use the cnbrp register to select the can protocol layer basic system clock (f btl ). the baud rate is determined by the value set to the cnsync register. while in normal operating mode (cndef register?s mom bit = 0), writing to the cnbrp register is enabled only when the initialization mode has been set (cnctrl register?s init bit = 1). this register can be read/written in 16-bit units. the c2brp register is valid only in models pd703089y and 70f3089y. caution while in diagnostic processing mode (cndef register?s mom bit = 1), the cnbrp register can be accessed only when the initialization mode has been set.
chapter 19 fcan controller (v850/sc3) user?s manual u15109ej3v0ud 623 (1/2) after reset: 0000h r/w addresses: c1brp: xx3ffc5ch c2brp: xx3ffc9ch (a) when tlm = 0 15 14 13 12 11 10 9 8 cnbrptlm0000000 (n = 1, 2)76543210 0 btype brp5 brp4 brp3 brp2 brp1 brp0 (b) when tlm = 1 15 14 13 12 11 10 9 8 cnbrp tlm 0 0 0 0 0 0 btype (n = 1, 2)76543210 brp7 brp6 brp5 brp4 brp3 brp2 brp1 brp0 (a) when tlm = 0 tlm transfer layer mode specification 0 6-bit prescaler mode btype can bus type specification 0 low speed ( 125 kbps) 1 high speed (> 125 kbps) a brp5 brp4 brp3 brp2 brp1 brp0 can protocol layer basic system clock (f btl ) 0000000f mem /2 1000001f mem /4 2000010f mem /6 3000011f mem /8 :f mem /{(a + 1) 2} 60111100f mem /122 61111101f mem /124 62111110f mem /126 63111111f mem /128 remark f btl = f mem /{(a + 1) 2}: can protocol layer basic system clock a = 0 to 63 (set by bits brp5 to brp0) f mem = can base clock
chapter 19 fcan controller (v850/sc3) user?s manual u15109ej3v0ud 624 (2/2) (b) when tlm = 1 tlm transfer layer mode specification 1 8-bit prescaler mode btype can bus type specification 0 low speed ( 125 kbps) 1 high speed (> 125 kbps) a brp7 brp6 brp5 brp4 brp3 brp2 brp1 brp0 can protocol layer basic system clock (f btl ) 000000000setting prohibited 100000001f mem /2 200000010f mem /3 300000011f mem /4 :f mem /(a + 1) 25211111100f mem /253 25311111101f mem /254 25411111110f mem /255 25511111111f mem /256 remark f btl = f mem /(a + 1): can protocol layer basic system clock a = 0 to 255 (set by bits brp7 to brp0) f mem = can base clock
chapter 19 fcan controller (v850/sc3) user?s manual u15109ej3v0ud 625 19.5.26 cann bus diagnostic information register (cndinf) the cndinf register indicates all the can bus bits, including the stuff bits and delimiters. this information is used only for diagnostic purposes. this register is read-only in 16-bit units. the c2dinf register is valid only in models pd703089y and 70f3089y. cautions 1. the cndinf register can be accessed only while in diagnostic processing mode (cndef register?s mom bit = 1) and in normal operating mode (cnctrl register?s init bit = 0). 2. storage of the last 8 bits is automatically stopped if an error or a valid message (ack delimiter) is detected on the can bus. storage is automatically reset each time when sof is detected on the can bus. after reset: 0000h r addresses: c1dinf: xx3ffc5ch c2dinf: xx3ffc9ch 15 14 13 12 11 10 9 8 cndinf dinf15 dinf14 dinf13 dinf12 dinf11 dinf10 dinf9 dinf8 (n = 1, 2)76543210 dinf7 dinf6 dinf5 dinf4 dinf3 dinf2 dinf1 dinf0 dinfa cann bus diagnostic information dinf15 to dinf8 no. of bits starting from sof dinf7 to dinf0 information from last 8 bits
chapter 19 fcan controller (v850/sc3) user?s manual u15109ej3v0ud 626 19.5.27 cann synchronization control register (cnsync) the cnsync register controls the data bit time for transmission speed. this register can be read/written in 16-bit units. the c2sync register is valid only in models pd703089y and 70f3089y. cautions 1. the cpu is able to read the cnsync register at any time. 2. writing to the cnsync register is enabled in initialization mode (when cnctrl register?s init bit = 1). 3. the limit values of can protocol when setting the sptra bit and dbtra bit are as follows (a = 0 to 4). ? ? ? ? 5 btl spt (sample point) 17 btl [4 set values of sptr4 to sptr0 16] ? ? ? ? 8 btl dbt (data bit time) 25 btl [7 set values of dbtr4 to dbtr0 24] ? ? ? ? sjw (synchronization jump width) dbt ? ? ? ? spt ? ? ? ? 2 (dbt ? ? ? ? spt) 8 remark btl = 1/f btl (f btl : can protocol layer basic system clock) (1/2) after reset: 0218h r/w addresses: c1sync: xx3ffc5eh c2sync: xx3ffc9eh 15 14 13 12 11 10 9 8 cnsync 0 0 0 samp sjwr1 sjwr0 sptr4 sptr3 (n = 1, 2)76543210 sptr2 sptr1 sptr0 dbtr4 dbtr3 dbtr2 dbtr1 dbtr0 samp bit sampling specification 0 sample data received at the sample point once 1 sample received data three times and majority value used as sampled value sjwr1 sjwr0 synchronization jump width note 00btl 01btl 2 10btl 3 11btl 4 note as stipulated in the can protocol specification, ver. 2.0 partb active. remark btl = 1/f btl (f btl : can protocol layer basic system clock)
chapter 19 fcan controller (v850/sc3) user?s manual u15109ej3v0ud 627 (2/2) sptr4 sptr3 sptr2 sptr1 sptr0 position of sampling point 00010btl 3 note 00011btl 4 note 00100btl 5 00101btl 6 00110btl 7 00111btl 8 01000btl 9 01001btl 10 01010btl 11 01011btl 12 01100btl 13 01101btl 14 01110btl 15 01111btl 16 10000btl 17 other than above setting prohibited sampling point within bit timing is selected. dbtr4 dbtr3 dbtr2 dbtr1 dbtr0 data bit time 00111btl 8 01000btl 9 01001btl 10 01010btl 11 01011btl 12 01100btl 13 01101btl 14 01110btl 15 01111btl 16 10000btl 17 10001btl 18 10010btl 19 10011btl 20 10100btl 21 10101btl 22 10110btl 23 10111btl 24 11000btl 25 other than above setting prohibited 1-bit data length is set for can bus note this setting is reserved for setting sample point extension and is not compliant with the can protocol specifications. remark btl = 1/f btl (f btl : can protocol layer basic system clock)
chapter 19 fcan controller (v850/sc3) user?s manual u15109ej3v0ud 628 19.6 cautions regarding bit set/clear function the fcan control registers include registers whose bits can be set or cleared via the cpu and via the can interface. an operation error occurs if the following registers are written to directly, so do not directly write (via bit manipulation, read/modify/write, or direct writing of target values) values to them. ? can global status register (cgst) ? can global interrupt enable register (cgie) ? cann control register (cnctrl) ? cann definition register (cndef) ? cann interrupt enable register (cnie) remark n = 1, 2 all 16 bits in the above registers can be read via the usual method. use the procedure described in figure 19-3 below to set or clear the lower 8 bits in these registers. setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (see figure 19-4 ). figure 19-3 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register. figure 19-3. example of bit setting/clearing operations 0000000011010001 0000101111011000 set00001011 0000000000000011 clear 11011000 set set no change no change clear no change clear clear bit status register ? s current values write values register ? s value after write operations
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 629 figure 19-4. 16-bit data during write operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n status of bit n after bit set/clear operation 0 0 no change 01 0 10 1 1 1 no change remark n = 0 to 7
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 630 19.7 time stamp function caution in the v850/sc3, the time stamp function by sof detection during message transmission/reception cannot be used. only the time stamp function by eof detection during message reception can be used for the v850/sc3. however, only the value captured by the m_time register is valid when the tsm bit of the cgst register is set to 1 and the tmr bit of the cnctrl register is set to 1. the fcan controller supports a time stamp function. this function is needed to build a global time system. the time stamp function is implemented using a 16-bit free-running time stamp counter. two types of time stamp function can be selected for message reception in the fcan controller. use bit 3 (tmr) of the canx control register (cxctrl) to set the desired time stamp function (x = 1, 2). when the tmrt bit is 0, the time stamp counter value is captured after the sof is sent via the can bus (see figure 19-5 ) and when the tmr bit is 1, the time stamp counter value is captured after the eof is sent via the can bus (a valid message is confirmed) (see figure 19-6 ). figure 19-5. time stamp function setting for message reception (when cxctrl register?s tmr bit = 0) message ack field eof sof <2> <1> time stamp counter temporary buffer m_timen can message buffer n <1> the time stamp counter value is captured when the sof is sent via the can bus. <2> a message is stored in can message buffer n and the value in the temporary buffer is copied to the m_timen register in can message buffer n when the eof is sent via the can bus. remark n = 00 to 31 x = 1, 2
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 631 figure 19-6. time stamp function setting for message reception (when cxctrl register?s tmr bit = 1) message ack field eof sof <1> time stamp counter m_timen can message buffer n <1> when the eof is sent via the can bus (a valid message is acknowledged), the captured time stamp counter value is copied to the m_timen register in can message buffer n when a message is stored in can message buffer n. remark n = 00 to 31 x = 1, 2 in a global time system, the time value must be captured using the sof. in addition, the ability to capture the counter value when data is stored in a message buffer is useful for evaluating the fcan controller ? s performance. the captured time stamp counter value is stored in can message buffer n, so can message buffer n has its own time stamp function (n = 00 to 31). when the sof is sent via the can bus while transmitting a message, there is an option to replace the last two bytes of the message with the time stamp counter value by setting bit 5 (ats) of can message control register n (m_ctrln). this function can be selected for can message buffer n on a buffer by buffer basis. figure 19-7 shows the time stamp setting when the ats bit = 1.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 632 figure 19-7. time stamp function setting for message transmission (when m_ctrl register?s ats bit = 1) message ack field eof sof <2> <1> time stamp counter temporary buffer <1> the time stamp counter value is captured to the temporary buffer when the sof is detected on the can bus. <2> the value of the temporary buffer is added to the last 2 bytes of the data length code note specified by bits dlc3 to dlc0 of the m_dlcn register. note the ats bit of the m_ctrln register must be 1 and the data length must be more than 2 bytes to add the time stamp counter value to the transmit message. remark n = 00 to 31 table 19-12. example when adding captured time stamp counter value to last 2 bytes of transmit message data field dlc bit value note 1 data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 1 m_datan0 register value ??????? 2 note 2 note 3 ?????? 3 m_datan0 register value note 2 note 3 ????? 4 m_datan0 register value m_datan1 register value note 2 note 3 ???? 5 m_datan0 register value m_datan1 register value m_datan2 register value note 2 note 3 ??? 6 m_datan0 register value m_datan1 register value m_datan2 register value m_datan3 register value note 2 note 3 ?? 7 m_datan0 register value m_datan1 register value m_datan2 register value m_datan3 register value m_datan4 register value note 2 note 3 ? 8 m_datan0 register value m_datan1 register value m_datan2 register value m_datan3 register value m_datan4 register value m_datan5 register value note 2 note 3 9 to 15 m_datan0 register value m_datan1 register value m_datan2 register value m_datan3 register value m_datan4 register value m_datan5 register value note 2 note 3 notes 1. see 19.5.1 can message data length registers 00 to 31 (m_dlc00 to m_dlc31) . 2. the lower 8 bits of the time stamp counter value when the sof is detected on the can bus 3. the higher 8 bits of the time stamp counter value when the sof is detected on the can bus remark n = 00 to 31
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 633 19.8 message processing a modular system is used for the fcan controller. consequently, messages can be placed at any location within the message area. the messages can be linked to mask functions that are in turn linked to can modules.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 634 19.8.1 message transmission the fcan system is a multiplexed communication system. the priority of message transmission within this system is determined based on message identifiers (ids). to facilitate communication processing by application software when there are several messages awaiting transmission, the can module uses hardware to check the message ids and automatically determine whether or not linked messages are prioritized. this eliminates the need for software-based priority control. in addition, the priority at transmission can be controlled by setting the pbb bit of the cndef register. ? when the pbb bit is set to 0 (see figure 19-8 ) transmission priority is controlled by the identifier (id). the number note of messages waiting to be transmitted in the message buffer that can be set simultaneously by application software is up to five messages per can module. note the number of message buffers when the trq bit of the m_statn register = 1. ? when the pbb bit is set to 1 (see figure 19-9 ) transmission priority is controlled by the message numbers. the number note of messages waiting to be transmitted in the message buffer is not limited by the application software. figure 19-8. message processing example (when pbb bit = 0) message no. can module transmits messages in the following sequence. message waiting to be transmitted id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 6 2. message 1 3. message 8 4. message 5 5. message 2 figure 19-9. message processing example (when pbb bit = 1) message no. can module transmits messages in the following sequence. message waiting to be transmitted id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 1 2. message 2 3. message 5 4. message 6 5. message 8
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 635 19.8.2 message reception when two or more message buffers of the can module receive a message, the storage priority of the received messages is as follows (the storage priority differs between data frames and remote frames). table 19-13. storage priority for data frame reception priority conditions 2 (high) unmasked message buffer 3 message buffer linked to mask 0 4 message buffer linked to mask 1 5 message buffer linked to mask 2 6 (low) message buffer linked to mask 3 table 19-14. storage priority for remote frame reception priority conditions 1 (high) transmit message buffer 2 unmasked message buffer 3 message buffer linked to mask 0 4 message buffer linked to mask 1 5 message buffer linked to mask 2 6 (low) message buffer linked to mask 3 a message (data frame or remote frame) is always stored in a receive message buffer with a higher priority, not in a receive buffer with a lower priority. for example, when the unmasked receive message buffer and the message buffer linked to the mask 0 have the same id, a message is always stored in the unmasked receive message buffer even if the unmasked receive message buffer has already received a message. when two or more message buffers with the same priority exist in the same can module, the priority is as follows. table 19-15. priority of same priority level priority condition 1 (high) dn bit of m_stat register is not set (1) 2 (low) dn bit of m_stat register is set (1) when two or more message buffers with the same priority exist, the message buffer with the smaller message number takes precedence. also, when two or more message buffers with the same id exist, the message buffer with the smaller message number takes precedence.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 636 19.9 mask function a mask linkage function can be defined for each received message. this means that there is no need to distinguish between local masks and global masks. when the mask function is used, the received message ? s identifier is compared with the message buffer ? s identifier and the message can be stored in the defined message buffer regardless of whether the mask sets ? 0 ? or ? 1 ? as a result of the comparison. when the mask function is operating, a bit whose value is defined as ? 1 ? by masking is not subject to the above- mentioned comparison between the received message ? s identifier and the message buffer ? s identifier. however, this comparison is performed for any bit whose value is defined as ? 0 ? by masking. for example, let us assume that all messages that have a standard-format id in which bit id27 to id25 = 0 and bits id24 and id22 = 1 are to be stored in message buffer 14 (which is linked by can module 1 or mask 1 as was explained in 19.5.6 ). the procedure for this example is shown below. <1> identifier bits to be stored in message buffer id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x0001x1xxxx x = don ? t care messages with id in which bits id27 to id25 = 0 and bits id24 and id22 = 1 are registered (initialized) in message buffer 14 (see 19.5.5 ). <2> identifier bits set to message buffer 14 (example) (using can message id registers l14 and h14 (m_idl14 and m_idh14)) id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 00001010000 id17 id16 id15 id14 id13 id12 id11 id10 id9 id8 id7 00000000000 id6 id5 id4 id3 id2 id1 id0 0000000 message buffer 14 is set as a standard-format identifier linked to mask 1 (see 19.5.6 ).
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 637 <3> mask setting for can module 1 (mask 1) (example) (using can1 address mask 1 registers l and h (c1maskl1 and c1maskh1)) cmid28 cmid27 cmid26 cmid25 cmid24 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 10000101111 cmid17 cmid16 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 cmid7 11111111111 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 1111111 1: do not compare (mask) 0: compare values are written to mask 1 (see 19.5.18 ), bits cmid27 to cmid24 and cmid22 = 0 and bits cmid28, cmid23, and cmid21 to cmid0 = 1.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 638 19.10 protocol can (controller area network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class c). can is prescribed in the iso 11898. for details, refer to the iso 11898 specifications. the can specification is generally divided into two layers: a physical layer and a data link layer. in turn, the data link layer includes logical link control and medium access control. the composition of these layers is illustrated below. figure 19-10. composition of layers note can controller specification 19.10.1 frame format (1) standard format frame in this format 2048 different identifiers can be set. ? the standard format frame uses 11-bit identifiers, which means that it can handle up to 2048 messages. (2) extended format frame this format is used to set the identifiers of approx. 5.3 million types. ? the extended format frame uses 29-bit (11 bits + 18 bits) identifiers which increases the number of messages that can be handled to 2048 2 18 messages. ? extended format frame is set when ? recessive: logical level 1 ? is set for both the srr and ide bits in the arbitration field. physical layer prescription of signal level and bit description data link layer note logical link control (llc) medium access control (mac) acceptance filtering overload report recovery management data capsuled/not capsuled frame coding (stuffing/not stuffing) medium access management error detection error report acknowledgement seriated/not seriated higher lower
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 639 19.10.2 frame types following four types of frames are used in can protocol. table 19-16. frame type frame type description data frame frame used to transmit data remote frame frame used to request a data frame error frame frame used to report error detection overload frame frame used to delay the next data frame or remote frame (1) bus value the bus values are divided into dominant and recessive. ? dominant level is indicated by logical 0. ? recessive level is indicated by logical 1. ? when a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. 19.10.3 data frame and remote frame (1) data frame a data frame is composed of seven fields. figure 19-11. data frame r d interframe space end of frame (eof) ack field crc field data field control field arbitration field start of frame (sof) data frame <1> <2> <3> <4> <5> <6> <7> <8> remark d: dominant = 0 r: recessive = 1
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 640 (2) remote frame a remote frame is composed of six fields. figure 19-12. remote frame r d interframe space end of frame (eof) ack field crc field control field arbitration field start of frame (sof) remote frame <1> <2> <3> <5> <6> <7> <8> remarks 1. the data field is not transferred even if the control field ? s data length code is not ? 0000b ? . 2. d: dominant = 0 r: recessive = 1 (3) description of fields <1> start of frame (sof) the start of frame field is located at the start of a data frame or remote frame. figure 19-13. start of frame (sof) r d 1 bit start of frame (interframe space or bus idle) (arbitration field) remark d: dominant = 0 r: recessive = 1 ? if the dominant level is detected in bus idle mode, the start of frame is recognized. ? if the recessive level is detected at the sample point of the start of frame, it is judged as noise and the bus idle state is entered again.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 641 <2> arbitration field the arbitration field is used to set the priority, data frame or remote frame, and frame format. figure 19-14. arbitration field (during standard format mode) r d ide (r1) r0 rtr identifier arbitration field (control field) (11 bits) id28 id18 (1 bit) (1 bit) remark d: dominant = 0 r: recessive = 1 figure 19-15. arbitration field (in extended format mode) r d r1 r0 rtr ide srr identifier identifier arbitration field (control field) (11 bits) (18 bits) id28 id18 id17 id0 (1 bit) (1 bit) (1 bit) cautions 1. id28 to id0 are identifier bits. 2. identifier bits are transferred in msb-first order. remark d: dominant = 0 r: recessive = 1 table 19-17. rtr frame settings frame type rtr bit data frame 0 (d) remote frame 1 (r) table 19-18. frame format setting (ide bit) and number of identifier (id) bits frame format srr bit ide bit no. of bits standard format mode none 0 (d) 11 bits extended format mode 1 (r) 1 (r) 29 bits
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 642 <3> control field the control field sets ? n ? as the number of data bytes in the data field (n = 0 to 8). figure 19-16. control field r d r1 (ide) r0 rtr dlc2 dlc3 dlc1 dlc0 control field (data field) (arbitration field) remark d: dominant = 0 r: recessive = 1 in a standard format frame, the control field ? s ide bit is the same as the r1 bit. table 19-19. data length code settings data length code dlc3 dlc2 dlc1 dlc0 data byte count 0000 0 bytes 0001 1 byte 0010 2 bytes 0011 3 bytes 0100 4 bytes 0101 5 bytes 0110 6 bytes 0111 7 bytes 1000 8 bytes other than above 8 bytes regardless of the value of dlc3 to dlc0 caution in the remote frame, there is no data field even if the data length code is not 0000b.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 643 <4> data field the data field contains the amount of data (byte unit) set by the control field. up to 8 units of data can be set. figure 19-17. data field r d data (8 bits) data (8 bits) data field (crc field) (control field) remark d: dominant = 0 r: recessive = 1 <5> crc field the crc field is a 16-bit field that is used to check for errors in transmit data. figure 19-18. crc field r d crc sequence crc delimiter (1 bit) (15 bits) crc field (ack field) (data field or control field) remark d: dominant = 0 r: recessive = 1 ? the polynomial p(x) used to generate the 15-bit crc sequence is expressed as follows. p(x) = x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1 ? transmitting node: the crc sequence calculated from the data (before bit stuffing) in the start of frame, arbitration field, control field, or data field is the transferred. ? receiving node: the crc sequence calculated using data bits that exclude the stuffing bits in the receive data is compared with the crc sequence in the crc field. if the two crc sequences do not match, the node is transferred to an error frame.
chapter 19 fcan controller (v850/sc3) user?s manual u15109ej3v0ud 644 <6> ack field the ack field is used to confirm normal reception. figure 19-19. ack field r d ack slot (1 bit) ack delimiter (1 bit) ack field (end of frame) (crc field) remark d: dominant = 0 r: recessive = 1 ? if no crc error is detected, the receiving node set the ack slot to the dominant level. ? the transmitting node outputs two recessive-level bits. <7> end of frame (eof) the end of frame field indicates the end of data frame/remote frame. figure 19-20. end of frame (eof) r d end of frame (7 bits) (interframe space or overload frame) (ack field) remark d: dominant = 0 r: recessive = 1
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 645 <8> interframe space the interframe space is inserted after the data frame, remote frame, error frame, and overload frame to separate one frame from the next. ? the bus status differs depending on the error status. (a) error active node the error active node is composed of a 3-bit intermission field and a bus idle field. figure 19-21. interframe space (error active node) r d interframe space intermission (3 or 2 bits) bus idle (0 or more bits) (frame) (frame) remarks 1. bus idle: status in which the bus is not used by nodes. 2. d: dominant = 0 r: recessive = 1 (b) error passive node the error passive node is composed of an intermission field, suspend transmission field, and bus idle field. figure 19-22. interframe space (error passive node) r d interframe space intermission (3 or 2 bits) suspend transmission (8 bits) bus idle (0 or more bits) (frame) (frame) remarks 1. bus idle: status in which the bus is not used by nodes. suspend transmission: 8-bit recessive transmitted from the node in the error passive status. 2. d: dominant = 0 r: recessive = 1
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 646 ? operation in error status table 19-20. operation in error status error status operation error active when the bus is idle, the transmit enable mode is set for each node. transmission then starts from a node. error passive after the 8-bit bus idle field (suspend transmission), the transmit enable mode is set. receive mode is set if a transmission starts from a different node in bus idle mode (the transmission priority of the local node is lowered). ? operation when the third bit of the intermission field is dominant level table 19-21. operation when third bit of intermission is dominant level error status operation no pending transmissions a receive operation is performed when start of frame output by the other node is detected. pending transmission exists the identifier is transmitted when start of frame output by the local node is detected.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 647 19.10.4 error frame an error frame is output from a node in which an error has been detected. figure 19-23. error frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame error delimiter error flag 2 error flag 1 error generation bit error frame remark d: dominant = 0 r: recessive = 1 table 19-22. field definitions of error frame no. name bit count definition <1> error flag 1 6 error active node: consecutive output of 6 dominant-level bits. error passive node: consecutive output of 6 recessive-level bits. when the other node outputs a dominant level during output of the passive error flag, the passive error flag does not end until 6 same-level bits are detected consecutively. <2> error flag 2 0 to 6 a node that receives error flag 1 is a node in which bit stuffing errors are detected, after which error flag 2 is output. <3> error delimiter 8 8 consecutive recessive-level bits are output. if a dominant level bit is detected at the eighth bit, an overload frame is transmitted starting at the next bit. <4> error generation bit ? bit in which the error is detected. this bit is output following the bit where the error occurred. if the error is a crc error, it is output following an ack delimiter. <5> interframe space/overload frame ? an interframe space or overload frame starts from here.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 648 19.10.5 overload frame an overload frame is transmitted under the following conditions. ? when the receiving node is not yet ready to receive. ? if a dominant level is detected at the first two bits during intermission mode. ? if a dominant level is detected at the last bit (8th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter. figure 19-24. overload frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame overload delimiter overload flag (node n) overload flag (node m) frame overload frame remarks 1. node n/node m: each node (n m) 2. d: dominant = 0 r: recessive = 1 table 19-23. field definition of overload frame no name bit count definition <1> overload flag starting from node m 6 consecutive output of 6 dominant-level bits. output when node m is not ready to receive. <2> overload flag starting from node n 0 to 6 node n, which has received an overload flag in the interframe space, outputs an overload flag <3> overload delimiter 8 consecutive output of 8 recessive-level bits. if a dominant level is detected at the eighth bit, an overload frame is sent starting at the next bit. <4> frame ? output following an end of frame, error delimiter, or overload delimiter. <5> interframe space or overload frame ? an interframe space or overload frame starts from here. remark node n/node m: each node (n m)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 649 19.11 functions 19.11.1 determination of bus priority (1) when one node has starting transmitting ? in bus idle mode, the node that outputs data first starts transmitting. (2) when several nodes have started transmitting ? the node that outputs the longest string of consecutive dominant-level bits starting from the first bit in the arbitration field has top priority for bus access (dominant-level bits take precedence due to wired-or bus arbitration). ? the transmitting node compares the arbitration field which it has output and the bus data level. table 19-24. determination of bus priority matched levels transmission continues mismatched levels when a mismatch is detected, data output stops at the next bit, and the operation switches to reception. (3) priority between data frame and remote frame ? if a bus conflict occurs between a data frame and a remote frame, the data frame takes priority because its last bit (rtr) is dominant level. 19.11.2 bit stuffing bit stuffing is when one bit of inverted data is added for resynchronization to prevent burst errors when the same level is maintained for five consecutive bits. table 19-25. bit stuffing transmit when transmitting data frames and remote frames, if the same level is maintained for at least five bits between the start of frame and crc fields, one bit of data whose level is inverted from the previous level is inserted before the next bit. receive when receiving data frames and remote frames, if the same level is maintained for at least five bits between the start of frame and crc fields, the next bit of data is deleted before reception is resumed. 19.11.3 multimasters since bus priority is determined based on the identifier, any node can be used as the bus master. 19.11.4 multi-cast even when there is only one transmitting node, the same identifier can be set for several nodes, so that the same data can be received by several nodes at the same time (this is called ? multi-casting ? ).
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 650 19.11.5 can sleep mode/can stop mode function the can sleep mode/can stop mode function can be used to set the fcan controller to sleep (standby) mode to reduce power consumption. the can sleep mode is set via the procedure stipulated in the can specifications. the can sleep mode can be set to either wake up or not wake up when the bus is operated (this is controlled via cpu access). 19.11.6 error control function (1) types of errors table 19-26. types of errors description of error detected status error type detection method detection condition transmit/ receive field/frame bit error comparison of output level and bus level (excludes stuff bits) mismatch between levels transmitting/ receiving nodes bus output of data from bits in start of frame to end of frame, error frame, or overload frame stuff error use stuff bits to check receive data six consecutive bits of same-level data transmitting/ receiving nodes start of frame to crc sequence crc error comparison of crc generated from receive data and received crc sequence crc mismatch receiving node start of frame to data field form error check fixed-format field/frame detection of inverted fixed format receiving node ? crc delimiter ? ack field ? end of frame ? error frame ? overload frame ack error use transmitting node to check ack slot use ack slot to detect recessive level transmitting node ack slot (2) error frame output timing table 19-27. error frame output timing error type output timing bit error, stuff error, form error, ack error error frame is output at the next bit following the bit where error was detected crc error error frame is output at the next bit following the ack delimiter (3) handling of errors the transmitting node retransmits the data frame or remote frame after the error frame has been transmitted.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 651 (4) error statuses (a) types of error statuses the three types of error statuses are listed below. error active error passive bus off ? the error status is controlled by the transmit error counter and receive error counter (see 19.5.22 cann error count register (cnerc) ). ? the various error statuses are categorized according to their error counter values. ? when the error counter value reaches 96 or more, the bus status must be tested since the bus may become seriously damaged. ? during start-up, if only one node is active, the error frame and data are repeatedly resent because no ack is returned even data has been transmitted. table 19-28. types of error statuses error status type operation error counter value type of output error flag error active transmit/ receive 0 to 127 active error flag (6 consecutive dominant level bits) transmit 128 to 255 error passive receive 128 or more passive error flag (6 consecutive recessive level bits) bus off transmit 256 or more transfer is not possible. when a string of at least 11 consecutive recessive level bits occurs 128 times, the error counter is zero-cleared and error active status can be resumed.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 652 (b) error counter the error counter value is incremented each time an error occurs and is decremented when a transmit or receive operation ends normally. the count up/count down timing occurs at the first bit of the error delimiter. table 19-29. error counter status transmit error counter (tec7 to tec0) receive error counter (rec7 to rec0) receiving node has detected an error (except for bit errors that occur in an active error flag or overload flag) no change +1 dominant level is detected following error frame ? s overload flag output by the receiving node no change +8 transmitting node has sent an error flag [when error counter = 0] <1> an ack error was detected in error passive status and a dominant level was not detected during error flag output <2> a stuff error occurs in the arbitration field +8 no change detection of bit error during output of active error flag or overload flag (transmitting node with error active status) +8 no change detection of bit error during output of active error flag or overload flag (receiving node with error active status) no change +8 14 consecutive dominant level bits were detected from the start of each node ? s active error flag or overload flag, followed by detection of eight consecutive dominant level bits. each node has detected eight consecutive dominant level bits after a passive error flag. +8 +8 the transmitting node has completed a transmit operation without any errors ( 0 if error counter value is 0). ? 1 no change the receiving node has completed a receive operation without any errors. no change ?? 1 (1 rec7 to rec0 127) ? 0 (rec7 to rec0 = 0) ? 127 is set (rec7 to rec0 > 127) (c) occurrence of bit error during intermission in this case, an overload frame occurs. caution when an error occurs, error control is performed according to the contents of the transmitting and receiving error counters as they existed prior to the error?s occurrence. the error counter value is incremented only after an error flag has been output.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 653 19.11.7 baud rate control function (1) prescaler the fcan controller of the v850/sc3 includes a prescaler for dividing the clock supplied to the can (f mem1 ). this prescaler generates a clock (f btl ) that is based on a division ratio ranging from 2 to 128 applied to the can base clock (f mem ) when the cnbrp register ? s tlm bit = 0, and from 2 to 256 when the tlm bit = 1 (see 19.5.25 cann bit rate prescaler register (cnbrp) ). (2) nominal bit time (8 to 25 time quanta) the definition of 1 data bit time (1 time quantum) is shown below. caution when selecting f mem1 as the clock (f mem ) to the memory access controller using the can main clock select register (cgcs) and f mem /2 as the can protocol layer base system clock (f btl ) using the cann bit rate prescaler register (cnbrp), set f xx 16 mhz to make one data bit time 8 time quanta. similarly, set f xx 18 mhz to make one data bit time 9 time quanta. if used with a larger frequency than above, the baud rate exceeds 1 mbps, which is the maximum value of the can protocol. remark 1 time quantum = 1/f btl
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 654 figure 19-25. nominal bit time nominal bit time sjw sjw phase segment 2 phase segment 1 sample point prop segment sync segment segment name segment length description sync segment (synchronization segment) 1 this segment begins when resynchronization occurs. prop segment (propagation segment) 1 to 8 (programmable) this segment is used to absorb the delays caused by the output buffer, can bus, and input buffer. it is set to return an ack signal until phase segment 1 begins. prop segment time (output buffer delay) + (can bus delay) + (input buffer delay) phase segment 1 (phase buffer segment 1) 1 to 8 (programmable) phase segment 2 (phase buffer segment 2) maximum value from phase segment 1 or ipt note (ipt = 0 to 2) this segment is used to compensate for errors in the data bit time. it accommodates a wide margin or error but slows down communication speed. sjw (resynchronization jump width) 1 to 4 (programmable) this sets the range for bit synchronization. note ipt: information processing time ipt is a period in which the current bit level is referenced and judgement for the next processing is performed. ipt is indicated by the expression below using the supply clock (f mem1 ) to can. ipt = f mem1 3 (3) data bit synchronization ? since the receiving node has no synchronization signal, synchronization is performed using level changes that occur on the bus. ? as for the transmitting node, data is transmitted in sync with the transmitting node ? s bit timing. (a) hardware synchronization this is bit synchronization that is performed when the receiving node has detected a start of frame in bus idle mode. ? when a falling edge is detected on the bus, the current bit is assigned to the sync segment and the next bit is assigned to the prop segment. in such cases, synchronization is performed regardless of the sjw (resynchronization jump width). ? since bit synchronization must be established after a reset or after a wakeup, hardware synchronization is performed only at the first level change that occurs on the bus (for the second and subsequent level changes, bit synchronization is performed as shown below).
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 655 figure 19-26. coordination of data bit synchronization phase segment 2 phase segment 1 prop segment sync segment start of frame bus idle can bus bit timing (b) resynchronization resynchronization is performed when a level change is detected on the bus during a receive operation (only when the last sampling was the recessive level). ? the edge ? s phase error is produced by the relative positions of the detected edge and sync segment. 0: when edge is within sync segment positive: edge is before sample point (phase error) negative: edge is after sample point (phase error) ? when the edge is detected as within the bit timing specified by the sjw, synchronization is performed in the same way as hardware synchronization. ? when the edge is detected as extending beyond the bit timing specified by the sjw, synchronization is performed on the following basis. when phase error is positive: phase segment 1 is lengthened to equal the sjw when phase error is negative: phase segment 2 is shortened to equal the sjw ? a ? shifting ? of the baud rate for the transmitting and receiving nodes moves the relative position of the sample point for data on the receiving node. figure 19-27. resynchronization phase segment 2 phase segment 1 prop segment sync segment sof next bit previous bit can bus bit timing sjw
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 656 19.12 operations 19.12.1 initialization processing figure 19-28 shows a flowchart of initialization processing. the register setting flow is shown in figures 19-29 to 19-41. figure 19-28. initialization processing start set can main clock selection register (cgcs) : see setting shown in figure 19-29 can main clock selection register (cgcs) settings : see setting shown in figure 19-30 can global interrupt enable register (cgie) settings : see setting shown in figure 19-31 can global status register (cgst) settings : see setting shown in figure 19-32 cann bit rate prescaler (cnbrp) settings : see setting shown in figure 19-33 cann synchronization control register (cnsync) settings : see setting shown in figure 19-34 cann interrupt enable register (cnie) settings : see setting shown in figure 19-35 cann definition register (cndef) settings : see setting shown in figure 19-36 cann control register (cnctrl) settings : see figure 19-37 cann address mask a registers l and h (cnmaskla and cnmaskha) settings : see figure 19-38 message buffer settings set can global interrupt enable register (cgie) set can global status register (cgst) set cann bit rate prescaler (cnbrp) set init = 1 (cnctrl) set cann synchronization control register (cnsync) set cann interrupt enable register (cnie) set cann definition register (cndef) set cann control register (cnctrl) mask required for message id? set message buffer (repeat as many times as number of messages) clear init = 1 (cnctrl) istat = 0? (cnctrl) end yes yes yes no no no istat = 1? (cnctrl) set mask (cnmaska) cstp = 1? (cstop) no yes cstp = 0 (cstop) remark a = 0 to 3 n = 1, 2
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 657 figure 19-29. setting of can main clock select register (cgcs) start f mem f gts1 f gts select clock for memory access controller (mcp0 to mcp3) f mem = f mem1 / (n + 1) n = 0 to 15 (set using bits mcp0 to mcp3) f gts = f gts1 / (n + 1) n = 0 to 255 (set using bits cgts0 to cgts7) gtcs1, gtcs0 = 00: f gts1 = f mem /2 gtcs1, gtcs0 = 01: f gts1 = f mem /4 gtcs1, gtcs0 = 10: f gts1 = f mem /8 gtcs1, gtcs0 = 11: f gts1 = f mem /16 select global timer clock (gtcs0, gtcs1) select system timer prescaler (cgts0 to cgts7) remark f mem = can base clock f mem1 = f xx : clock supply to can f gts1 = global timer clock f gts = system timer prescaler figure 19-30. setting of can global interrupt enable register (cgie) remark gom: bit of can global status register (cgst) efsd: bit of can global status register (cgst) istat: bit of cann control register (cnctrl) start no enable interrupt for g_ie1 bit yes set g_ie1 = 1 clear g_ie1 = 0 no enable interrupt for g_ie2 bit yes set g_ie2 = 1 clear g_ie2 = 0 interrupt occurrence conditions ? invalid global macro shutdown occurs ? access error to unusable memory address occurs interrupt occurrence conditions ? write access error to the can module register (register with a name starting with "cn" (n = 1, 2)) occurs when the gom bit is 0. ? write access error to the temporary buffer occurs when the gom bit is 1.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 658 figure 19-31. setting of can global status register (cgst) start no use time stamp function? yes set tsm = 1 clear tsm = 0 start fcan operation set gom = 1 clear gom = 0 figure 19-32. setting of cann bit rate prescaler (cnbrp) start no transfer speed is 125 kbps or less yes btype = 0 (low speed) f btl setting when tlm = 0 brp5 to brp0 when tlm = 1 brp7 to brp0 when tlm = 0 f btl = f mem /{(m + 1) 2} m = 0 to 63 (set using bits brp5 to brp0) when tlm = 1 f btl = f mem /(m + 1) m = 0 to 255 (set using bits brp7 to brp0) f btl btype = 1 (high speed) remarks 1. f btl = can protocol layer basic system clock f mem = can base clock 2 .n = 1, 2
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 659 figure 19-33. setting of cann synchronization control register (cnsync) start no samp = 0 set data bit time (dbtr4 to dbtr0) 1 bit time = btl (m + 1) m = 7 to 24 (set using bits dbtr4 to dbtr0) sample point = btl (m + 1) m = 2 to 16 (set using bits sptr4 to sptr0) note set sample point (sptr4 to sptr0) set sjw (sjwr1, sjwr0) samp = 1 yes set once-only (single shot) sampling set sampling for one location only set sampling for three locations sjw = btl ( m + 1) m = 0 to 3 (set using bits sjwr1 and sjwr0) note the setting of m = 2, 3 is reserved for setting sample point extension, and is not compliant with the can protocol specifications. remarks 1. btl = 1/f btl (f btl = can protocol layer basic system clock) 2 .n = 1, 2
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 660 figure 19-34. setting of cann interrupt enable register (cnie) set e_int0 = 1 clear e_int0 = 0 start no yes yes yes yes yes yes yes clear e_int0 = 1 set e_int0 = 0 enable interrupt for e_int0? interrupt enable flag for end of transmission set e_int1 = 1 clear e_int1 = 0 no clear e_int1 = 1 set e_int1 = 0 enable interrupt for e_int1? interrupt enable flag for end of reception set e_int2 = 1 clear e_int2 = 0 no clear e_int2 = 1 set e_int2 = 0 enable interrupt for e_int2? interrupt enable flag for error passive or bus off by tec set e_int3 = 1 clear e_int3 = 0 no clear e_int3 = 1 set e_int3 = 0 enable interrupt for e_int3? interrupt enable flag for error passive by rec set e_int4 = 1 clear e_int4 = 0 no clear e_int4 = 1 set e_int4 = 0 enable interrupt for e_int4? interrupt enable flag for wake-up from can sleep mode set e_int5 = 1 clear e_int5 = 0 no clear e_int5 = 1 set e_int5 = 0 enable interrupt for e_int5? interrupt enable flag for can bus error set e_int6 = 1 clear e_int6 = 0 no clear e_int6 = 1 set e_int6 = 0 enable interrupt for e_int6? interrupt enable flag for can error remark n = 1, 2
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 661 figure 19-35. setting of cann definition register (cndef) set mom = 1 clear mom = 0 start no yes yes yes yes clear mom = 1 set mom = 0 set to diagnostic processing mode? normal operating mode normal operation mode transmit priority is determined based on message numbers diagnostic processing mode transmit priority is determined based on identifiers single-shot mode: transmit only once. do not retransmit. clear dgm = 1 set dgm = 0 no set dgm = 1 clear dgm = 0 store to buffer used for diagnostic processing mode note ? clear pbb = 1 set pbb = 0 no set pbb = 1 clear pbb = 0 determine transmit priority based on identifiers? set ssht = 1 clear ssht = 0 no clear ssht = 1 set ssht = 0 set single-shot mode? note bits 5 to 3 (mt2 to mt0) in can message configuration register m (m_confm) are set as ? 111 ? remark n = 1, 2 m = 00 to 31
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 662 figure 19-36. setting of cann control register (cnctrl) start yes clear tmr = 1 set tmr = 0 store timer value at sof? set time stamp for receiving set overwrite for receive message buffer set dominant level for transmit pins set dominant level for receive pins store timer value at eof do not overwrite message in dn flag (delete new message) set dominant level to high level set dominant level to high level set ovm = 1 clear ovm = 0 yes clear ovm = 1 set ovm = 0 store message in dn flag? set dlevt = 1 clear dlevt = 0 yes clear dlevt = 1 set dlevt = 0 set dominant level to low level? set dlevr = 1 clear dlevr = 0 yes no no no no clear dlevr = 1 set dlevr = 0 set dominant level to low level? set tmr = 1 clear tmr = 0 remark n = 1, 2
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 663 figure 19-37. setting of cann address mask a registers l and h (cnmaskla and cnmaskha) start standard frame mask setting for standard frame (x = 18 to 28) mask setting for extended frame (x = 0 to 28) mask setting for message id format yes cmidx = 0 cmidy = 1 cmidx = 1 compare with received id bit? no yes no yes cmide = 0 cmide = 1 check id type? no yes cmidx = 0 cmidx = 1 compare with received id bit? no (y = 0 to 17)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 664 figure 19-38. message buffer setting start no standard frame? set message id type yes ide = 0 (standard) (m_idhm) set message configuration see figure 19-39 setting of can message configuration registers 00 to 31 (m_conf00 to m_conf31) see figure 19-40 setting of can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) ide = 1 (extended) (m_idhm) set identifier (standard, extended) set message control byte set message length see figure 19-41 setting of message status registers 00 to 31 (m_stat00 to m_stat31) set message status remark m = 00 to 31
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 665 figure 19-39. setting of can message configuration registers 00 to 31 (m_conf00 to m_conf31) start use message buffer? release can message buffer yes yes ma2 to ma0 = 000 ma2 to ma0 = 010 ma2 to ma0 = 001 yes no no no no no no no mt2 to mt0 = 111 (used in diagnostic processing mode) mt2 to mt0 = 000 mt2 to mt0 = 001 mt2 to mt0 = 010 mt2 to mt0 = 011 mt2 to mt0 = 100 mt2 to mt0 = 101 can module 2 message buffer address specification can module 1 yes yes yes yes transmit message receive message (no mask setting) receive message (set mask 0) receive message (set mask 1) receive message (set mask 2) receive message (set mask 3)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 666 figure 19-40. setting of can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) start yes no no rtr = 0 rtr = 1 transmit/receive remote frame transmit/receive data frame? set remote frame auto acknowledge function yes no ie = 0 ie = 1 enable interrupt disable interrupt? yes no rmde0 = 1 rmde0 = 0 remote frame auto acknowledge? yes no rmde1 = 1 rmde1 = 0 ats = 1 ats = 0 set dn flag? yes apply time stamp? set dn flag when remote frame is received
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 667 figure 19-41. setting of can message status registers 00 to 31 (m_stat00 to m_stat31) start clear dn flag clear dn = 1, set dn = 0 (sc_statm) clear trq flag clear trq = 1, set trq = 0 (sc_statm) clear rdy flag clear rdy = 1, set rdy = 0 (sc_statm) remark m = 00 to 31
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 668 19.12.2 transmit setting transmit messages are output from the target message buffer. figure 19-42. transmit setting start end of transmit operation set rdy flag set rdy = 1, clear rdy = 0 (sc_statm) set data (m_datamn) select transmit message buffer set transmit request flag set trq = 1, clear trq = 0 (sc_statm) remark n = 0 to 7 m = 00 to 31
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 669 19.12.3 receive setting receive messages are retrieved from the target message buffer. figure 19-43. setting of receive operation using reception completion interrupt start set rdy flag set rdy = 1, clear rdy = 0 (sc_statm) end of receive operation yes receive data frame no yes receive data frame? receive remote frame : detection methods <1> detect using cann information register (cnlast) <2> detect using can message search start/result register (cgmss/cgmsr) (see figure 19-45 setting of can message search start/result register (cgmss/cgmsr) .) no dn = 0 (m_statm) detect target message buffer clear dn flag clear dn = 1, set dn = 0 (sc_statm) get data length transmit operation get data get time stamp reception completion interrupt occurs remark m = 00 to 31
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 670 figure 19-44. setting receive operation using reception polling remark m = 00 to 31 start set rdy flag set rdy = 1, clear rdy = 0 (sc_statm) end of receive operation yes yes receive data frame no yes receive data frame? cnint1 = 1 (cnintp) receive remote frame : detection methods <1> detect using cann information register (cnlast) <2> detect using can message search start/result register (cgmss/cgmsr) (see figure 19-45 setting of can message search start/result register (cgmss/cgmsr). ) no no dn = 0 (m_statm) detect target message buffer clear dn flag clear dn = 1, set dn = 0 (sc_statm) get data length transmit operation get data get time stamp
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 671 figure 19-45. setting of can message search start/result register (cgmss/cgmsr) start yes yes search non mask- linked messages only search all messages (regardless of mask setting) do not check message id format search standard id only check message id? no no cide = 1 (cgmss) cide = 0 (cgmss) cmsk = 0 (cgmss) get search results check dn flag (cdn = 1) check masked messages? cmsk = 1 (cgmss) set start position and start search
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 672 19.12.4 can sleep mode in can sleep mode, the fcan controller can be set to standby mode. a wakeup occurs when there is a bus operation. figure 19-46. can sleep mode setting start end of can sleep mode setting no yes sleep = 1 (cnctrl) set sleep = 1 clear sleep = 0 (cnctrl) remark n = 1, 2 figure 19-47. clearing can sleep mode by can bus active status start can bus active sleep = 0 (cnctrl) wake = 1 (cndef) wake-up interrupt occurs end of can sleep mode clearing operation remark n = 1, 2
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 673 figure 19-48. clearing can sleep mode by cpu clear sleep = 1 set sleep = 0 (cnctrl) sleep = 0 (cnctrl) start end of can sleep mode clearing operation remark n = 1, 2
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 674 19.12.5 can stop mode in can stop mode, the fcan controller can be set to standby mode. no wakeup occurs when there is a bus operation (stop mode is controlled by cpu access only). figure 19-49. can stop mode setting start end of can stop mode setting yes yes sleep = 1 (cnctrl) stop = 1 (cnctrl) no no set stop = 1 clear stop = 0 (cnctrl) set can sleep mode (see figure 19-46 ) remark n = 1, 2 figure 19-50. clearing can stop mode start end of can stop mode clearing operation clear stop = 1 set stop = 0 clear sleep = 1 set sleep = 0 (cnctrl) stop = 0 sleep = 0 (cnctrl)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 675 19.13 rules for correct setting of baud rate the can protocol limit values for ensuring correct operation of fcan are described below. if these limit values are exceeded, a can protocol violation may occur, which can result in operation faults. always make sure that settings are within the range of limit values. (a) 5 btl spt (sampling point) 17 btl [4 set values of sptr4 to sptr0 16] (b) 8 btl dbt (data bit time) 25 btl [7 set values of dbtr4 to dbtr0 24 (c) sjw (synchronization jump width) dbt ? spt (d) 2 (dbt ? spt) 8 remark btl = 1/f btl (f btl : can protocol layer basic system clock) sptr4 to sptr0 (bits 9 to 5 of the cann synchronization control register (cnsync)) dbtr4 to dbtr0 (bits 4 to 0 of the cann synchronization control register (cnsync)) (1) example of fcan baud rate setting (when cnbrp register ? s tlm bit = 0) the following is an example of how correct settings for the cnbrp register and cnsync register can be calculated. conditions from can bus: <1> can base clock frequency (f mem ): 16 mhz <2> can bus baud rate: 83 kbps <3> sample point: 80% or more <4> synchronization jump width: 3 btl first, calculate the ratio between the can base clock frequency and the can bus baud rate frequency as shown below. f mem /can bus band rate = 16 mhz/83 khz 192.77 2 6 3 set an even number between 2 and 128 to the cnbrp register ? s bits brp5 to brp0 as the setting for the prescaler (can protocol layer basic system clock: f btl ), then set a value between 8 and 25 to the cnsync register ? s bits dtbr4 to dbtr0 as the data bit time. since it is assumed that the sjw (synchronization jump width) value is 3, the maximum setting for spt (sample point) is the ? data bit time setting minus 3 ? or less and 17 or less. (spt dbt ? 3 and spt 17)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 676 given the above limit values, the following four settings are possible. prescaler dbt spt (max.) calculated spt 24 8 5 5/8 = 62.5% 16 12 9 9/12 = 75% 12 16 13 13/16 = 81% 8 24 17 17/24 = 71% 16 mhz/83 kbps ? 192 = 64 3<1> = 48 4<2> = 32 6<3> = 24 8<4> = 16 12 <5> = 12 16 <6> = 8 24 <7> = 6 32 <8> = 4 48 <9> = 3 64 <10> the settings that can actually be made for the v850/sc3 are in the range from <4> to <7> above (the section enclosed in broken lines). among these options in the range from <4> to <7> above, option <6> is the ideal setting when actually setting the register. (i) prescaler (can protocol layer basic system clock: f btl ) setting f btl is calculated as shown below. ? f btl = f mem /{(a + 1) 2} : [0 a 63] value a is set using bits 5 to 0 (brp5 to brp0) of the cnbrp register. f btl = 16 mhz/12 = 16 mhz/{(5 + 1) 2} thus a = 5 therefore, cnbrp register = 0005h
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 677 (ii) dbt (data bit time) setting dbt is calculated as shown below. ? dbt = btl (a + 1) : [7 a 24] value a is set using bits 4 to 0 (dbtr4 to dbtr0) of the cnsync register. dbt = btl 16 = btl (a + 1) thus a = 15 therefore, the cnbrp register ? s bits dbtr4 to dbtr0 = 01111b note that 1/dbt = f btl /16 ? 1333 khz/16 ? 83 kbps (nearly equal to the can bus baud rate) (iii) spt (sample point) setting given sjw = 3: sjw dbt ? spt 3 16 ? spt spt 13 therefore, spt is set as 13 (max.) spt is calculated as shown below. ? spt = btl (a + 1) : [4 a 16] value a is set using bits 9 to 5 (sptr4 to sptr0) of the cnsync register. spt = btl 13 = btl (12 + 1) thus a = 12 therefore, the cnsync register ? s bits sptr4 to sptr0 = 01100b (iv) sjw (synchronization jump width) setting sjw is calculated as shown below. ? sjw = btl (a + 1) : [0 a 3] value a is set using bits11 and 10 (sjwr1, sjwr0) of the cnsync register. the cnsync register ? s bits sjwr1 and sjwr0 = btl 3 = btl (2 + 1) thus a = 2 therefore, the cnsync register ? s bits sjwr1 and sjwr0 = 10b the cnsync register settings based on these results are shown in figure 19-51 below.
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 678 figure 19-51. cnsync register settings 15 14 13 12 11 10 9 8 cnsync 0 0 0 samp sjwr1 sjwr0 sptr4 sptr3 setting00001001 76543210 sptr2 sptr1 sptr0 dbtr4 dbtr3 dbtr2 dbtr1 dbtr0 setting10001111
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 679 19.14 ensuring data consistency when the cpu reads data from can message buffers, it is essential for the read data to be consistent. two methods are used to ensure data consistency: sequential data read and burst read mode. 19.14.1 sequential data read when the cpu performs sequential access of a message buffer, data is read from the buffer in the order shown in figure 19-74 below. only the fcan internal operation can set the m_statn register ? s dn bit (1) and only the cpu can clear it (0), so during the read operation the cpu must be able to check whether or not any new data has been stored in the message buffer. figure 19-52. sequential data read read cpu end of cpu ? s read operation yes dn = 0 (m_statn) no clear dn flag clear dn = 1, set dn = 0 (sc_statn) read data from message buffer remark n = 00 to 31
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 680 19.14.2 burst read mode burst read mode is implemented in the fcan to enable faster access to complete messages and secure the synchronization of data. burst read mode starts up automatically each time the cpu reads the m_dlcn register and data is then copied from the message buffer area to a temporary read buffer. data continues to be read from the temporary buffer as long as the cpu keeps directly incrementing (+1) the read address (in other words, when data is read in the following order: m_dlcn register m_ctrln register m_timen register m_datan0 to m_datan7 registers m_idln, m_idhn register), and reads more data. if these linear access rules are not followed or if access is attempted to an address that is lower than the midhn register ? s address (such as the m_confn register or m_statn register), burst read mode becomes invalid. cautions 1. 16-bit read access is required for the entire message buffer area when using the burst read mode. if 8-bit access (byte read operation) is attempted, burst read mode does not start up even if the address is linearly incremented (+1) as described above. 2. be sure to read out the value of fcan control registers other than the m_dlcn register before starting the burst read mode. remark n = 00 to 31
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 681 19.15 interrupt conditions 19.15.1 interrupts that occur for fcan controller when interrupts are enabled (condition <1>: the m_ctrlm register ? s ie bit = 1, conditions other than <1>: c_ie register ? s interrupt flags = 1), interrupts will occur under the following conditions (m = 00 to 31). <1> message-related operation has succeeded ? when a message has been received in the receive message buffer ? when a remote frame has been received in the transmit message buffer (only when auto acknowledge mode has not been set, i.e., when the m_ctrlm register ? s rmde0 bit = 0) ? when a message has been transmitted from the transmit message buffer <2> when a can bus error has been detected ? bit error ? bit stuff error ? form error ? crc error ? ack error <3> when the can bus mode has been changed ? error passive status elapsed while fcan was transmitting ? bus off status was set while fcan was transmitting ? error passive status elapsed while fcan was receiving <4> internal error ? overrun error 19.15.2 interrupts that occur for global can interface interrupts occur for the global can interface under the following conditions. <1> interrupt source generated at gint1 (gintp register) ? access to unused area in the can module ? when clearing (0) the gom bit is attempted with the efsd bit of the cgst register = 0, when there is even one can module not initialized (init bit of cnctrl register = 0) <2> interrupt source generated at gint2 (cgintp register) ? write access to the can module register (register with a name starting with ? cn ? (n = 1, 2)), when the gom bit of the cgst register = 0 ? write access to a temporary buffer area when the gom bit of the cgst register = 1
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 682 19.16 how to shutdown fcan controller the following procedure should be used to stop can bus operations in order to stop the clock supply to the can interface (to set low power mode). <1> set fcan controller initialization mode ? set initialization mode (init bit = 1 in cnctrl register (set init bit = 1, clear init bit = 0)) (n = 1, 2) <2> stop time stamp counter ? set tsm bit = 0 in cgst register (set tsm = 0, clear tsm = 1) <3> stop can interface ? set gom bit = 0 in cgst register (set gom = 0, clear gom = 1) ? stop can clock caution if the above procedure is not performed correctly, the can interface (in active status) can cause operation faults. 19.17 cautions on use <1> bit manipulation is prohibited for all fcan controller registers. <2> be sure to properly clear (0) all interrupt request flags note in the interrupt routine. if these flags are not cleared (0), subsequent interrupt requests may not be generated. note also that if an interrupt is generated at the same time as a cpu clear operation, that interrupt request flag will not be cleared (0). it is therefore important to confirm that interrupt request flags have been properly cleared (0). note see 19.5.9 can interrupt pending register (ccintp) , 19.5.10 can global interrupt pending register (cgintp) , and 19.5.11 cann local interrupt pending register (cnintp) . <3> when the cstp bit of the cstop register is set (1), wakeup from the can sleep mode (sleep bit of cann control register (cnctrl) = 1) can be performed in accordance with a change on the can bus. <4> if the os (osek/com) is not used, be sure to execute the following processing. [when can communication is performed using an interrupt routine] ? clear (0) the following interrupt pending bits at the start of the corresponding interrupt routine. ? cnintm bit of cnintp register (n = 1, 2, m = 0 to 6) ? cintm bit of cgintp register (n = 1, 2, m = 1 to 3) ? clear (0) the following enable bits during the corresponding interrupt routine. ? e_intm bit of cnie register (n = 1, 2, m = 0 to 6) ? g_ien bit of cgie register (n = 1, 2)
chapter 19 fcan controller (v850/sc3) user ? s manual u15109ej3v0ud 683 [when can communication is performed by polling of bits, not using interrupt routines] ? the following interrupt mask flags and interrupt enable bits are used when set (1) (do not clear (0) them). ? canmkn bit of canicn register (n= 1 to 7) ? e_intm bit of cnie register (n = 1, 2, m = 0 to 6) ? g_ien bit of cgie register (n = 1, 2) ? ie bit of m_ctrln register (n = 00 to 31) ? clear (0) the following interrupt pending bits in accordance with procedures (i) to (iii) below. ? cnintm bit of cnintp register (n = 1, 2, m = 0 to 6) ? gintn bit of cgintp register (n = 1 to 3) (i) poll the corresponding interrupt request flag. (ii) if the value of the bit in procedure (i) is 1, clear (0) the corresponding interrupt pending bit. (iii) after executing procedure (ii), clear (0) the interrupt request flag. example can reception (i) poll until the canifm bit of the canicm register becomes 1 (m = 2, 5). (ii) clear (0) the cnint1 bit of the cnintp register (n = 1, 2). (iii) clear (0) the canifm bit of the canicm register. <5> in the v850/sc3, the time stamp function by sof detection during message transmission/reception cannot be used. only the time stamp function by eof detection during message reception can be used for the v850/sc3. however, only the value captured by the m_time register is valid when the tsm bit of the cgst register is set to 1 and the tmr bit of the cnctrl register is set to 1.
user?s manual u15109ej3v0ud 684 chapter 20 electrical specifications absolute maximum ratings (t a = 25c) parameter symbol conditions ratings unit v dd v dd0 pin = v dd1 pin ?0.3 to +6.0 v adcv dd adcv dd pin = v dd ?0.3 to +6.0 v supply voltage portv dd portv dd 0 pin portv dd1 pin portv dd2 pin ?0.3 to v dd v v i0 portv dd system pins ?0.3 to portv dd + 0.3 note 1 v v i1 p170 to p176, reset pins ?0.3 to v dd + 0.3 note 1 v input voltage v i2 v pp pin note 2 /mode pin note 3 ?0.3 to +8.5 v analog input voltage v an p70 to p77, p80 to p83 ?0.3 to adcv dd + 0.3 note 1 v v o0 portv dd system pins ?0.3 to portv dd + 0.3 note 1 v output voltage v o1 p170 to p176 ?0.3 to v dd + 0.3 note 1 v per pin 8.0 ma output current, low i ol total for all pins 40 ma per pin ?8.0 ma p40 to p47, p50 to p57, p60 to p65, p90 to p96, clkout ?25 ma p00 to p03, p10 to p17, p30 to p37, p100 to p107, p110 to p117 ?25 ma p04 to p07, p20 to p27, p120 to p127, p130 to p133, p140 to p147, p150 to p157 ?25 ma output current, high i oh p170 to p176 ?15 ma normal operation mode ?40 to +85 c operating ambient temperature t a flash memory programming mode note 2 ?20 to +85 c note 3 ?65 to +150 c storage temperature t stg note 2 ?40 to + 125 c notes 1. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. 2. pd70f3089y 3. pd703068y, 703069y, 703088y, 703089y cautions 1. avoid direct connections among the ic device output (or i/o) pins and between v dd or v cc and gnd. however, direct connections among open-drain and open-collector pins are possible, as are direct connections to external circuits that have timing designed to prevent output conflict with pins that become high-impedance. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
chapter 20 electrical specifications user?s manual u15109ej3v0ud 685 operating conditions (1) operating voltage (portv dd0 portv dd1 portv dd2 v dd0 v dd1 adcv dd ) parameter symbol conditions min. typ. max. unit when all functions are operating 4.5 5.5 v note 1 3.5 5.5 v v dd , adcv dd when all functions are operating (except the a/d converter) note 2 4.0 5.5 v 0.5 f cpu 17 mhz, f xt = 32.768 khz, note 3 3.0 5.5 v supply voltage portv dd 0.5 f cpu 20 mhz, note 3 4.0 5.5 v notes 1. pd703068y, 703069y, 703088y, 703089y 2. pd70f3089y 3. when using the fcan controller: portv dd1 portv dd2 (due to the supply voltage conditions of the in-circuit emulator) remark i/o buffer power supply of each pin is shown below. power supply corresponding pins portv dd0 p40 to p47, p50 to p57, p60 to p65, p90 to p96. clkout portv dd1 p00 to p03, p10 to p17, p30 to p37, p100 to p107, p110 to p117 portv dd2 p04 to p07, p20 to p27, p120 to p127, p130 to p133, p140 to p147, p150 to p157 v dd0 reset v dd1 p170 to p176 adcv dd p70 to p77, p80 to p83 (2) cpu operating frequency parameter symbol conditions min. typ. max. unit main clock operation 0.5 20 mhz cpu operating frequency f cpu subclock operation 32.768 khz
chapter 20 electrical specifications 686 user?s manual u15109ej3v0ud recommended oscillator (1) main clock oscillator (t a = ?40 to +85c) (a) connection of ceramic resonator or crystal resonator x1 x2 parameter symbol conditions min. typ. max. unit oscillation frequency f xx 420mhz ? when reset is released 2 18 /f xx s oscillation stabilization time ? when stop mode is released note s note the typ. value differs depending on the setting of the oscillation stabilization time select register (osts). cautions 1. main clock oscillator operates on the output voltage of the on-chip regulator. external clock input is prohibited. 2. when using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. 3. for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 687 (2) subclock oscillator (t a = ?40 to +85c) (a) connection of crystal resonator xt1 xt2 parameter symbol conditions min. typ. max. unit oscillation frequency f xt 32.768 khz oscillation stabilization time ? when reset is released 10 s cautions 1. subclock oscillator operates on the output voltage of the on-chip regulator. external clock input is prohibited. 2. when using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. 3. for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 20 electrical specifications 688 user?s manual u15109ej3v0ud dc characteristics (t a = ?40 to +85c, portv dd0 = portv dd1 = portv dd2 = 3.0 to 5.5 v, pd703068y, 703069y, 703088y, 703089y: v dd0 = v dd1 = adcv dd = 3.5 to 5.5 v, pd70f3089y: v dd0 = v dd1 = adcv dd = 4.0 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 note 1 0.7portv dd portv dd v v ih2 note 2 0.8portv dd portv dd v v ih6 p70 to p77, p80 to p83 0.7adcv dd adcv dd v v ih7 note 3 0.7v dd v dd v input voltage, high v ih8 reset pin 0.8v dd v dd v v il1 note 1 0 0.3portv dd v v il3 note 2 0 0.2portv dd v v il6 p70 to p77, p80 to p83 0 0.3adcv dd v v il7 note 3 00.3v dd v input voltage, low v il8 reset pin 0 0.2v dd v 3.5 v v dd 5.5 v, i oh = ?100 a v dd ? 0.5 v v oh1 note 3 4.0 v v dd 5.5 v, i oh = ?1 ma v dd ? 1.0 v 3.0 v portv dd 4.0 v, i oh = ?100 a portv dd ? 0.5 v output voltage, high v oh2 note 4 4.0 v portv dd 5.5 v, i oh = ?1 ma portv dd ? 1.0 v 3.5 v v dd 5.5 v, i oh = ?100 a 0.5 v v ol1 note 3 4.0 v v dd 5.5 v, i oh = ?1 ma 0.5 v 3.0 v portv dd 4.0 v, i oh = ?100 a 0.5 v output voltage, low v ol2 note 4 4.0 v portv dd 5.5 v, i oh = ?1 ma 0.5 v notes 1. p11, p14, p16, p21, p25, p27, p33, p40 to p47, p50 to p57, p60 to p65, p90 to p96, p110 to p114, p116, p122, p125 to p127, p130 to p133, p141, p155 and their alternate-function pins 2. p00 to p03, p04 to p07, p10, p12, p13, p15, p17, p20, p22 to p24, p26, p30 to p32, p34 to p37, p100 to p107, p115, p117, p120, p121, p123, p124, p140, p142 to p147, p150 to p154, p156, p157, and their alternate-function pins 3. p170 to p176 and their alternate-function pins 4. all output pins other than p170 to p176 and their alternate-function pins
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 689 dc characteristics (t a = ?40 to +85c, portv dd0 = portv dd1 = portv dd2 = 3.0 to 5.5 v, pd703068y, 703069y, 703088y, 703089y: v dd0 = v dd1 = adcv dd = 3.5 to 5.5 v, pd70f3089y: v dd0 = v dd1 = adcv dd = 4.0 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit note 1 v in = v dd note 2 v in = portv dd input leakage current, high i ih1 note 3 v in = adcv dd 5.0 a input leakage current, low i il1 notes 1, 2 v in = 0 v ? 5.0 a output off-leakage current i l1 note 4 v oh = portv dd 5.0 a pull-up resistor r l1 note 5 v in = 0 v 10 30 100 k ? i dd1 in normal operation mode note 6 25 40 ma i dd2 in halt mode note 7 10 20 ma i dd3 in idle mode note 8 14ma i dd4 in software stop mode note 9 8 100 a i dd5 in normal mode (subclock operation) note 10 50 150 a pd703068y, pd703069y pd703088y, pd703089y i dd6 in idle mode (subclock operation) note 11 13 120 a i dd1 in normal operation mode note 6 42 60 ma i dd2 in halt mode note 7 14 28 ma i dd3 in idle mode note 8 14ma i dd4 in software stop mode note 9 15 100 a i dd5 in normal mode (subclock operation) note 10 300 600 a supply current pd70f3089y i dd6 in idle mode (subclock operation) note 11 170 340 a notes 1. p170 to p176, reset, and their alternate-function pins 2. all input pins other than p170 to p176, reset and their alternate-function pins 3. p70 to p77, p80 to p83 4. p10, p12, p20, p22 (in n-ch open drain mode) 5. p100 to p107 (in key return mode) 6. f cpu = f xx = 20 mhz, v in = v cpureg , peripheral functions operating (except fcan controller) 7. f cpu = f xx = 20 mhz, v in = v cpureg , cpu stopped, peripheral functions operating (except fcan controller) 8. f xx = 20 mhz, v in = v cpureg , all peripheral functions stopped (watch timer operating) 9. f xt = 32.768 khz, v in = v cpureg , main clock oscillator stopped, all peripheral functions stopped (watch timer operating) 10. f cpu = f xt = 32.768 khz, v in = v cpureg , main clock oscillator stopped, all peripheral functions operating (except fcan controller) 11. f xt = 32.768 khz, v in = v cpureg , main clock oscillator stopped, all peripheral functions stopped (watch timer operating)
chapter 20 electrical specifications 690 user?s manual u15109ej3v0ud data retention characteristics (t a = ?40 to +85c) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode note (no functions operating) 2.2 5.5 v data retention current i dddr stop mode note (no functions operating) 5 100 a supply voltage rise time t rvd 200 s supply voltage fall time t fvd 200 s supply voltage hold time (from stop mode setting) t hvd 0ms stop release signal input time t drel 0ns data retention high-level input voltage v ihdr all input ports 0.9v dddr v dddr v data retention low-level input voltage v ildr all input ports 0 0.1v dddr v note subclock stopped t hvd v dddr t drel v ihdr v ihdr t fvd t rvd v dd stop mode release interrupt (nmi, etc.) (released by falling edge) setting stop mode reset (input) stop mode release interrupt (nmi, etc.) (released by rising edge) v ildr
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 691 ac characteristics ac test input test points (v dd : v dd , portv dd ) v dd 0 v v ih v il v ih v il test points input signal ac test output test points (v dd : v dd , portv dd ) load conditions dut (device under test) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit configuration, lower the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means. v oh v ol v oh v ol test points output signal v dd 0 v
chapter 20 electrical specifications 692 user ? s manual u15109ej3v0ud (1) clock timing (a) t a = ?40 to +85c, v dd = 4.0 to 5.5 v, portv dd = 4.0 to 5.5 v, portgnd = 0 v parameter symbol conditions min. max. unit clkout output cycle <1> t cyk 50 ns 31 s clkout high-level width <2> t wkh 0.4(t cyk ? t kr ? t kf )ns clkout low-level width <3> t wkl 0.4(t cyk ? t kr ? t kf )ns clkout rise time <4> t kr 12 ns clkout fall time <5> t kf 12 ns (b) t a = ?40 to +85c, portv dd = 3.0 to 4.0 v, portgnd = 0 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v parameter symbol conditions min. max. unit clkout output cycle <1> t cyk 58.8 ns 31 s clkout high-level width <2> t wkh 0.4(t cyk ? t kr ? t kf )ns clkout low-level width <3> t wkl 0.4(t cyk ? t kr ? t kf )ns clkout rise time <4> t kr 15 ns clkout fall time <5> t kf 15 ns clkout (output) <2> <4> <5> <3> <1>
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 693 (2) output waveform (other than clkout) (a) t a = ?40 to +85c, v dd = 4.0 to 5.5 v, portv dd = 4.0 to 5.5 v, portgnd = 0 v parameter symbol conditions min. max. unit output rise time <6> t or 30 ns output fall time <7> t of 30 ns (b) t a = ?40 to +85c, portv dd = 3.0 to 4.0 v, portgnd = 0 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v parameter symbol conditions min. max. unit output rise time <6> t or 35 ns output fall time <7> t of 35 ns (3) reset timing (t a = ?40 to +85c, portv dd = 3.0 to 5.0 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit reset pin high-level width <8> t wrsh 500 ns reset pin low-level width <9> t wrsl 500 ns <7> <6> output signal <8> <9> reset (input)
chapter 20 electrical specifications 694 user ? s manual u15109ej3v0ud (4) bus timing (a) clock asynchronous (t a = ?40 to +85c, v dd = 4.0 to 5.5 v, portv dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit address setup time (to astb ) <10> t sast 0.5t ? 20 ns address hold time (from astb ) <11> t hsta 0.5t ? 15 ns delay time from dstb to address float <12> t fda 0ns data input setup time from address <13> t said (2 + n)t ? 40 ns data input setup time from dstb <14> t sdid (1 + n)t ? 40 ns data input setup time from astb <15> t sasid (1.5 + n)t ? 51 ns delay time from astb to dstb <16> t dstd 0.5t ? 15 ns data input hold time (from dstb ) <17> t hdid 0ns address output time from dstb <18> t dda (1 + i)t ? 15 ns delay time from dstb to astb <19> t ddst1 0.5t ? 15 ns delay time from dstb to astb <20> t ddst2 (1.5 + i)t ? 15 ns dstb low-level width <21> t wdl (1 + n)t ? 22 ns astb high-level width <22> t wsth t ? 15 ns data output time from dstb <23> t ddod 10 ns data output setup time (to dstb ) <24> t sodd (1 + n)t ? 25 ns data output hold time (from dstb ) <25> t hdod t ? 20 ns <26> t sawt1 n 1 1.5t ? 40 ns wait setup time (to address) <27> t sawt2 (1.5 + n)t ? 40 ns <28> t hawt1 n 1 (0.5 + n)t ns wait hold time (from address) <29> t hawt2 (1.5 + n)t ns <30> t sstwt1 n 1t ? 32 ns wait setup time (to astb ) <31> t sstwt2 (1 + n)t ? 32 ns <32> t hstwt1 n 1ntns wait hold time (from astb ) <33> t hstwt2 (1 + n)t ns hldrq high-level width <34> t whqh t + 10 ns hldak low-level width <35> t whal t ? 15 ns delay time from hldak to bus output <36> t dhac ? 11 ns delay time from hldrq to hldak <37> t dhqha1 1.5t (2n + 7.5)t + 25 ns delay time from hldrq to hldak <38> t dhqha2 0.5t 1.5t + 25 ns remarks 1. t: 1/f cpu (f cpu : cpu clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. i: number of idle cycles inserted in the bus cycle. 4. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 695 (b) clock asynchronous (t a = ?40 to +85c, portv dd = 3.0 to 4.0 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit address setup time (to astb ) <10> t sast 0.5t ? 23 ns address hold time (from astb ) <11> t hsta 0.5t ? 22 ns delay time from dstb to address float <12> t fda 0ns data input setup time from address <13> t said (2 + n)t ? 55 ns data input setup time from dstb <14> t sdid (1 + n)t ? 50 ns data input setup time from astb <15> t sasid (1.5 + n)t ? 65 ns delay time from astb to dstb <16> t dstd 0.5t ? 15 ns data input hold time (from dstb ) <17> t hdid 0ns address output time from dstb <18> t dda (1 + i)t ? 15 ns delay time from dstb to astb <19> t ddst1 0.5t ? 15 ns delay time from dstb to astb <20> t ddst2 (1.5 + i)t ? 18 ns dstb low-level width <21> t wdl (1 + n)t ? 35 ns astb high-level width <22> t wsth t ? 18 ns data output time from dstb <23> t ddod 20 ns data output setup time (to dstb ) <24> t sodd (1 + n)t ? 35 ns data output hold time (from dstb ) <25> t hdod t ? 30 ns <26> t sawt1 n 1 1.5t ? 55 ns wait setup time (to address) <27> t sawt2 (1.5 + n)t ? 55 ns <28> t hawt1 n 1 (0.5 + n)t ns wait hold time (from address) <29> t hawt2 (1.5 + n)t ns <30> t sstwt1 n 1t ? 45 ns wait setup time (to astb ) <31> t sstwt2 (1 + n)t ? 45 ns <32> t hstwt1 n 1ntns wait hold time (from astb ) <33> t hstwt2 (1 + n)t ns hldrq high-level width <34> t whqh t + 10 ns hldak low-level width <35> t whal t ? 25 ns delay time from hldak to bus output <36> t dhac ? 13 ns delay time from hldrq to hldak <37> t dhqha1 (2n + 7.5)t + 25 ns delay time from hldrq to hldak <38> t dhqha2 0.5t 1.5t + 25 ns remarks 1. t: 1/f cpu (f cpu : cpu clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. i: number of idle cycles inserted in the bus cycle. 4. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
chapter 20 electrical specifications 696 user ? s manual u15109ej3v0ud (c) clock synchronous (t a = ?40 to +85c, v dd = 4.0 to 5.5 v, portv dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit delay time from clkout to address <39> t dka 025ns delay time from clkout to address float <40> t fka ? 12 10 ns delay time from clkout to astb <41> t dkst 019ns delay time from clkout to dstb <42> t dkd 019ns data input setup time (to clkout ) <43> t sidk 20 ns data input hold time (from clkout ) <44> t hkid 5ns delay time from clkout to data output <45> t dkod 19 ns wait setup time (to clkout ) <46> t swtk 20 ns wait hold time (from clkout ) <47> t hkwt 5ns hldrq setup time (to clkout ) <48> t shqk 20 ns hldrq hold time (from clkout ) <49> t hkhq 5ns delay time from clkout to address float (during bus hold) <50> t dkf 19 ns delay time from clkout to hldak <51> t dkha 19 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (d) clock synchronous (t a = ?40 to +85c, portv dd = 3.0 to 4.0 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit delay time from clkout to address <39> t dka 040ns delay time from clkout to address float <40> t fka ? 16 10 ns delay time from clkout to astb <41> t dkst 030ns delay time from clkout to dstb <42> t dkd 030ns data input setup time (to clkout ) <43> t sidk 20 ns data input hold time (from clkout ) <44> t hkid 5ns delay time from clkout to data output <45> t dkod 40 ns wait setup time (to clkout ) <46> t swtk 24 ns wait hold time (from clkout ) <47> t hkwt 5ns hldrq setup time (to clkout ) <48> t shqk 24 ns hldrq hold time (from clkout ) <49> t hkhq 5ns delay time from clkout to address float (during bus hold) <50> t dkf 19 ns delay time from clkout to hldak <51> t dkha 35 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 697 (e) read cycle (clkout synchronous/asynchronous, 1 wait) clkout (output) astb (output) t1 t2 tw <39> < 16 > < 21 > < 46 > dstb (output) wait (input) ad0 to ad15 (i/o) < 40 > < 10 > < 44 > < 41 > t3 < 43 > < 13 > < 22 > < 17 > < 14 > < 20 > < 18 > < 19 > < 42 > < 12 > < 30 > < 32 > < 26 > < 28 > < 27 > < 29 > < 31 > < 47 > < 46 > < 47 > data address < 41 > < 11 > < 42 > < 33 > a16 to a21 (output) note (output) < 15 > note r/w, uben, lben remark broken lines indicate high impedance.
chapter 20 electrical specifications 698 user ? s manual u15109ej3v0ud (f) write cycle (clkout synchronous/asynchronous, 1 wait) clkout (output) astb (output) t1 t2 tw <39> < 16 > < 21 > < 46 > a16 to a21 (output) note (output) dstb (output) wait (input) ad0 to ad15 (i/o) < 45 > < 10 > < 41 > t3 < 22 > < 24 > < 25 > < 19 > < 42 > < 23 > < 30 > < 32 > < 26 > < 28 > < 27 > < 29 > < 31 > < 47 > < 46 > < 47 > data address < 41 > < 11 > < 42 > < 33 > note r/w, uben, lben remark broken lines indicate high impedance.
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 699 (g) bus hold timing clkout (output) th < 48 >< 49 > th th th ti < 48 > < 37 > < 51 >< 51 > <35> < 38 > <34> <50> <36> a16 to a19 (output) note (output) hldrq (input) hldak (output) astb (output) dstb (output) ad0 to ad15 (i/o) data note r/w, uben, lben remark broken lines indicate high impedance.
chapter 20 electrical specifications 700 user ? s manual u15109ej3v0ud (5) interrupt timing (t a = ? 40 to +85 c, portv dd = 3.0 to 5.0 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit nmi high-level width <52> t wnih 500 ns nmi low-level width <53> t wnil 500 ns n = 0 to 3, 7 to 9, analog noise elimination 500 ns n = 4, 5, digital noise elimination 3t + 20 ns intpn high-level width <54> t with n = 6, digital noise elimination 3tsmp + 20 ns <55> t witl n = 0 to 3, 7 to 9, analog noise elimination 500 ns n = 4, 5, digital noise elimination 3t + 20 ns intpn low-level width n = 6, digital noise elimination 3tsmp + 20 ns remarks 1. t = 1/f xx 2. tsmp: noise elimination sampling clock cycle <52> <53> nmi (input) <54> <55> intpn (input) remark n = 0 to 9
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 701 (6) tin timing (t a = ? 40 to +85 c, portv dd = 3.0 to 5.5 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit tin0, tin1 high-level width <56> t tihn n = 0, 1, 7 to 12 2t sam + 20 note ns tin0, tin1 low-level width <57> t tiln n = 0, 1, 7 to 12 2t sam + 20 note ns tim high-level width <58> t tihm m = 5, 6 3t + 20 ns tim low-level width <59> t tilm m = 5, 6 3t + 20 ns note the following cycles can be selected for t sam (count clock cycle) by setting the prmn2 to prmn0 bits of prescaler mode registers n0 and n1 (prmn0, prmn1). when n = 0 (tm0), t sam = 2t, 4t, 16t, 64t, 256t, or 1/intwtni cycle when n = 1, 7 (tm1, tm7), t sam = 2t, 4t, 16t, 32t, 128t, or 256t cycle when n = 8, 10, 12 (tm8, tm10, tm12), t sam = 2t, 8t, 16t, 32t, 128t, or 256t cycle when n = 9, 11, (tm9, tm11), t sam = 4t, 8t, 32t, 64t, 128t or 512t cycle however, when the tin0 valid edge is selected as the count clock, t sam = 4t. remark t: 1/f xx <56> <57> tin0, tin1 (input) <58> <59> tim (input) remark n = 0, 1, 7 to 12 m = 5, 6
chapter 20 electrical specifications 702 user ? s manual u15109ej3v0ud (7) asynchronous serial interface (uart0 to uart3) timing (t a = ? 40 to +85 c, portv dd = 3.0 to 5.5 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit asckn cycle time <60> t kcy13 200 ns asckn high-level width <61> t kh13 80 ns asckn low-level width <62> t kl13 80 ns remark n = 0 to 3 <63> <62> <60> asckn (input) remark n = 0 to 3
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 703 (8) 3-wire serial interface (csi0, csi2, csi3) timing (t a = ? 40 to +85 c, portv dd = 3.0 to 5.5 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v) (a) master mode parameter symbol conditions min. max. unit sckn cycle <63> t kcy1 400 ns sckn high-level width <64> t kh1 140 ns sckn low-level width <65> t kl1 140 ns sin setup time (to sckn ) <66> t sik1 50 ns sin hold time (from sckn ) <67> t ksi1 50 ns ns delay time from sckn to son output <68> t kso1 60 ns remark n = 0, 2, 3 (b) slave mode parameter symbol conditions min. max. unit sckn cycle <63> t kcy2 400 ns sckn high-level width <64> t kh2 140 ns sckn low-level width <65> t kl2 140 ns sin setup time (to sckn ) <66> t sik2 50 ns sin hold time (from sckn ) <67> t ksi2 50 ns note 1 80 ns delay time from sckn to son output <68> t kso2 note 2 100 ns notes 1. portv dd = 4.0 to 5.5 v 2. portv dd = 3.0 to 4.0 v remark n = 0, 2, 3
chapter 20 electrical specifications 704 user ? s manual u15109ej3v0ud <67> <68> <66> <63> <64> <65> remarks 1. broken lines indicate high impedance. 2. n = 0, 2, 3 sckn (i/o) sin (input) son (output) input data output data
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 705 (9) 3-wire variable-length serial interface (csi4) timing (t a = ? 40 to +85 c, portv dd = 3.0 to 5.5 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v) (a) master mode parameter symbol conditions min. max. unit note 1 200 ns sck4 cycle <69> t kcy1 note 2 400 ns note 1 60 ns sck4 high-level width <70> t kh1 note 2 140 ns note 1 60 ns sck4 low-level width <71> t kl1 note 2 140 ns note 1 25 ns si4 setup time (to sck4 ) <72> t sik1 note 2 50 ns si4 hold time (from sck4 ) <73> t ksi1 20 ns delay time from sck4 to so4 output <74> t kso1 55 ns notes 1. portv dd = 4.0 to 5.5 v 2. portv dd = 3.0 to 4.0 v (b) slave mode parameter symbol conditions min. max. unit note 1 200 ns sck4 cycle <69> t kcy2 note 2 400 ns note 1 60 ns sck4 high-level width <70> t kh2 note 2 140 ns note 1 60 ns sck4 low-level width <71> t kl2 note 2 140 ns note 1 25 ns si4 setup time (to sck4 ) <72> t sik2 note 2 50 ns si4 hold time (from sck4 ) <73> t ksi2 20 ns note 1 70 ns delay time from sck4 to so4 output <74> t kso2 note 2 120 ns notes 1. portv dd = 4.0 to 5.5 v 2. portv dd = 3.0 to 4.0 v
chapter 20 electrical specifications 706 user ? s manual u15109ej3v0ud <69> <71> <70> <72> <73> <74> si4 (input) so4 (output) sck4 (i/o) output data input data remark broken lines indicate high impedance.
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 707 (10) 3-wire serial interface (csi5, csi6) timing (t a = ? 40 to +85 c, portv dd = 3.0 to 5.5 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v) (a) master mode parameter symbol conditions min. max. unit note 1 200 ns sckn cycle <75> t kcy1 note 2 400 ns note 1 60 ns sckn high-level width <76> t kh1 note 2 140 ns note 1 60 ns sckn low-level width <77> t kl1 note 2 140 ns note 1 30 ns sin setup time (to sckn ) <78> t sik1 note 2 60 ns sin hold time (from sckn ) <79> t ksi1 30 ns delay time from sckn to son output <80> t kso1 55 ns notes 1. portv dd = 4.0 to 5.5 v 2. portv dd = 3.0 to 4.0 v remark n = 5, 6 (b) slave mode parameter symbol conditions min. max. unit note 1 200 ns sckn cycle <75> t kcy2 note 2 400 ns note 1 60 ns sckn high-level width <76> t kh2 note 2 140 ns note 1 60 ns sckn low-level width <77> t kl2 note 2 140 ns note 1 50 ns sin setup time (to sckn ) <78> t sik2 note 2 100 ns sin hold time (from sckn ) <79> t ksi2 50 ns note 1 70 ns delay time from sckn to son output <80> t kso2 note 2 120 ns notes 1. portv dd = 4.0 to 5.5 v 2. portv dd = 3.0 to 4.0 v remark n = 5, 6
chapter 20 electrical specifications 708 user ? s manual u15109ej3v0ud <75> <77> <76> <78> <79> <80> sin (input) son (output) sckn (i/o) output data input data remarks 1. broken lines indicate high impedance. 2. n = 5, 6
chapter 20 electrical specifications user?s manual u15109ej3v0ud 709 (11) i 2 c interface (i 2 c0, i 2 c1) timing (t a = ?40 to +85c, portv dd = 3.0 to 5.5 v, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v) normal mode high-speed mode parameter symbol min. max. min. max. unit scln clock frequency ? f clk 0 100 0 400 khz bus-free time (between stop/start conditions) <81> t buf 4.7 ? 1.3 ? s hold time note 1 <82> t hd:sta 4.0 ? 0.6 ? s scln clock low-level width <83> t low 4.7 ? 1.3 ? s scln clock high-level width <84> t high 4.0 ? 0.6 ? s setup time for start/restart conditions <85> t su:sta 4.7 ? 0.6 ? s cbus compatible master 5.0 ? ? ? s data hold time i 2 c mode <86> t hd:dat 0 note 2 ?0 note 2 0.9 note 3 s data setup time <87> t su:dat 250 ? 100 note 4 ?ns sdan and scln signal rise time <88> t r ? 1000 20 + 0.1cb note 5 300 ns sdan and scln signal fall time <89> t f ? 300 20 + 0.1cb note 5 300 ns stop condition setup time <90> t su:sto 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter <91> t sp ??050ns capacitance load of each bus line ? cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sdan signal (at v ihmin. . of scln signal) in order to occupy the undefined area at the falling edge of scln. 3. if the system does not extend the scln signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scln signal?s low state hold time: t su : dat 250 ns ? if the system extends the scln signal?s low state hold time: transmit the following data bit to the sdan line prior to the scln line release (t rmax. + t su : dat = 1000 + 250 = 1250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark n = 0, 1
chapter 20 electrical specifications 710 user ? s manual u15109ej3v0ud stop condition start condition restart condition stop condition scln (i/o) sdan (i/o) <82> <81> <83> <84> <88> <89> <86> <87> <85> <82> <91> <90> <89> <88> remark n = 0, 1 a/d converter characteristics (t a = ? 40 to +85 c, v dd = adcv dd = 4.5 to 5.5 v, gnd = adcgnd = 0 v) parameter symbol conditions min. typ. max. unit resolution ? 10 10 10 bit overall error note 1 ? 1.0 %fsr conversion time t conv 510 s zero-scale error note 1 ainl 0.4 %fsr full-scale error note 1 ainl 0.6 %fsr integral linearity error note 2 inl 6.0 lsb differential linearity error note 2 dnl 6.0 lsb analog power supply voltage av dd 4.5 5.5 v analog input voltage v ian 0 adcv dd v adcv dd current ai dd 48ma notes 1. excluding quantization error ( 0.05%fsr) 2. excluding quantization error ( 0.5lsb) remark lsb: least significant bit fsr: full scale range regulator, power-on-clear circuit, 4.5 v detection flag characteristics (t a = ? 40 to +85 c, pd703068y, 703069y, 703088y, 703089y: v dd = 3.5 to 5.5 v, pd70f3089y: v dd = 4.0 to 5.5 v) parameter symbol conditions min. typ. max. unit cpureg output voltage v reg 1 f capacitor connected 3.0 3.3 3.6 v v poch cpu operation 2.7 3.0 3.3 v poc circuit detection voltage v pocl stop mode 1.5 1.8 2.1 v vm45 flag setting voltage vm45 3.7 4.2 4.5 v
chapter 20 electrical specifications user ? s manual u15109ej3v0ud 711 flash memory programming mode ( pd70f3089y only) basic characteristics (t a = ? 20 to +85 ) parameter symbol conditions min. typ. max. unit v dd supply voltage v dd 4.5 5.5 v v pp0 normal operation 0 0.6 v v pp supply voltage v pp1 flash memory programming 7.5 7.8 8.1 v v pp write supply current v ppw v pp = v pp1 50 ma v pp erase supply current i ppe v pp = v pp1 100 ma step erase time t er 0.2 0.2 0.2 s overall erase time per area t era note 1 20 s/area number of rewrites per area c erwr 1 erase + 1 write after erase = 1 rewrite, note 2 100 count/ area notes 1. the prewrite time prior to erasure and the erase verify time (write-back time) are not included. 2. when writing initially to shipped products, it is counted as one rewrite for both ? erase to write ? and ? write only ? . example (p: write, e: erase) shipped product ?? p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remarks 1. the operating clock range during programming flash memory is the same as normal operation. 2. when the pg-fp3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. do not change the settings otherwise specified. 3. area 0 = 00000h to 1ffffh, area 1 = 20000h to 3ffffh, area 2 = 40000h to 5ffffh, area 3= 60000h to 7ffffh
user?s manual u15109ej3v0ud 712 chapter 21 package drawing 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 + 4 ? 3 g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 ? 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b
user?s manual u15109ej3v0ud 713 chapter 22 recommended soldering conditions tbd
714 user?s manual u15109ej3v0ud appendix a register index (1/11) symbol name unit page adcr a/d conversion result register adc 456 adcrh a/d conversion result register h (higher 8 bits) adc 456 adic interrupt control register adc 233 adm1 a/d converter mode register 1 adc 458 adm2 a/d converter mode register 2 adc 460 ads analog input channel specification register adc 460 asim0 asynchronous serial interface mode register 0 uart 437 asim1 asynchronous serial interface mode register 1 uart 437 asim2 asynchronous serial interface mode register 2 uart 437 asim3 asynchronous serial interface mode register 3 uart 437 asis0 asynchronous serial interface status register 0 uart 438 asis1 asynchronous serial interface status register 1 uart 438 asis2 asynchronous serial interface status register 2 uart 438 asis3 asynchronous serial interface status register 3 uart 438 bcc bus cycle control register bcu 206 bcr iebus control register iebus 525 brgc0 baud rate generator control register 0 brg 439 brgc1 baud rate generator control register 1 brg 439 brgc2 baud rate generator control register 2 brg 439 brgc3 baud rate generator control register 3 brg 439 brgck4 baud rate generator output clock select register 4 brg 337 brgcn4 baud rate generator source clock select register 4 brg 336 brgmc00 baud rate generator mode control register 00 brg 440 brgmc01 baud rate generator mode control register 01 brg 440 brgmc10 baud rate generator mode control register 10 brg 440 brgmc11 baud rate generator mode control register 11 brg 440 brgmc20 baud rate generator mode control register 20 brg 440 brgmc21 baud rate generator mode control register 21 brg 440 brgmc30 baud rate generator mode control register 30 brg 440 brgmc31 baud rate generator mode control register 31 brg 440 c1ba can1 bus active register fcan 621 c1brp can1 bit rate prescaler register fcan 622 c1ctrl can1 control register fcan 608 c1def can1 definition register fcan 612 c1dinf can1 bus diagnostic information register fcan 625 c1erc can1 error count register fcan 617
appendix a register index user ? s manual u15109ej3v0ud 715 (2/11) symbol name unit page c1ie can1 interrupt enable register fcan 618 c1intp can1 interrupt pending register fcan 594 c1last can1 information register fcan 616 c1maskh0 can1 address mask 0 register h fcan 606 c1maskh1 can1 address mask 1 register h fcan 606 c1maskh2 can1 address mask 2 register h fcan 606 c1maskh3 can1 address mask 3 register h fcan 606 c1maskl0 can1 address mask 0 register l fcan 606 c1maskl1 can1 address mask 1 register l fcan 606 c1maskl2 can1 address mask 2 register l fcan 606 c1maskl3 can1 address mask 3 register l fcan 606 c1sync can1 synchronization control register fcan 626 c2ba can2 bus active register fcan 621 c2brp can2 bit rate prescaler register fcan 622 c2ctrl can2 control register fcan 608 c2def can2 definition register fcan 612 c2dinf can2 bus diagnostic information register fcan 625 c2erc can2 error count register fcan 617 c2ie can2 interrupt enable register fcan 618 c2intp can2 interrupt pending register fcan 594 c2last can2 information register fcan 616 c2maskh0 can2 address mask 0 register h fcan 606 c2maskh1 can2 address mask 1 register h fcan 606 c2maskh2 can2 address mask 2 register h fcan 606 c2maskh3 can2 address mask 3 register h fcan 606 c2maskl0 can2 address mask 0 register l fcan 606 c2maskl1 can2 address mask 1 register l fcan 606 c2maskl2 can2 address mask 2 register l fcan 606 c2maskl3 can2 address mask 3 register l fcan 606 c2sync can2 synchronization control register fcan 626 canic1 interrupt control register intc 233 canic2 interrupt control register intc 233 canic3 interrupt control register intc 233 canic4 interrupt control register intc 233 canic5 interrupt control register intc 233 canic6 interrupt control register intc 233 canic7 interrupt control register intc 233 ccintp can interrupt pending register fcan 591 ccr iebus transmit counter iebus 543
appendix a register index 716 user ? s manual u15109ej3v0ud (3/11) symbol name unit page cdr iebus control data register iebus 528 cgcs can main clock select register fcan 601 cgie can global interrupt enable register fcan 600 cgintp can global interrupt pending register fcan 593 cgmsr can message search result register fcan 604 cgmss can message search start register fcan 604 cgst can global status register fcan 597 cgtsc can time stamp count register fcan 603 corad0 correction address register 0 cpu 491 corad1 correction address register 1 cpu 491 corad2 correction address register 2 cpu 491 corad3 correction address register 3 cpu 491 corcn correction control register cpu 490 corrq correction request register cpu 490 cr00 16-bit capture/compare register 00 rpu 258 cr01 16-bit capture/compare register 01 rpu 259 cr10 16-bit capture/compare register 10 rpu 258 cr100 16-bit capture/compare register 100 rpu 258 cr101 16-bit capture/compare register 101 rpu 259 cr11 16-bit capture/compare register 11 rpu 259 cr110 16-bit capture/compare register 110 rpu 258 cr111 16-bit capture/compare register 111 rpu 259 cr120 16-bit capture/compare register 120 rpu 258 cr121 16-bit capture/compare register 121 rpu 259 cr5 16-bit compare register 5 rpu 297 cr6 16-bit compare register 6 rpu 297 cr70 16-bit capture/compare register 70 rpu 258 cr71 16-bit capture/compare register 71 rpu 259 cr80 16-bit capture/compare register 80 rpu 258 cr81 16-bit capture/compare register 81 rpu 259 cr90 16-bit capture/compare register 90 rpu 258 cr91 16-bit capture/compare register 91 rpu 259 crc0 capture/compare control register 0 rpu 262 crc1 capture/compare control register 1 rpu 262 crc10 capture/compare control register 10 rpu 262 crc11 capture/compare control register 11 rpu 262 crc12 capture/compare control register 12 rpu 262 crc7 capture/compare control register 7 rpu 262 crc8 capture/compare control register 8 rpu 262
appendix a register index user ? s manual u15109ej3v0ud 717 (4/11) symbol name unit page crc9 capture/compare control register 9 rpu 262 csib4 variable-length serial setting register 4 csi 335 csic0 interrupt control register intc 233 csic2 interrupt control register intc 233 csic3 interrupt control register intc 233 csic4 interrupt control register intc 233 csic5 interrupt control register intc 233 csic6 interrupt control register intc 233 csick5 clocked serial interface clock select register 5 csi 348 csick6 clocked serial interface clock select register 6 csi 348 csim0 serial operation mode register 0 csi 326 csim2 serial operation mode register 2 csi 326 csim3 serial operation mode register 3 csi 326 csim4 variable-length serial control register 4 csi 334 csim5 clocked serial interface mode register 5 csi 346 csim6 clocked serial interface mode register 6 csi 346 csis0 serial clock select register 0 csi 326 csis2 serial clock select register 2 csi 326 csis3 serial clock select register 3 csi 326 cstop can stop register fcan 596 dbc0 dma byte counter register 0 dmac 475 dbc1 dma byte counter register 1 dmac 475 dbc2 dma byte counter register 2 dmac 475 dbc3 dma byte counter register 3 dmac 475 dbc4 dma byte counter register 4 dmac 475 dbc5 dma byte counter register 5 dmac 475 dchc0 dma channel control register 0 dmac 476 dchc1 dma channel control register 1 dmac 476 dchc2 dma channel control register 2 dmac 476 dchc3 dma channel control register 3 dmac 476 dchc4 dma channel control register 4 dmac 476 dchc5 dma channel control register 5 dmac 476 dioa0 dma peripheral i/o address register 0 dmac 473 dioa1 dma peripheral i/o address register 1 dmac 473 dioa2 dma peripheral i/o address register 2 dmac 473 dioa3 dma peripheral i/o address register 3 dmac 473 dioa4 dma peripheral i/o address register 4 dmac 473 dioa5 dma peripheral i/o address register 5 dmac 473
appendix a register index 718 user ? s manual u15109ej3v0ud (5/11) symbol name unit page dlr iebus telegraph length register iebus 532 dmaic0 interrupt control register intc 233 dmaic1 interrupt control register intc 233 dmaic2 interrupt control register intc 233 dmaic3 interrupt control register intc 233 dmaic4 interrupt control register intc 233 dmaic5 interrupt control register intc 233 dmas dma start factor expansion register dmac 475 dr iebus data register iebus 533 dra0 dma internal ram address register 0 dmac 473 dra1 dma internal ram address register 1 dmac 473 dra2 dma internal ram address register 2 dmac 473 dra3 dma internal ram address register 3 dmac 473 dra4 dma internal ram address register 4 dmac 473 dra5 dma internal ram address register 5 dmac 473 dwc data wait control register bcu 204 ecr interrupt source register cpu 89 egn0 falling edge specification register 0 intc 143, 226 egn1 falling edge specification register 1 intc 155, 240 egp0 rising edge specification register 0 intc 142, 226 egp1 rising edge specification register 1 intc 155, 240 iebic1 interrupt control register intc 233 iebic2 interrupt control register intc 233 ieclk iebus clock select register iebus 543 iic0 iic shift register 0 i 2 c 373, 387 iic1 iic shift register 1 i 2 c 373, 387 iicc0 iic control register 0 i 2 c 375 iicc1 iic control register 1 i 2 c 375 iicce0 iic clock expansion register 0 i 2 c 385 iicce1 iic clock expansion register 1 i 2 c 385 iiccl0 iic clock select register 0 i 2 c 385 iiccl1 iic clock select register 1 i 2 c 385 iicf0 iic flag register 0 i 2 c 383 iicf1 iic flag register 1 i 2 c 383 iics0 iic status register 0 i 2 c 380 iics1 iic status register 1 i 2 c 380 iicx0 iic function expansion register 0 i 2 c 385 iicx1 iic function expansion register 1 i 2 c 385 ispr in-service priority register intc 237
appendix a register index user ? s manual u15109ej3v0ud 719 (6/11) symbol name unit page isr iebus interrupt status register iebus 536 kric interrupt control register intc 233 krm key return mode register kr 253 mam memory address output mode register port 105 mm memory expansion mode register port 104 m_conf00 to m_conf31 can message configuration registers 00 to 31 fcan 585 m_ctrl00 to m_ctrl31 can message control registers 00 to 31 fcan 577 m_data000 to m_data317 can message data registers 000 to 317 fcan 581 m_dlc00 to m_dlc31 can message data length registers 00 to 31 fcan 576 m_idh00 to m_idh31 can message id registers h00 to h31 fcan 583 m_idl00 to m_idl31 can message id registers l00 to l31 fcan 583 m_stat00 to m_stat31 can message status registers 00 to 31 fcan 587 m_time00 to m_time31 can message time stamp registers 00 to 31 fcan 579 ncc noise elimination control register intc 239 osts oscillation stabilization time select register wdt 124, 318, 323 p0 port 0 port 140 p1 port 1 port 144 p10 port 10 port 168 p11 port 11 port 171 p12 port 12 port 176 p13 port 13 port 180 p14 port 14 port 182 p15 port 15 port 185 p17 port 17 port 188 p2 port 2 port 149 p3 port 3 port 153 p4 port 4 port 157
appendix a register index 720 user ? s manual u15109ej3v0ud (7/11) symbol name unit page p5 port 5 port 157 p6 port 6 port 160 p7 port 7 port 163 p8 port 8 port 163 p9 port 9 port 165 pac port alternate-function control register port 173 pac2 port alternate-function control register 2 port 177 par iebus partner address register iebus 528 pcc processor clock control register cg 122 pf1 port 1 function register port 145 pf2 port 2 function register port 150 pic0 interrupt control register intc 233 pic1 interrupt control register intc 233 pic2 interrupt control register intc 233 pic3 interrupt control register intc 233 pic4 interrupt control register inyc 233 pic5 interrupt control register intc 233 pic6 interrupt control register intc 233 pic7 interrupt control register intc 233 pm0 port 0 mode register port 142 pm1 port 1 mode register port 145 pm10 port 10 mode register port 169 pm11 port 11 mode register port 172 pm12 port 12 mode register port 177 pm13 port 13 mode register port 180 pm14 port 14 mode register port 183 pm15 port 15 mode register port 186 pm17 port 17 mode register port 189 pm2 port 2 mode register port 150 pm3 port 3 mode register port 154 pm4 port 4 mode register port 158 pm5 port 5 mode register port 158 pm6 port 6 mode register port 161 pm9 port 9 mode register port 166 pocc poc control register reset 487 pocs poc status register reset 486 prcmd command register cg 119 prm00 prescaler mode register 00 rpu 264 prm01 prescaler mode register 01 rpu 264
appendix a register index user ? s manual u15109ej3v0ud 721 (8/11) symbol name unit page prm10 prescaler mode register 10 rpu 266 prm100 prescaler mode register 100 rpu 268 prm101 prescaler mode register 101 rpu 268 prm11 prescaler mode register 11 rpu 266 prm110 prescaler mode register 110 rpu 270 prm111 prescaler mode register 111 rpu 270 prm120 prescaler mode register 120 rpu 268 prm121 prescaler mode register 121 rpu 268 prm70 prescaler mode register 70 rpu 266 prm71 prescaler mode register 71 rpu 266 prm80 prescaler mode register 80 rpu 268 prm81 prescaler mode register 81 rpu 268 prm90 prescaler mode register 90 rpu 270 prm91 prescaler mode register 91 rpu 270 psc power save control register cg 123 psw program status word cpu 90 pu10 pull-up resistor option register 10 port 169 rxb0 receive buffer register 0 uart 435 rxb1 receive buffer register 1 uart 435 rxb2 receive buffer register 2 uart 435 rxb3 receive buffer register 3 uart 435 sar iebus slave address register iebus 528 scr iebus communication success register iebus 542 sc_stat00 to sc_stat31 can status set/clear registers 00 to 31 fcan 589 sio0 serial i/o shift register 0 csi 325 sio2 serial i/o shift register 2 csi 325 sio3 serial i/o shift register 3 csi 325 sio4 variable-length serial i/o shift register 4 csi 332 sio5 serial i/o shift register 5 csi 353 sio6 serial i/o shift register 6 csi 353 siol5 serial i/o shift register l5 csi 353 siol6 serial i/o shift register l6 csi 353 sirb5 clocked serial interface receive buffer register 5 csi 349 sirb6 clocked serial interface receive buffer register 6 csi 349 sirbe5 clocked serial interface read-only receive buffer register 5 csi 350 sirbe6 clocked serial interface read-only receive buffer register 6 csi 350 sirbel5 clocked serial interface read-only receive buffer register l5 csi 350
appendix a register index 722 user ? s manual u15109ej3v0ud (9/11) symbol name unit page sirbel6 clocked serial interface read-only receive buffer register l6 csi 350 sirbl5 clocked serial interface receive buffer register l5 csi 349 sirbl6 clocked serial interface receive buffer register l6 csi 349 sotb5 clocked serial interface transmit buffer register 5 csi 351 sotb6 clocked serial interface transmit buffer register 6 csi 351 sotbf5 clocked serial interface initial transmit buffer register 5 csi 352 sotbf6 clocked serial interface initial transmit buffer register 6 csi 352 sotbfl5 clocked serial interface initial transmit buffer register l5 csi 352 sotbfl6 clocked serial interface initial transmit buffer register l6 csi 352 sotbl5 clocked serial interface transmit buffer register l5 csi 351 sotbl6 clocked serial interface transmit buffer register l6 csi 351 sric2 interrupt control register intc 233 sric3 interrupt control register intc 233 ssr iebus slave status register iebus 541 stic0 interrupt control register intc 233 stic1 interrupt control register intc 233 stic2 interrupt control register intc 233 stic3 interrupt control register intc 233 sva0 slave address register 0 i 2 c 373, 387 sva1 slave address register 1 i 2 c 373, 387 syc system control register port 201 sys system status register cg 119 tcl50 timer clock select register 50 rpu 298 tcl51 timer clock select register 51 rpu 298 tcl60 timer clock select register 60 rpu 298 tcl61 timer clock select register 61 rpu 298 tm0 16-bit timer register 0 rpu 257 tm1 16-bit timer register 1 rpu 257 tm10 16-bit timer register 10 rpu 257 tm11 16-bit timer register 11 rpu 257 tm12 16-bit timer register 12 rpu 257 tm5 16-bit counter 5 rpu 297 tm6 16-bit counter 6 rpu 297 tm7 16-bit timer register 7 rpu 257 tm8 16-bit timer register 8 rpu 257 tm9 16-bit timer register 9 rpu 257 tmc0 16-bit timer mode control register 0 rpu 260 tmc1 16-bit timer mode control register 1 rpu 260 tmc10 16-bit timer mode control register 10 rpu 260
appendix a register index user ? s manual u15109ej3v0ud 723 (10/11) symbol name unit page tmc11 16-bit timer mode control register 11 rpu 260 tmc12 16-bit timer mode control register 12 rpu 260 tmc50 timer mode control register 50 rpu 300 tmc60 timer mode control register 60 rpu 300 tmc7 16-bit timer mode control register 7 rpu 260 tmc8 16-bit timer mode control register 8 rpu 260 tmc9 16-bit timer mode control register 9 rpu 260 tmic00 interrupt control register intc 233 tmic01 interrupt control register intc 233 tmic10 interrupt control register intc 233 tmic100 interrupt control register intc 233 tmic101 interrupt control register intc 233 tmic11 interrupt control register intc 233 tmic110 interrupt control register intc 233 tmic111 interrupt control register intc 233 tmic120 interrupt control register intc 233 tmic121 interrupt control register intc 233 tmic5 interrupt control register intc 233 tmic6 interrupt control register intc 233 tmic70 interrupt control register intc 233 tmic71 interrupt control register intc 233 tmic80 interrupt control register intc 233 tmic81 interrupt control register intc 233 tmic90 interrupt control register intc 233 tmic91 interrupt control register intc 233 toc0 timer output control register 0 rpu 262 toc1 timer output control register 1 rpu 262 toc10 timer output control register 10 rpu 262 toc11 timer output control register 11 rpu 262 toc12 timer output control register 12 rpu 262 toc7 timer output control register 7 rpu 262 toc8 timer output control register 8 rpu 262 toc9 timer output control register 9 rpu 262 txs0 transmit shift register 0 uart 435 txs1 transmit shift register 1 uart 435 txs2 transmit shift register 2 uart 435 txs3 transmit shift register 3 uart 435 uar iebus unit address register iebus 528 usr iebus unit status register iebus 534
appendix a register index 724 user ? s manual u15109ej3v0ud (11/11) symbol name unit page vm45c vm45 control register reset 487 wdcs watchdog timer clock select register wdt 319 wdtic interrupt control register intc 233 wdtm watchdog timer mode register wdt 238, 320 wtncs watch timer clock select register wt 312 wtnhc watch timer high-speed clock select register wt 312 wtnic interrupt control register intc 233 wtniic interrupt control register intc 233 wtnm watch timer mode control register wt 311
user?s manual u15109ej3v0ud 725 appendix b list of instruction sets ? how to read instruction set list mnemonic operand op code operation flag cy ov s z sat this column shows instruction groups. instructions are divided into each instruction group and described. this column shows instruction mnemonics. this column shows instruction operands (refer to table b-1 ). this column shows instruction operations (refer to table b-3 ). this column shows flag statuses (refer to table b-4 ). this column shows instruction codes (op code) in binary format. 32-bit instructions are displayed in 2 lines (refer to table b-2 ). instruction group table b-1. symbols in operand description symbol description reg1 general-purpose register (r0 to r31): used as source register reg2 general-purpose register (r0 to r31): mainly used as destination register ep element pointer (r30) bit#3 3-bit data for bit number specification imm -bit immediate data disp -bit displacement regid system register number vector 5-bit data that specifies trap vector number (00h to 1fh) cccc 4-bit data that indicates c ondition code
appendix b list of instruction sets user ? s manual u15109ej3v0ud 726 table b-2. symbols used for op code symbol description r 1-bit data of code that specifies reg1 or regid r 1-bit data of code that specifies reg2 d 1-bit data of displacement i 1-bit data of immediate data cccc 4-bit data that indicates c ondition code bbb 3-bit data that specifies bit number table b-3. symbols used for operation description symbol description assignment gr[ ] general-purpose register sr[ ] system register zero-extend (n) zero-extends n to word length. sign-extend (n) sign-extends n to word length. load-memory (a, b) reads data of size b from address a. store-memory (a, b, c) writes data b of size c to address a. load-memory-bit (a, b) reads bit b from address a. store-memory-bit (a, b, c) writes c to bit b of address a saturated (n) performs saturated processing of n. (n is 2 ? s complements). result of calculation of n: if n is n 7fffffffh as result of calculation, 7fffffffh. if n is n 80000000h as result of calculation, 80000000h. result reflects result to a flag. byte byte (8 bits) halfword halfword (16 bits) word word (32 bits) + add ? subtract || bit concatenation multiply divide and logical product or logical sum xor exclusive logical sum not logical negate logically shift left by logical left shift logically shift right by logical right shift arithmetically shift right by arithmetic right shift
appendix b list of instruction sets user ? s manual u15109ej3v0ud 727 table b-4. symbols used for flag operation symbol description (blank) not affected 0 cleared to 0 set of cleared according to result r previously saved value is restored table b-5. condition codes condition name (cond) condition code ( cccc) c onditional expression description v 0000 ov = 1 overflow nv 1000 ov = 0 no overflow c/l 0001 cy = 1 carry lower (less than) nc/nl 1001 cy = 0 no carry no lower (greater than or equal) z/e 0010 z = 1 zero equal nz/ne 1010 z = 0 not zero not equal nh 0011 (cy or z) = 1 not higher (less than or equal) h 1011 (cy or z) = 0 higher (greater than) n 0100 s = 1 negative p 1100 s = 0 positive t 0101 ? always (unconditional) sa 1101 sat = 1 saturated lt 0110 (s xor ov) = 1 less than signed ge 1110 (s xor ov) = 0 greater than or equal signed le 0111 ( (s xor ov) or z) = 1 less than or equal signed gt 1111 ( (s xor ov) or z) = 0 greater than signed
appendix b list of instruction sets 728 user ? s manual u15109ej3v0ud instruction set list (1/4) flag instruction group mnemonic operand op code operation cy ov s z sat sld.b disp7 [ep], reg2 rrrrr0110ddddddd adr ep + zero-extend (disp7) gr [reg2] sign-extend (load-memory (adr, byte)) sld.h disp8 [ep], reg2 rrrrr1000ddddddd ( note 1 ) adr ep + zero-extend (disp8) gr [reg2] sign-extend (load-memory (adr, halfword)) sld.w disp8 [ep], reg2 rrrrr1010dddddd0 ( note 2 ) adr ep + zero-extend (disp8) gr [reg2] load-memory (adr, word) ld.b disp16 [reg1], reg2 rrrrr111000rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) gr [reg2] sign-extend (load-memory (adr, byte)) ld.h disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd0 ( note 3 ) adr gr [reg1] + sign-extend (disp16) gr [reg2] sign-extend (load-memory (adr, halfword)) ld.w disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd1 ( note 3 ) adr gr [reg1] + sign-extend (disp16) gr [reg2] load-memory (adr, word)) sst.b reg2, disp7 [ep] rrrrr0111ddddddd adr ep + zero-extend (disp7) store-memory (adr, gr [reg2], byte) sst.h reg2, disp8 [ep] rrrrr1001ddddddd ( note 1 ) adr ep + zero-extend (disp8) store-memory (adr, gr [reg2], halfword) sst.w reg2, disp8 [ep] rrrrr1010dddddd1 ( note 2 ) adr ep + zero-extend (disp8) store-memory (adr, gr [reg2], word) st.b reg2, disp16 [reg1] rrrrr111010rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], byte) st.h reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd0 ( note 3 ) adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], halfword) load/store st.w reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd1 ( note 3 ) adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], word) mov reg1, reg2 rrrrr000000rrrrr gr [reg2] gr [reg1] mov imm5, reg2 rrrrr010000iiiii gr [reg2] sign-extend (imm5) movhi imm16, reg1, reg2 rrrrr110010rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + (imm16 || 0 16 ) arithmetic operation movea imm16, reg1, reg2 rrrrr110001rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + sign-extend (imm16) notes 1. ddddddd is the higher 7 bits of disp8. 2. dddddd is the higher 6 bits of disp8. 3. ddddddddddddddd is the higher 15 bits of disp16.
appendix b list of instruction sets user ? s manual u15109ej3v0ud 729 instruction set list (2/4) flag instruction group mnemonic operand op code operation cy ov s z sat add reg1, reg2 rrrrr001110rrrrr gr [reg2] gr [reg2] + gr [reg1] add imm5, reg2 rrrrr010010iiiii gr [reg2] gr [reg2] + sign-extend (imm5) addi imm16, reg1, reg2 rrrrr110000rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + sign-extend (imm16) sub reg1, reg2 rrrrr001101rrrrr gr [reg2] gr [reg2] ? gr [reg1] subr reg1, reg2 rrrrr001100rrrrr gr [reg2] gr [reg1] ? gr [reg2] mulh reg1, reg2 rrrrr000111rrrrr gr [reg2] gr [reg2] note gr [reg1] note (signed multiplication) mulh imm5, reg2 rrrrr010111iiiii gr [reg2] gr [reg2] note sign-extend (imm5) (signed multiplication) mulhi imm16, reg1, reg2 rrrrr110111rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] note imm16 (signed multiplication) divh reg1, reg2 rrrrr000010rrrrr gr [reg2] gr [reg2] gr [reg2] note (signed division) cmp reg1, reg2 rrrrr001111rrrrr result gr [reg2] ? gr [reg1] cmp imm5, reg2 rrrrr010011iiiii result gr [reg2] ? sign-extend (imm5) arithmetic operation setf cccc, reg2 rrrrr1111110 cccc 0000000000000000 if conditions are satisfied then gr [reg2] 00000001h else gr [reg2] 00000000h satadd reg1, reg2 rrrrr000110rrrrr gr [reg2] saturated (gr [reg2] + gr [reg1]) satadd imm5, reg2 rrrrr010001iiiii gr [reg2] saturated (gr [reg2] + sign- extend (imm5)) satsub reg1, reg2 rrrrr000101rrrrr gr [reg2] saturated (gr [reg2] ? gr [reg1]) satsubi imm16, reg1, reg2 rrrrr110011rrrrr iiiiiiiiiiiiiiii gr [reg2] saturated (gr [reg1] ? sign- extend (imm16)) saturated operation satsubr reg1, reg2 rrrrr000100rrrrr gr [reg2] saturated (gr [reg1] ? gr [reg2]) tst reg1, reg2 rrrrr001011rrrrr result gr [reg2] and gr [reg1] 0 or reg1, reg2 rrrrr001000rrrrr gr [reg2] gr [reg2] or gr [reg1] 0 ori imm16, reg1, reg2 rrrrr110100rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] or zero-extend (imm16) 0 and reg1, reg2 rrrrr001010rrrrr gr [reg2] gr [reg2] and gr [reg1] 0 logic operation andi imm16, reg1, reg2 rrrrr110110rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] and zero-extend (imm16) 00 note only the lower halfword data is valid.
appendix b list of instruction sets 730 user ? s manual u15109ej3v0ud instruction set list (3/4) flag instruction group mnemonic operand op code operation cy ov s z sat xor reg1, reg2 rrrrr001001rrrrr gr [reg2] gr [reg2] xor gr [reg1] 0 xori imm16, reg1, reg2 rrrrr110101rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] xor zero-extend (imm16) 0 not reg1, reg2 rrrrr000001rrrrr gr [reg2] not (gr [reg1]) 0 shl reg1, reg2 rrrrr111111rrrrr 0000000011000000 gr [reg2] gr [reg2] logically shift left by gr [reg1]) 0 shl imm5, reg2 rrrrr010110iiiii gr [reg2] gr [reg2] logically shift left by zero-extend (imm5) 0 shr reg1, reg2 rrrrr1111111 cccc 0000000010000000 gr [reg2] gr [reg2] logically shift right by gr [reg1] 0 shr imm5, reg2 rrrrr010100iiiii gr [reg2] gr [reg2] logically shift right by zero-extend (imm5) 0 sar reg1, reg2 rrrrr111111rrrrr 0000000010100000 gr [reg2] gr [reg2] arithmetically shift right by gr [reg1] 0 logic operation sar imm5, reg2 rrrrr010101iiiii gr [reg2] gr [reg2] arithmetically shift right by zero-extend (imm5) 0 jmp [reg1] 00000000011rrrrr pc gr [reg1] jr disp22 0000011110dddddd ddddddddddddddd0 ( note 1 ) pc pc + sign-extend (disp22) jarl disp22, reg2 rrrrr11110dddddd ddddddddddddddd0 ( note 1 ) gr [reg2] pc + 4 pc pc + sign-extend (disp22) jump bcond disp9 ddddd1011ddd cccc ( note 2 ) if conditions are satisfied then pc pc + sign-extend (disp9) set1 bit#3, disp16 [reg1] 00bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3) store memory-bit (adr, bit#3, 1) clr1 bit#3, disp16 [reg1] 10bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store memory-bit (adr, bit#3, 0) not1 bit#3, disp16 [reg1] 01bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, z flag) bit manipulate tst1 bit#3, disp16 [reg1] 11bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) notes 1. ddddddddddddddddddddd is the higher 21 bits of dip22. 2. dddddddd is the higher 8 bits of disp9.
appendix b list of instruction sets user ? s manual u15109ej3v0ud 731 instruction set list (4/4) flag instruction group mnemonic operand op code operation cy ov s z sat regid = eipc, fepc regid = eipsw, fepsw ldsr reg2, regid rrrrr111111rrrrr 0000000000100000 ( note ) sr [regid] gr [reg2] regid = psw stsr regid, reg2 rrrrr111111rrrrr 0000000001000000 gr [reg2] sr [regid] trap vector 00000111111iiiii 0000000100000000 eipc pc + 4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (vector = 00h to 0fh) 00000050h (vector = 10h to 1fh) reti 0000011111100000 0000000101000000 if psw.ep = 1 then pc eipc psw eipsw else if psw.np = 1 then pc fepc psw fepsw else pc eipc psw eipsw rrrrr halt 0000011111100000 0000000100100000 stops di 0000011111100000 0000000101100000 psw.id 1 (maskable interrupt disabled) ei 1000011111100000 0000000101100000 psw.id 0 (maskable interrupt enabled) special nop 0000000000000000 uses 1 clock cycle wit hout doing anything note the op code of the ldsr instruction uses the field of reg1 even though the source register is shown as reg2 in the above table. therefore, the meaning of the register specification for the mnemonic description and op code differs to that of the other instructions. rrrrr = regid specification rrrrr = reg2 specification
user?s manual u15109ej3v0ud 732 appendix c revision history the following table shows the revision history up to the previous editions. the ?applied to:? column indicates the chapters of each edition in which the revision was applied. (1/5) edition major revision from previous edition applied to: ? deletion of indication ?under development? for the following products (developed) pd703068ygj- -uen, 703069ygj- -uen ? addition of watch timer high-speed clock select register (wtnhc), iic flag registers 0 and 1 (iicf0, iicf1) throughout change of minimum instruction execution time in 1.4.1 features (v850/sc3) chapter 1 introduction modification of description in table 2-1 pin i/o buffer power supplies modification of description in table 2-3 pin operation states in various operating modes chapter 2 pin functions modification of 3.4.8 peripheral i/o registers addition of remarks in 3.4.9 (2) system status register (sys) chapter 3 cpu functions change of frequency of the v850/sc3 in 4.1 (1) main clock oscillator addition of note and caution in 4.3.1 (1) processor clock control register (pcc) modification of description for setting dclk1 and dclk0 bits = 01b and addition to notes in 4.3.1 (2) power save control register (psc) modification of description on operation status of a16 to a21 pins in table 4-1 operating statuses in halt mode modification of description on operation of uart0 to uart3 in table 4-2 operating statuses in idle mode addition of description in 4.4.4 (1) settings and operating states modification of description on operation status of uart0 to uart3 in table 4-3 operating statuses in software stop mode addition of 4.6 (1) when executing an instruction on internal rom addition of caution in 4.6 (2) when executing an instruction on external rom chapter 4 clock generation function modification of description in table 5-1 pin i/o buffer power supplies addition of caution in 5.2.8 (1) function of p9 pins addition and modification of description in table 5-16 setting when port pin is used for alternate function addition of 5.4 operation of port function chapter 5 port functions addition of note and caution in 6.2.2 (1) system control register (syc) (v850/sc1, v850/sc2) chapter 6 bus control function modification of description in figure 7-2 acknowledging non-maskable interrupt requests addition of 7.8.1 interrupt request valid timing following ei instruction 3rd addition of 7.9 bit manipulation instruction of interrupt control register on dma transfer chapter 7 interrupt/excep tion processing function
appendix c revision history user ? s manual u15109ej3v0ud 733 (2/5) edition major revision from previous edition applied to: addition and modification of description in 8.1.3 (2) capture/compare register n0 (cr00, cr10, cr70 to cr120) addition and modification of description in 8.1.3 (3) capture/compare register n1 (cr01, cr11, cr71 to cr121) addition to cautions in 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (tmc0, tmc1, tmc7 to tmc12) addition to cautions in 8.1.4 (2) capture/compare control registers 0, 1, 7 to 12 (crc0, crc1, crc7 to crc12) addition of figure 8-6 configuration of ppg output and figure 8-7 ppg output operation timing change of description of caution in 8.2.6 (2) one-shot pulse output via external trigger chapter 8 timer/counter function addition of caution in 10.3 (2) watchdog timer clock select register (wdcs) chapter 10 watchdog timer function addition of description in 11.2 (2) 3-wire serial i/o mode (fixed as msb first) addition to cautions in 11.2.2 (1) serial clock select register n (csisn) and serial operation mode register n (csimn) modification of description on manipulatable bits in 11.4.3 (6) clocked serial interface read-only receive buffer registers l5, l6 (sirbel5, sirbel6) modification of description on manipulatable bits in 11.4.3 (8) clocked serial interface transmit buffer registers l5, l6 (sotbl5, sotbl6) modification of description on manipulatable bits in 11.4.3 (10) clocked serial interface initial transmit buffer registers l5, l6 (sotbfl5, sotbfl6) modification of description on manipulatable bits in 11.4.3 (12) serial i/o shift registers l5, l6 (siol5, siol6) modification of description and addition to note in 11.5.2 (1) iic control register 0, 1 (iicc0, iicc1) addition of caution in 11.5.2 (4) iic clock expansion registers 0, 1 (iicce0, iicce1), iic function expansion registers 0, 1 (iicx0, iicx1), iic clock select registers 0, 1 (iiccl0, iiccl1) addition of 11.5.12 (2) when communication reservation function is disabled (iicrsvn of iicfn register = 1) change of description in 11.5.13 cautions change of description in 11.5.14 (1) master operations (1) addition of 11.5.14 (2) master operations (2) addition of description in figure 11-39 slave operation flowchart addition to cautions in 11.6.2 (1) asynchronous serial interface mode registers 0 to 3 (asim0 to asim3) addition to cautions in 11.6.2 (4) baud rate generator mode control registers n0, n1 (brgmcn0, brgmcn1) addition to cautions in figure 11-43 asimn setting (operation stopped mode) 3rd addition to cautions in figure 11-44 asimn setting (asynchronous serial interface mode) chapter 11 serial interface function
appendix c revision history 734 user ? s manual u15109ej3v0ud (3/5) edition major revision from previous edition applied to: addition to cautions in figure 11-47 brgmcn0 and brgmcn1 settings (asynchronous serial interface mode) addition of description in 11.6.3 (3) (d) reception deletion of description in 11.6.3 (3) (e) receive error modification of note in figure 11-52 receive error timing chapter 11 serial interface function modification of caution in 12.2 (2) a/d conversion result register (adcr), a/d conversion result register h (adcrh) addition of caution in 12.3 (2) analog input channel specification register (ads) modification of description in 12.6 (3) <3> conflict between writing of adcr and writing a/d converter mode register 1 (adm1) or analog input channel specification register (ads) modification of description in 12.6 (8) reading out a/d converter result register (adcr) chapter 12 a/d converter addition of 13.3 configuration addition to cautions in 13.4 (6) start factor settings addition of 13.5 operation addition of 13.6 cautions chapter 13 dma functions modification of description in 14.1 (3) internal reset by power-on-clear (poc) modification of description in 14.3 (3) poc control register (pocc) chapter 14 reset f unction addition of figure 17-1 example of wiring of adapter for flash programming (fa- 144gj-uen) addition of table 17-1 table for wiring of adapter for pd70f3089y flash programming (fa-144gj-uen) chapter 17 flash memory ( pd70f3089y) addition of description in table 18-5 control field acknowledge signal output conditions chapter 18 iebus controller (v850/sc2) addition of 19.1 features modification of description in table 19-1 overview of functions change of manipulatable bits and reset values in 19.4.2 list of fcan registers modification of description in 19.5.1 can message data length registers 00 to 31 (m_dlc00 to m_dlc31) modification of description in 19.5.2 can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) addition of description in 19.5.6 can message configuration registers 00 to 31 (m_conf00 to m_conf31) modification of description in 19.5.7 can message status registers 00 to 31 (m_stat00 to m_stat31) modification of description on manipulatable bits and modification of register format and bit description in 19.5.10 can global interrupt pending register (cgintp) modification of description on manipulatable bits and modification of register format in 19.5.11 cann interrupt pending register (cnintp) addition to cautions in 19.5.12 can stop register (cstop) 3rd modification of description on manipulatable bits and modification of bit description in 19.5.13 can global status register (cgst) chapter 19 fcan controller (v850/sc3)
appendix c revision history user?s manual u15109ej3v0ud 735 (4/5) edition major revision from previous edition applied to: modification of description on manipulatable bits and modification of bit description in 19.5.14 can global interrupt enable register (cgie) addition of description in 19.5.15 can main clock select register (cgcs) deletion of caution in figure 19-2 fcan clocks addition of cautions and bit name, and modification of bit description in 19.5.17 can message search start/result register (cgmss/cgmsr) addition of description in 19.5.18 cann address mask a registers l and h (cnmaskla and cnmaskha) addition of description in 19.5.19 cann control register (cnctrl) modification of description on manipulatable bits and modification of bit description in 19.5.20 cann definition register (cndef) modification of description on manipulatable bits and addition of bit description in 19.5.23 cann interrupt enable register (cnie) modification of description in cautions and addition of bit description in 19.5.27 cann synchronization control register (cnsync) addition of caution in 19.7 time stamp function modification of description in 19.8 message processing change of figure 19-10 composition of layers addition of caution in 19.11.7 (2) nominal bit time (8 to 25 time quanta) addition to note in figure 19-25 nominal bit time addition of description in figure 19-28 initialization processing addition of note in figure 19-33 setting of cann synchronization control register (cnsync) addition of description in figure 19-38 message buffer setting addition of figure 19-41 setting of can message status registers 00 to 31 (m_stat00 to m_stat31) addition of figure 19-44 setting receive operation using reception polling addition of figure 19-45 setting of can message search start/result register (cgmss/cgmsr) addition of description in figure 19-49 can stop mode setting addition of description in figure 19-50 clearing can stop mode modification of description in 19.13 rules for correct setting of baud rate addition to cautions in 19.14.2 burst read mode deletion of caution 2 in 19.16 how to shutdown fcan controller addition of <4> and <5> in 19.17 cautions on use chapter 19 fcan controller (v850/sc3) addition of chapter 20 electrical specifications chapter 20 electrical specifications 3rd addition of chapter 21 package drawing chapter 21 package drawing
appendix c revision history 736 user ? s manual u15109ej3v0ud (5/5) edition major revision from previous edition applied to: addition of chapter 22 recommended soldering conditions chapter 22 recommended soldering conditions 3rd addition of appendix c revision history appendix c revision history
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